diff options
Diffstat (limited to 'include')
59 files changed, 1446 insertions, 73 deletions
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 6a01a90425..40080f512b 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -120,8 +120,6 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_ETHPRIME "eTSEC1" -#undef CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define CONFIG_SYS_L2_SIZE (256 << 10) #endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index be571066f2..15cda803cc 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -275,7 +275,6 @@ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ @@ -284,7 +283,6 @@ #define CONFIG_SYS_MMC_ENV_PART 0 #define CONFIG_ENV_OFFSET 0x260000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SYS_MMC_MAX_DEVICE 2 #elif defined(CONFIG_NOR_BOOT) #define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index a08e6bfe08..7bb2bff5d1 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -80,7 +80,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x0 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif /* Network. */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d355b80c2f..9db006880b 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -109,7 +109,6 @@ #endif #ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND 0x120000 #endif diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 531f79ee70..baeca5417d 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -20,7 +20,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 /* eMMC */ #define CONFIG_SYS_MMC_ENV_PART 0 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SYS_BOOTM_LEN SZ_64M diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 1149d55937..9c06f10a2f 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -121,7 +121,6 @@ #define CONFIG_ENV_SIZE (128 << 10) #define CONFIG_ENV_OFFSET 0x680000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index b451c7e7dc..041abb5ac1 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -147,7 +147,6 @@ /* Environment organization */ #define CONFIG_ENV_SIZE (12 * 1024) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (0x010000) #define CONFIG_ENV_OFFSET (0x0d0000) #define CONFIG_ENV_OFFSET_REDUND (0x0e0000) diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index db21a473f1..4ecf8de333 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -444,7 +444,6 @@ DEFAULT_LINUX_BOOT_ENV \ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ @@ -453,7 +452,6 @@ DEFAULT_LINUX_BOOT_ENV \ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x0 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif /* SPI flash. */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index b8437052a9..2feabdd6c6 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -149,7 +149,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Environment configuration. */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SIZE (64 << 10) /* 64 KiB */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index bc0dabb51b..c9c28bef04 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -182,7 +182,6 @@ NANDTGTS \ #if defined(CONFIG_SPI) /* SPI Flash */ /* Environment */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SECT_SIZE) #elif defined(CONFIG_ENV_IS_IN_MMC) @@ -190,7 +189,6 @@ NANDTGTS \ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #elif defined(CONFIG_ENV_IS_IN_NAND) /* No NAND env support in SPL */ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index 19e796edb1..47d7a87728 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -69,7 +69,6 @@ BUR_COMMON_ENV \ /* SPI Flash */ /* Environment */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SECT_SIZE) diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index c6e308b04d..30bd8cb383 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -69,6 +69,5 @@ BUR_COMMON_ENV \ #define CONFIG_ENV_SIZE 0x10000 #define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif /* __CONFIG_BRXRE1_H__ */ diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 13c15bd79f..8141aece41 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -166,7 +166,6 @@ #else #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif /* Network. */ diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 2387f864e3..7368fd85bb 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -37,7 +37,6 @@ #define CONFIG_ENV_OFFSET 0xc0000 /* (in bytes) 768 KB */ #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT /* Enhance our eMMC support / experience. */ #define CONFIG_HSMMC2_8BIT diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 4f99805ee2..801011cf77 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -41,7 +41,6 @@ /* Environment settings */ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_OFFSET (14 * SZ_64K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND \ (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 86c1192035..d4bd88f511 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -138,7 +138,6 @@ /* Environment */ #define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) #define CONFIG_ENV_OFFSET (1024 * 1024) diff --git a/include/configs/display5.h b/include/configs/display5.h index 65dae1f62f..7b171489e3 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -352,7 +352,6 @@ /* The 0x120000 value corresponds to above SPI-NOR memory MAP */ #define CONFIG_ENV_OFFSET (0x120000) #define CONFIG_ENV_SECT_SIZE (SZ_64K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 3487b8ac1b..0ad23ce4b9 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -22,7 +22,6 @@ /* MMC ENV related defines */ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif #if (CONFIG_CONS_INDEX == 1) @@ -84,7 +83,6 @@ #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 #if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ #define CONFIG_ENV_OFFSET 0x1C0000 diff --git a/include/configs/evb_px30.h b/include/configs/evb_px30.h new file mode 100644 index 0000000000..e761c7c519 --- /dev/null +++ b/include/configs/evb_px30.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_PX30_H +#define __EVB_PX30_H + +#include <configs/px30_common.h> + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define CONFIG_SUPPORT_EMMC_RPMB + +#endif diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h index 73ceab0373..bf6c7eaf4c 100644 --- a/include/configs/evb_rk3128.h +++ b/include/configs/evb_rk3128.h @@ -8,7 +8,6 @@ #include <configs/rk3128_common.h> -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #endif diff --git a/include/configs/evb_rk3308.h b/include/configs/evb_rk3308.h new file mode 100644 index 0000000000..4d40606e4b --- /dev/null +++ b/include/configs/evb_rk3308.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_RK3308_H +#define __EVB_RK3308_H + +#include <configs/rk3308_common.h> + +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#undef CONFIG_CONSOLE_SCROLL_LINES +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/firefly_rk3308.h b/include/configs/firefly_rk3308.h new file mode 100644 index 0000000000..2cc7b4a153 --- /dev/null +++ b/include/configs/firefly_rk3308.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __FIREFLY_RK3308_H +#define __FIREFLY_RK3308_H + +#include <configs/rk3308_common.h> + +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#undef CONFIG_CONSOLE_SCROLL_LINES +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index e83a96ad5e..94c5b8daf3 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -41,7 +41,6 @@ #define CONFIG_ENV_OFFSET 0xa0000 #define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index a9d99ec8b7..e0c5f5a626 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -150,4 +150,12 @@ #define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 + #endif diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h new file mode 100644 index 0000000000..8d4a88b332 --- /dev/null +++ b/include/configs/imx8mn_evk.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8MN_EVK_H +#define __IMX8MN_EVK_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE SZ_8K +#endif + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x95fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x00950000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x00940000 + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image.itb\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#endif +#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 829a5c7825..64c968b63b 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -158,8 +158,6 @@ int get_scl(void); #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define KM_FLASH_GPIO_PIN 16 #define CONFIG_KM_UPDATE_UBOOT \ diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index 75480a8a58..f83b98c879 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -56,8 +56,6 @@ #define CONFIG_ENV_OFFSET_REDUND 0x110000 #define CONFIG_ENV_TOTAL_SIZE 0x020000 -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(unsigned long dummy); #endif diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 55bfa0fe59..ff564b27ec 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -99,7 +99,6 @@ /* environment organization */ #define CONFIG_ENV_OFFSET (SZ_1M) #define CONFIG_ENV_SIZE (SZ_8K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index f6746a93ca..fc3896e7d1 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -129,6 +129,5 @@ #define CONFIG_ENV_SIZE (SZ_8K) #define CONFIG_ENV_OFFSET 0x100000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index c685de6551..c75519c195 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -251,7 +251,6 @@ #define CONFIG_ENV_SECT_SIZE (SZ_128K) #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index dd045804ae..2fad2c7a84 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -44,7 +44,6 @@ /* Environment is in SPI flash */ #if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET 0x40000 /* 256K */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_ENV_SECT_SIZE 0x1000 diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 3710a71ae9..ff811569b9 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -33,7 +33,6 @@ /* MMC ENV related defines */ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT /* Enhance our eMMC support / experience. */ #define CONFIG_HSMMC2_8BIT diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 650caaa573..23e491236c 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -23,7 +23,6 @@ /* Environment settings */ #define CONFIG_ENV_SIZE (0x4000) #define CONFIG_ENV_OFFSET (0x80000) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND \ (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 855bc445fe..b9f5ad3260 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -76,7 +76,6 @@ #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_OFFSET (1024 * SZ_1K) #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index 8731d89af2..9a169351a3 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -74,11 +74,9 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 /* Environment organization */ -#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_OFFSET (1024 * SZ_1K) #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h new file mode 100644 index 0000000000..d6c70601dd --- /dev/null +++ b/include/configs/px30_common.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_PX30_COMMON_H +#define __CONFIG_PX30_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 +#define COUNTER_FREQUENCY 24000000 + +/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ +#define CONFIG_IRAM_BASE 0xff020000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00400000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x4000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define GICD_BASE 0xff131000 +#define GICC_BASE 0xff132000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +//#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 +#define SDRAM_BANK_SIZE (2UL << 30) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x08300000\0" \ + "kernel_addr_r=0x00280000\0" \ + "kernel_addr_c=0x03e80000\0" \ + "ramdisk_addr_r=0x0a200000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h new file mode 100644 index 0000000000..a67d3d7d1b --- /dev/null +++ b/include/configs/rk3308_common.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3308_COMMON_H +#define __CONFIG_RK3308_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 +#define CONFIG_IRAM_BASE 0xfff80000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00800000 +#define CONFIG_SYS_LOAD_ADDR 0x00C00800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define COUNTER_FREQUENCY 24000000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 +#define SDRAM_BANK_SIZE (2UL << 30) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x00680000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h new file mode 100644 index 0000000000..5f52c1e4f6 --- /dev/null +++ b/include/configs/rockpro64_rk3399.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com> + */ + +#ifndef __ROCKPRO64_RK3399_H +#define __ROCKPRO64_RK3399_H + +#include <configs/rk3399_common.h> + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h index 4f7ec2d7e9..e1a7d724c1 100644 --- a/include/configs/sksimx6.h +++ b/include/configs/sksimx6.h @@ -56,7 +56,6 @@ #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SIZE) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 3a8ccc3021..e1a48715fb 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_BOOTCOUNT_BE /* Environment setting for SPI flash */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_OFFSET 0x000e0000 diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index debf3ea94b..abde883487 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -195,7 +195,6 @@ "fi\0" \ "socfpga_legacy_reset_compat=1\0" -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_OFFSET 0x100000 diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index 0c563e714d..2d7be7d5b9 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -23,7 +23,6 @@ #define CONFIG_BMP_16BPP /* Environment settings */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #undef CONFIG_ENV_SIZE #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x1000 diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index 5adae68c91..f8a55a2cec 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -12,6 +12,7 @@ #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 13e3d60bfe..3c1d629d25 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -148,7 +148,6 @@ #define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ TQMA6_UBOOT_SECTOR_COUNT) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE) #define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 8c68372026..7ed9524359 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -30,7 +30,6 @@ #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index 3eca34fbf7..692e5fc8cb 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -370,19 +370,6 @@ int pinctrl_request_noflags(struct udevice *dev, int func); int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph); /** - * pinctrl_decode_pin_config() - decode pin configuration flags - * - * This decodes some of the PIN_CONFIG values into flags, with each value - * being (1 << pin_cfg). This does not support things with values like the - * slew rate. - * - * @blob: Device tree blob - * @node: Node containing the PIN_CONFIG values - * @return decoded flag value, or -ve on error - */ -int pinctrl_decode_pin_config(const void *blob, int node); - -/** * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO * * This allows the raw mux value for a GPIO to be obtained. It is diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h new file mode 100644 index 0000000000..5255b1c242 --- /dev/null +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H +#define __DT_BINDINGS_CLOCK_IMX8MN_H + +#define IMX8MN_CLK_DUMMY 0 +#define IMX8MN_CLK_32K 1 +#define IMX8MN_CLK_24M 2 +#define IMX8MN_OSC_HDMI_CLK 3 +#define IMX8MN_CLK_EXT1 4 +#define IMX8MN_CLK_EXT2 5 +#define IMX8MN_CLK_EXT3 6 +#define IMX8MN_CLK_EXT4 7 +#define IMX8MN_AUDIO_PLL1_REF_SEL 8 +#define IMX8MN_AUDIO_PLL2_REF_SEL 9 +#define IMX8MN_VIDEO_PLL1_REF_SEL 10 +#define IMX8MN_DRAM_PLL_REF_SEL 11 +#define IMX8MN_GPU_PLL_REF_SEL 12 +#define IMX8MN_VPU_PLL_REF_SEL 13 +#define IMX8MN_ARM_PLL_REF_SEL 14 +#define IMX8MN_SYS_PLL1_REF_SEL 15 +#define IMX8MN_SYS_PLL2_REF_SEL 16 +#define IMX8MN_SYS_PLL3_REF_SEL 17 +#define IMX8MN_AUDIO_PLL1 18 +#define IMX8MN_AUDIO_PLL2 19 +#define IMX8MN_VIDEO_PLL1 20 +#define IMX8MN_DRAM_PLL 21 +#define IMX8MN_GPU_PLL 22 +#define IMX8MN_VPU_PLL 23 +#define IMX8MN_ARM_PLL 24 +#define IMX8MN_SYS_PLL1 25 +#define IMX8MN_SYS_PLL2 26 +#define IMX8MN_SYS_PLL3 27 +#define IMX8MN_AUDIO_PLL1_BYPASS 28 +#define IMX8MN_AUDIO_PLL2_BYPASS 29 +#define IMX8MN_VIDEO_PLL1_BYPASS 30 +#define IMX8MN_DRAM_PLL_BYPASS 31 +#define IMX8MN_GPU_PLL_BYPASS 32 +#define IMX8MN_VPU_PLL_BYPASS 33 +#define IMX8MN_ARM_PLL_BYPASS 34 +#define IMX8MN_SYS_PLL1_BYPASS 35 +#define IMX8MN_SYS_PLL2_BYPASS 36 +#define IMX8MN_SYS_PLL3_BYPASS 37 +#define IMX8MN_AUDIO_PLL1_OUT 38 +#define IMX8MN_AUDIO_PLL2_OUT 39 +#define IMX8MN_VIDEO_PLL1_OUT 40 +#define IMX8MN_DRAM_PLL_OUT 41 +#define IMX8MN_GPU_PLL_OUT 42 +#define IMX8MN_VPU_PLL_OUT 43 +#define IMX8MN_ARM_PLL_OUT 44 +#define IMX8MN_SYS_PLL1_OUT 45 +#define IMX8MN_SYS_PLL2_OUT 46 +#define IMX8MN_SYS_PLL3_OUT 47 +#define IMX8MN_SYS_PLL1_40M 48 +#define IMX8MN_SYS_PLL1_80M 49 +#define IMX8MN_SYS_PLL1_100M 50 +#define IMX8MN_SYS_PLL1_133M 51 +#define IMX8MN_SYS_PLL1_160M 52 +#define IMX8MN_SYS_PLL1_200M 53 +#define IMX8MN_SYS_PLL1_266M 54 +#define IMX8MN_SYS_PLL1_400M 55 +#define IMX8MN_SYS_PLL1_800M 56 +#define IMX8MN_SYS_PLL2_50M 57 +#define IMX8MN_SYS_PLL2_100M 58 +#define IMX8MN_SYS_PLL2_125M 59 +#define IMX8MN_SYS_PLL2_166M 60 +#define IMX8MN_SYS_PLL2_200M 61 +#define IMX8MN_SYS_PLL2_250M 62 +#define IMX8MN_SYS_PLL2_333M 63 +#define IMX8MN_SYS_PLL2_500M 64 +#define IMX8MN_SYS_PLL2_1000M 65 + +/* CORE CLOCK ROOT */ +#define IMX8MN_CLK_A53_SRC 66 +#define IMX8MN_CLK_GPU_CORE_SRC 67 +#define IMX8MN_CLK_GPU_SHADER_SRC 68 +#define IMX8MN_CLK_A53_CG 69 +#define IMX8MN_CLK_GPU_CORE_CG 70 +#define IMX8MN_CLK_GPU_SHADER_CG 71 +#define IMX8MN_CLK_A53_DIV 72 +#define IMX8MN_CLK_GPU_CORE_DIV 73 +#define IMX8MN_CLK_GPU_SHADER_DIV 74 + +/* BUS CLOCK ROOT */ +#define IMX8MN_CLK_MAIN_AXI 75 +#define IMX8MN_CLK_ENET_AXI 76 +#define IMX8MN_CLK_NAND_USDHC_BUS 77 +#define IMX8MN_CLK_DISP_AXI 78 +#define IMX8MN_CLK_DISP_APB 79 +#define IMX8MN_CLK_USB_BUS 80 +#define IMX8MN_CLK_GPU_AXI 81 +#define IMX8MN_CLK_GPU_AHB 82 +#define IMX8MN_CLK_NOC 83 +#define IMX8MN_CLK_AHB 84 +#define IMX8MN_CLK_AUDIO_AHB 85 + +/* IPG CLOCK ROOT */ +#define IMX8MN_CLK_IPG_ROOT 86 +#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 + +/* IP */ +#define IMX8MN_CLK_DRAM_CORE 88 +#define IMX8MN_CLK_DRAM_ALT 89 +#define IMX8MN_CLK_DRAM_APB 90 +#define IMX8MN_CLK_DRAM_ALT_ROOT 91 +#define IMX8MN_CLK_DISP_PIXEL 92 +#define IMX8MN_CLK_SAI2 93 +#define IMX8MN_CLK_SAI3 94 +#define IMX8MN_CLK_SAI5 95 +#define IMX8MN_CLK_SAI6 96 +#define IMX8MN_CLK_SPDIF1 97 +#define IMX8MN_CLK_ENET_REF 98 +#define IMX8MN_CLK_ENET_TIMER 99 +#define IMX8MN_CLK_ENET_PHY_REF 100 +#define IMX8MN_CLK_NAND 101 +#define IMX8MN_CLK_QSPI 102 +#define IMX8MN_CLK_USDHC1 103 +#define IMX8MN_CLK_USDHC2 104 +#define IMX8MN_CLK_I2C1 105 +#define IMX8MN_CLK_I2C2 106 +#define IMX8MN_CLK_I2C3 107 +#define IMX8MN_CLK_I2C4 118 +#define IMX8MN_CLK_UART1 119 +#define IMX8MN_CLK_UART2 110 +#define IMX8MN_CLK_UART3 111 +#define IMX8MN_CLK_UART4 112 +#define IMX8MN_CLK_USB_CORE_REF 113 +#define IMX8MN_CLK_USB_PHY_REF 114 +#define IMX8MN_CLK_ECSPI1 115 +#define IMX8MN_CLK_ECSPI2 116 +#define IMX8MN_CLK_PWM1 117 +#define IMX8MN_CLK_PWM2 118 +#define IMX8MN_CLK_PWM3 119 +#define IMX8MN_CLK_PWM4 120 +#define IMX8MN_CLK_WDOG 121 +#define IMX8MN_CLK_WRCLK 122 +#define IMX8MN_CLK_CLKO1 123 +#define IMX8MN_CLK_CLKO2 124 +#define IMX8MN_CLK_DSI_CORE 125 +#define IMX8MN_CLK_DSI_PHY_REF 126 +#define IMX8MN_CLK_DSI_DBI 127 +#define IMX8MN_CLK_USDHC3 128 +#define IMX8MN_CLK_CAMERA_PIXEL 129 +#define IMX8MN_CLK_CSI1_PHY_REF 130 +#define IMX8MN_CLK_CSI2_PHY_REF 131 +#define IMX8MN_CLK_CSI2_ESC 132 +#define IMX8MN_CLK_ECSPI3 133 +#define IMX8MN_CLK_PDM 134 +#define IMX8MN_CLK_SAI7 135 + +#define IMX8MN_CLK_ECSPI1_ROOT 136 +#define IMX8MN_CLK_ECSPI2_ROOT 137 +#define IMX8MN_CLK_ECSPI3_ROOT 138 +#define IMX8MN_CLK_ENET1_ROOT 139 +#define IMX8MN_CLK_GPIO1_ROOT 140 +#define IMX8MN_CLK_GPIO2_ROOT 141 +#define IMX8MN_CLK_GPIO3_ROOT 142 +#define IMX8MN_CLK_GPIO4_ROOT 143 +#define IMX8MN_CLK_GPIO5_ROOT 144 +#define IMX8MN_CLK_I2C1_ROOT 145 +#define IMX8MN_CLK_I2C2_ROOT 146 +#define IMX8MN_CLK_I2C3_ROOT 147 +#define IMX8MN_CLK_I2C4_ROOT 148 +#define IMX8MN_CLK_MU_ROOT 149 +#define IMX8MN_CLK_OCOTP_ROOT 150 +#define IMX8MN_CLK_PWM1_ROOT 151 +#define IMX8MN_CLK_PWM2_ROOT 152 +#define IMX8MN_CLK_PWM3_ROOT 153 +#define IMX8MN_CLK_PWM4_ROOT 154 +#define IMX8MN_CLK_QSPI_ROOT 155 +#define IMX8MN_CLK_NAND_ROOT 156 +#define IMX8MN_CLK_SAI2_ROOT 157 +#define IMX8MN_CLK_SAI2_IPG 158 +#define IMX8MN_CLK_SAI3_ROOT 159 +#define IMX8MN_CLK_SAI3_IPG 160 +#define IMX8MN_CLK_SAI5_ROOT 161 +#define IMX8MN_CLK_SAI5_IPG 162 +#define IMX8MN_CLK_SAI6_ROOT 163 +#define IMX8MN_CLK_SAI6_IPG 164 +#define IMX8MN_CLK_SAI7_ROOT 165 +#define IMX8MN_CLK_SAI7_IPG 166 +#define IMX8MN_CLK_SDMA1_ROOT 167 +#define IMX8MN_CLK_SDMA2_ROOT 168 +#define IMX8MN_CLK_UART1_ROOT 169 +#define IMX8MN_CLK_UART2_ROOT 170 +#define IMX8MN_CLK_UART3_ROOT 171 +#define IMX8MN_CLK_UART4_ROOT 172 +#define IMX8MN_CLK_USB1_CTRL_ROOT 173 +#define IMX8MN_CLK_USDHC1_ROOT 174 +#define IMX8MN_CLK_USDHC2_ROOT 175 +#define IMX8MN_CLK_WDOG1_ROOT 176 +#define IMX8MN_CLK_WDOG2_ROOT 177 +#define IMX8MN_CLK_WDOG3_ROOT 178 +#define IMX8MN_CLK_GPU_BUS_ROOT 179 +#define IMX8MN_CLK_ASRC_ROOT 180 +#define IMX8MN_CLK_GPU3D_ROOT 181 +#define IMX8MN_CLK_PDM_ROOT 182 +#define IMX8MN_CLK_PDM_IPG 183 +#define IMX8MN_CLK_DISP_AXI_ROOT 184 +#define IMX8MN_CLK_DISP_APB_ROOT 185 +#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 +#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 +#define IMX8MN_CLK_USDHC3_ROOT 188 +#define IMX8MN_CLK_SDMA3_ROOT 189 +#define IMX8MN_CLK_TMU_ROOT 190 +#define IMX8MN_CLK_ARM 191 +#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 +#define IMX8MN_CLK_GPU_CORE_ROOT 193 + +#define IMX8MN_CLK_END 194 + +#endif diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h new file mode 100644 index 0000000000..e5e59690b5 --- /dev/null +++ b/include/dt-bindings/clock/px30-cru.h @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine <zhangqing@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_NPLL 4 +#define APLL_BOOST_H 5 +#define APLL_BOOST_L 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define USB480M 14 +#define SCLK_PDM 15 +#define SCLK_I2S0_TX 16 +#define SCLK_I2S0_TX_OUT 17 +#define SCLK_I2S0_RX 18 +#define SCLK_I2S0_RX_OUT 19 +#define SCLK_I2S1 20 +#define SCLK_I2S1_OUT 21 +#define SCLK_I2S2 22 +#define SCLK_I2S2_OUT 23 +#define SCLK_UART1 24 +#define SCLK_UART2 25 +#define SCLK_UART3 26 +#define SCLK_UART4 27 +#define SCLK_UART5 28 +#define SCLK_I2C0 29 +#define SCLK_I2C1 30 +#define SCLK_I2C2 31 +#define SCLK_I2C3 32 +#define SCLK_I2C4 33 +#define SCLK_PWM0 34 +#define SCLK_PWM1 35 +#define SCLK_SPI0 36 +#define SCLK_SPI1 37 +#define SCLK_TIMER0 38 +#define SCLK_TIMER1 39 +#define SCLK_TIMER2 40 +#define SCLK_TIMER3 41 +#define SCLK_TIMER4 42 +#define SCLK_TIMER5 43 +#define SCLK_TSADC 44 +#define SCLK_SARADC 45 +#define SCLK_OTP 46 +#define SCLK_OTP_USR 47 +#define SCLK_CRYPTO 48 +#define SCLK_CRYPTO_APK 49 +#define SCLK_DDRC 50 +#define SCLK_ISP 51 +#define SCLK_CIF_OUT 52 +#define SCLK_RGA_CORE 53 +#define SCLK_VOPB_PWM 54 +#define SCLK_NANDC 55 +#define SCLK_SDIO 56 +#define SCLK_EMMC 57 +#define SCLK_SFC 58 +#define SCLK_SDMMC 59 +#define SCLK_OTG_ADP 60 +#define SCLK_GMAC_SRC 61 +#define SCLK_GMAC 62 +#define SCLK_GMAC_RX_TX 63 +#define SCLK_MAC_REF 64 +#define SCLK_MAC_REFOUT 65 +#define SCLK_MAC_OUT 66 +#define SCLK_SDMMC_DRV 67 +#define SCLK_SDMMC_SAMPLE 68 +#define SCLK_SDIO_DRV 69 +#define SCLK_SDIO_SAMPLE 70 +#define SCLK_EMMC_DRV 71 +#define SCLK_EMMC_SAMPLE 72 +#define SCLK_GPU 73 +#define SCLK_PVTM 74 +#define SCLK_CORE_VPU 75 +#define SCLK_GMAC_RMII 76 +#define SCLK_UART2_SRC 77 +#define SCLK_NANDC_DIV 78 +#define SCLK_NANDC_DIV50 79 +#define SCLK_SDIO_DIV 80 +#define SCLK_SDIO_DIV50 81 +#define SCLK_EMMC_DIV 82 +#define SCLK_EMMC_DIV50 83 + +/* dclk gates */ +#define DCLK_VOPB 150 +#define DCLK_VOPL 151 + +/* aclk gates */ +#define ACLK_GPU 170 +#define ACLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_VI_PRE 173 +#define ACLK_VO_PRE 174 +#define ACLK_VPU 175 +#define ACLK_PERI_PRE 176 +#define ACLK_GMAC 178 +#define ACLK_CIF 179 +#define ACLK_ISP 180 +#define ACLK_VOPB 181 +#define ACLK_VOPL 182 +#define ACLK_RGA 183 +#define ACLK_GIC 184 +#define ACLK_DCF 186 +#define ACLK_DMAC 187 + +/* hclk gates */ +#define HCLK_BUS_PRE 240 +#define HCLK_CRYPTO 241 +#define HCLK_VI_PRE 242 +#define HCLK_VO_PRE 243 +#define HCLK_VPU 244 +#define HCLK_PERI_PRE 245 +#define HCLK_MMC_NAND 246 +#define HCLK_SDMMC 247 +#define HCLK_USB 248 +#define HCLK_CIF 249 +#define HCLK_ISP 250 +#define HCLK_VOPB 251 +#define HCLK_VOPL 252 +#define HCLK_RGA 253 +#define HCLK_NANDC 254 +#define HCLK_SDIO 255 +#define HCLK_EMMC 256 +#define HCLK_SFC 257 +#define HCLK_OTG 258 +#define HCLK_HOST 259 +#define HCLK_HOST_ARB 260 +#define HCLK_PDM 261 +#define HCLK_I2S0 262 +#define HCLK_I2S1 263 +#define HCLK_I2S2 264 + +/* pclk gates */ +#define PCLK_BUS_PRE 320 +#define PCLK_DDR 321 +#define PCLK_VO_PRE 322 +#define PCLK_GMAC 323 +#define PCLK_MIPI_DSI 324 +#define PCLK_MIPIDSIPHY 325 +#define PCLK_MIPICSIPHY 326 +#define PCLK_USB_GRF 327 +#define PCLK_DCF 328 +#define PCLK_UART1 329 +#define PCLK_UART2 330 +#define PCLK_UART3 331 +#define PCLK_UART4 332 +#define PCLK_UART5 333 +#define PCLK_I2C0 334 +#define PCLK_I2C1 335 +#define PCLK_I2C2 336 +#define PCLK_I2C3 337 +#define PCLK_I2C4 338 +#define PCLK_PWM0 339 +#define PCLK_PWM1 340 +#define PCLK_SPI0 341 +#define PCLK_SPI1 342 +#define PCLK_SARADC 343 +#define PCLK_TSADC 344 +#define PCLK_TIMER 345 +#define PCLK_OTP_NS 346 +#define PCLK_WDT_NS 347 +#define PCLK_GPIO1 348 +#define PCLK_GPIO2 349 +#define PCLK_GPIO3 350 +#define PCLK_ISP 351 +#define PCLK_CIF 352 +#define PCLK_OTP_PHY 353 + +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) + +/* pmu-clocks indices */ + +#define PLL_GPLL 1 + +#define SCLK_RTC32K_PMU 4 +#define SCLK_WIFI_PMU 5 +#define SCLK_UART0_PMU 6 +#define SCLK_PVTM_PMU 7 +#define PCLK_PMU_PRE 8 +#define SCLK_REF24M_PMU 9 +#define SCLK_USBPHY_REF 10 +#define SCLK_MIPIDSIPHY_REF 11 + +#define XIN24M_DIV 12 + +#define PCLK_GPIO0_PMU 20 +#define PCLK_UART0_PMU 21 + +#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_GPU 18 +#define SRST_GPU_NIU 19 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_p 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_AXI_CMD_A 30 +#define SRST_AXI_CMD_P 31 + +#define SRST_DDRPHY 32 +#define SRST_DDRPHYDIV 33 +#define SRST_DDRPHY_P 34 +#define SRST_VPU_A 36 +#define SRST_VPU_NIU_A 37 +#define SRST_VPU_H 38 +#define SRST_VPU_NIU_H 39 +#define SRST_VI_NIU_A 40 +#define SRST_VI_NIU_H 41 +#define SRST_ISP_H 42 +#define SRST_ISP 43 +#define SRST_CIF_A 44 +#define SRST_CIF_H 45 +#define SRST_CIF_PCLKIN 46 +#define SRST_MIPICSIPHY_P 47 + +#define SRST_VO_NIU_A 48 +#define SRST_VO_NIU_H 49 +#define SRST_VO_NIU_P 50 +#define SRST_VOPB_A 51 +#define SRST_VOPB_H 52 +#define SRST_VOPB 53 +#define SRST_PWM_VOPB 54 +#define SRST_VOPL_A 55 +#define SRST_VOPL_H 56 +#define SRST_VOPL 57 +#define SRST_RGA_A 58 +#define SRST_RGA_H 59 +#define SRST_RGA 60 +#define SRST_MIPIDSI_HOST_P 61 +#define SRST_MIPIDSIPHY_P 62 +#define SRST_VPU_CORE 63 + +#define SRST_PERI_NIU_A 64 +#define SRST_USB_NIU_H 65 +#define SRST_USB2OTG_H 66 +#define SRST_USB2OTG 67 +#define SRST_USB2OTG_ADP 68 +#define SRST_USB2HOST_H 69 +#define SRST_USB2HOST_ARB_H 70 +#define SRST_USB2HOST_AUX_H 71 +#define SRST_USB2HOST_EHCI 72 +#define SRST_USB2HOST 73 +#define SRST_USBPHYPOR 74 +#define SRST_USBPHY_OTG_PORT 75 +#define SRST_USBPHY_HOST_PORT 76 +#define SRST_USBPHY_GRF 77 +#define SRST_CPU_BOOST_P 78 +#define SRST_CPU_BOOST 79 + +#define SRST_MMC_NAND_NIU_H 80 +#define SRST_SDIO_H 81 +#define SRST_EMMC_H 82 +#define SRST_SFC_H 83 +#define SRST_SFC 84 +#define SRST_SDCARD_NIU_H 85 +#define SRST_SDMMC_H 86 +#define SRST_NANDC_H 89 +#define SRST_NANDC 90 +#define SRST_GMAC_NIU_A 92 +#define SRST_GMAC_NIU_P 93 +#define SRST_GMAC_A 94 + +#define SRST_PMU_NIU_P 96 +#define SRST_PMU_SGRF_P 97 +#define SRST_PMU_GRF_P 98 +#define SRST_PMU 99 +#define SRST_PMU_MEM_P 100 +#define SRST_PMU_GPIO0_P 101 +#define SRST_PMU_UART0_P 102 +#define SRST_PMU_CRU_P 103 +#define SRST_PMU_PVTM 104 +#define SRST_PMU_UART 105 +#define SRST_PMU_NIU_H 106 +#define SRST_PMU_DDR_FAIL_SAVE 107 +#define SRST_PMU_CORE_PERF_A 108 +#define SRST_PMU_CORE_GRF_P 109 +#define SRST_PMU_GPU_PERF_A 110 +#define SRST_PMU_GPU_GRF_P 111 + +#define SRST_CRYPTO_NIU_A 112 +#define SRST_CRYPTO_NIU_H 113 +#define SRST_CRYPTO_A 114 +#define SRST_CRYPTO_H 115 +#define SRST_CRYPTO 116 +#define SRST_CRYPTO_APK 117 +#define SRST_BUS_NIU_H 120 +#define SRST_USB_NIU_P 121 +#define SRST_BUS_TOP_NIU_P 122 +#define SRST_INTMEM_A 123 +#define SRST_GIC_A 124 +#define SRST_ROM_H 126 +#define SRST_DCF_A 127 + +#define SRST_DCF_P 128 +#define SRST_PDM_H 129 +#define SRST_PDM 130 +#define SRST_I2S0_H 131 +#define SRST_I2S0_TX 132 +#define SRST_I2S1_H 133 +#define SRST_I2S1 134 +#define SRST_I2S2_H 135 +#define SRST_I2S2 136 +#define SRST_UART1_P 137 +#define SRST_UART1 138 +#define SRST_UART2_P 139 +#define SRST_UART2 140 +#define SRST_UART3_P 141 +#define SRST_UART3 142 +#define SRST_UART4_P 143 + +#define SRST_UART4 144 +#define SRST_UART5_P 145 +#define SRST_UART5 146 +#define SRST_I2C0_P 147 +#define SRST_I2C0 148 +#define SRST_I2C1_P 149 +#define SRST_I2C1 150 +#define SRST_I2C2_P 151 +#define SRST_I2C2 152 +#define SRST_I2C3_P 153 +#define SRST_I2C3 154 +#define SRST_PWM0_P 157 +#define SRST_PWM0 158 +#define SRST_PWM1_P 159 + +#define SRST_PWM1 160 +#define SRST_SPI0_P 161 +#define SRST_SPI0 162 +#define SRST_SPI1_P 163 +#define SRST_SPI1 164 +#define SRST_SARADC_P 165 +#define SRST_SARADC 166 +#define SRST_TSADC_P 167 +#define SRST_TSADC 168 +#define SRST_TIMER_P 169 +#define SRST_TIMER0 170 +#define SRST_TIMER1 171 +#define SRST_TIMER2 172 +#define SRST_TIMER3 173 +#define SRST_TIMER4 174 +#define SRST_TIMER5 175 + +#define SRST_OTP_NS_P 176 +#define SRST_OTP_NS_SBPI 177 +#define SRST_OTP_NS_USR 178 +#define SRST_OTP_PHY_P 179 +#define SRST_OTP_PHY 180 +#define SRST_WDT_NS_P 181 +#define SRST_GPIO1_P 182 +#define SRST_GPIO2_P 183 +#define SRST_GPIO3_P 184 +#define SRST_SGRF_P 185 +#define SRST_GRF_P 186 +#define SRST_I2S0_RX 191 + +#endif diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h new file mode 100644 index 0000000000..d97840f9ee --- /dev/null +++ b/include/dt-bindings/clock/rk3308-cru.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_VPLL0 3 +#define PLL_VPLL1 4 +#define ARMCLK 5 + +/* sclk (special clocks) */ +#define USB480M 14 +#define SCLK_RTC32K 15 +#define SCLK_PVTM_CORE 16 +#define SCLK_UART0 17 +#define SCLK_UART1 18 +#define SCLK_UART2 19 +#define SCLK_UART3 20 +#define SCLK_UART4 21 +#define SCLK_I2C0 22 +#define SCLK_I2C1 23 +#define SCLK_I2C2 24 +#define SCLK_I2C3 25 +#define SCLK_PWM0 26 +#define SCLK_SPI0 27 +#define SCLK_SPI1 28 +#define SCLK_SPI2 29 +#define SCLK_TIMER0 30 +#define SCLK_TIMER1 31 +#define SCLK_TIMER2 32 +#define SCLK_TIMER3 33 +#define SCLK_TIMER4 34 +#define SCLK_TIMER5 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_OTP 38 +#define SCLK_OTP_USR 39 +#define SCLK_CPU_BOOST 40 +#define SCLK_CRYPTO 41 +#define SCLK_CRYPTO_APK 42 +#define SCLK_NANDC_DIV 43 +#define SCLK_NANDC_DIV50 44 +#define SCLK_NANDC 45 +#define SCLK_SDMMC_DIV 46 +#define SCLK_SDMMC_DIV50 47 +#define SCLK_SDMMC 48 +#define SCLK_SDMMC_DRV 49 +#define SCLK_SDMMC_SAMPLE 50 +#define SCLK_SDIO_DIV 51 +#define SCLK_SDIO_DIV50 52 +#define SCLK_SDIO 53 +#define SCLK_SDIO_DRV 54 +#define SCLK_SDIO_SAMPLE 55 +#define SCLK_EMMC_DIV 56 +#define SCLK_EMMC_DIV50 57 +#define SCLK_EMMC 58 +#define SCLK_EMMC_DRV 59 +#define SCLK_EMMC_SAMPLE 60 +#define SCLK_SFC 61 +#define SCLK_OTG_ADP 62 +#define SCLK_MAC_SRC 63 +#define SCLK_MAC 64 +#define SCLK_MAC_REF 65 +#define SCLK_MAC_RX_TX 66 +#define SCLK_MAC_RMII 67 +#define SCLK_DDR_MON_TIMER 68 +#define SCLK_DDR_MON 69 +#define SCLK_DDRCLK 70 +#define SCLK_PMU 71 +#define SCLK_USBPHY_REF 72 +#define SCLK_WIFI 73 +#define SCLK_PVTM_PMU 74 +#define SCLK_PDM 75 +#define SCLK_I2S0_8CH_TX 76 +#define SCLK_I2S0_8CH_TX_OUT 77 +#define SCLK_I2S0_8CH_RX 78 +#define SCLK_I2S0_8CH_RX_OUT 79 +#define SCLK_I2S1_8CH_TX 80 +#define SCLK_I2S1_8CH_TX_OUT 81 +#define SCLK_I2S1_8CH_RX 82 +#define SCLK_I2S1_8CH_RX_OUT 83 +#define SCLK_I2S2_8CH_TX 84 +#define SCLK_I2S2_8CH_TX_OUT 85 +#define SCLK_I2S2_8CH_RX 86 +#define SCLK_I2S2_8CH_RX_OUT 87 +#define SCLK_I2S3_8CH_TX 88 +#define SCLK_I2S3_8CH_TX_OUT 89 +#define SCLK_I2S3_8CH_RX 90 +#define SCLK_I2S3_8CH_RX_OUT 91 +#define SCLK_I2S0_2CH 92 +#define SCLK_I2S0_2CH_OUT 93 +#define SCLK_I2S1_2CH 94 +#define SCLK_I2S1_2CH_OUT 95 +#define SCLK_SPDIF_TX_DIV 96 +#define SCLK_SPDIF_TX_DIV50 97 +#define SCLK_SPDIF_TX 98 +#define SCLK_SPDIF_RX_DIV 99 +#define SCLK_SPDIF_RX_DIV50 100 +#define SCLK_SPDIF_RX 101 +#define SCLK_I2S0_8CH_TX_MUX 102 +#define SCLK_I2S0_8CH_RX_MUX 103 +#define SCLK_I2S1_8CH_TX_MUX 104 +#define SCLK_I2S1_8CH_RX_MUX 105 +#define SCLK_I2S2_8CH_TX_MUX 106 +#define SCLK_I2S2_8CH_RX_MUX 107 +#define SCLK_I2S3_8CH_TX_MUX 108 +#define SCLK_I2S3_8CH_RX_MUX 109 +#define SCLK_I2S0_8CH_TX_SRC 110 +#define SCLK_I2S0_8CH_RX_SRC 111 +#define SCLK_I2S1_8CH_TX_SRC 112 +#define SCLK_I2S1_8CH_RX_SRC 113 +#define SCLK_I2S2_8CH_TX_SRC 114 +#define SCLK_I2S2_8CH_RX_SRC 115 +#define SCLK_I2S3_8CH_TX_SRC 116 +#define SCLK_I2S3_8CH_RX_SRC 117 +#define SCLK_I2S0_2CH_SRC 118 +#define SCLK_I2S1_2CH_SRC 119 +#define SCLK_PWM1 120 +#define SCLK_PWM2 121 +#define SCLK_OWIRE 122 + +/* dclk */ +#define DCLK_VOP 125 + +/* aclk */ +#define ACLK_BUS_SRC 130 +#define ACLK_BUS 131 +#define ACLK_PERI_SRC 132 +#define ACLK_PERI 133 +#define ACLK_MAC 134 +#define ACLK_CRYPTO 135 +#define ACLK_VOP 136 +#define ACLK_GIC 137 +#define ACLK_DMAC0 138 +#define ACLK_DMAC1 139 + +/* hclk */ +#define HCLK_BUS 150 +#define HCLK_PERI 151 +#define HCLK_AUDIO 152 +#define HCLK_NANDC 153 +#define HCLK_SDMMC 154 +#define HCLK_SDIO 155 +#define HCLK_EMMC 156 +#define HCLK_SFC 157 +#define HCLK_OTG 158 +#define HCLK_HOST 159 +#define HCLK_HOST_ARB 160 +#define HCLK_PDM 161 +#define HCLK_SPDIFTX 162 +#define HCLK_SPDIFRX 163 +#define HCLK_I2S0_8CH 164 +#define HCLK_I2S1_8CH 165 +#define HCLK_I2S2_8CH 166 +#define HCLK_I2S3_8CH 167 +#define HCLK_I2S0_2CH 168 +#define HCLK_I2S1_2CH 169 +#define HCLK_VAD 170 +#define HCLK_CRYPTO 171 +#define HCLK_VOP 172 + +/* pclk */ +#define PCLK_BUS 190 +#define PCLK_DDR 191 +#define PCLK_PERI 192 +#define PCLK_PMU 193 +#define PCLK_AUDIO 194 +#define PCLK_MAC 195 +#define PCLK_ACODEC 196 +#define PCLK_UART0 197 +#define PCLK_UART1 198 +#define PCLK_UART2 199 +#define PCLK_UART3 200 +#define PCLK_UART4 201 +#define PCLK_I2C0 202 +#define PCLK_I2C1 203 +#define PCLK_I2C2 204 +#define PCLK_I2C3 205 +#define PCLK_PWM0 206 +#define PCLK_SPI0 207 +#define PCLK_SPI1 208 +#define PCLK_SPI2 209 +#define PCLK_SARADC 210 +#define PCLK_TSADC 211 +#define PCLK_TIMER 212 +#define PCLK_OTP_NS 213 +#define PCLK_WDT 214 +#define PCLK_GPIO0 215 +#define PCLK_GPIO1 216 +#define PCLK_GPIO2 217 +#define PCLK_GPIO3 218 +#define PCLK_GPIO4 219 +#define PCLK_SGRF 220 +#define PCLK_GRF 221 +#define PCLK_USBSD_DET 222 +#define PCLK_DDR_UPCTL 223 +#define PCLK_DDR_MON 224 +#define PCLK_DDRPHY 225 +#define PCLK_DDR_STDBY 226 +#define PCLK_USB_GRF 227 +#define PCLK_CRU 228 +#define PCLK_OTP_PHY 229 +#define PCLK_CPU_BOOST 230 +#define PCLK_PWM1 231 +#define PCLK_PWM2 232 +#define PCLK_CAN 233 +#define PCLK_OWIRE 234 + +#define CLK_NR_CLKS (PCLK_OWIRE + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +/* cru_softrst_con1 */ +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_CORE_PRF 18 +#define SRST_CORE_GRF 19 +#define SRST_DDRUPCTL 20 +#define SRST_DDRUPCTL_P 22 +#define SRST_MSCH 23 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRPHY 28 +#define SRST_DDRPHY_DIV 29 +#define SRST_DDRPHY_P 30 + +/* cru_softrst_con2 */ +#define SRST_BUS_NIU_H 32 +#define SRST_USB_NIU_P 33 +#define SRST_CRYPTO_A 34 +#define SRST_CRYPTO_H 35 +#define SRST_CRYPTO 36 +#define SRST_CRYPTO_APK 37 +#define SRST_VOP_A 38 +#define SRST_VOP_H 39 +#define SRST_VOP_D 40 +#define SRST_INTMEM_A 41 +#define SRST_ROM_H 42 +#define SRST_GIC_A 43 +#define SRST_UART0_P 44 +#define SRST_UART0 45 +#define SRST_UART1_P 46 +#define SRST_UART1 47 + +/* cru_softrst_con3 */ +#define SRST_UART2_P 48 +#define SRST_UART2 49 +#define SRST_UART3_P 50 +#define SRST_UART3 51 +#define SRST_UART4_P 52 +#define SRST_UART4 53 +#define SRST_I2C0_P 54 +#define SRST_I2C0 55 +#define SRST_I2C1_P 56 +#define SRST_I2C1 57 +#define SRST_I2C2_P 58 +#define SRST_I2C2 59 +#define SRST_I2C3_P 60 +#define SRST_I2C3 61 +#define SRST_PWM0_P 62 +#define SRST_PWM0 63 + +/* cru_softrst_con4 */ +#define SRST_SPI0_P 64 +#define SRST_SPI0 65 +#define SRST_SPI1_P 66 +#define SRST_SPI1 67 +#define SRST_SPI2_P 68 +#define SRST_SPI2 69 +#define SRST_SARADC_P 70 +#define SRST_TSADC_P 71 +#define SRST_TSADC 72 +#define SRST_TIMER0_P 73 +#define SRST_TIMER0 74 +#define SRST_TIMER1 75 +#define SRST_TIMER2 76 +#define SRST_TIMER3 77 +#define SRST_TIMER4 78 +#define SRST_TIMER5 79 + +/* cru_softrst_con5 */ +#define SRST_OTP_NS_P 80 +#define SRST_OTP_NS_SBPI 81 +#define SRST_OTP_NS_USR 82 +#define SRST_OTP_PHY_P 83 +#define SRST_OTP_PHY 84 +#define SRST_GPIO0_P 86 +#define SRST_GPIO1_P 87 +#define SRST_GPIO2_P 88 +#define SRST_GPIO3_P 89 +#define SRST_GPIO4_P 90 +#define SRST_GRF_P 91 +#define SRST_USBSD_DET_P 92 +#define SRST_PMU 93 +#define SRST_PMU_PVTM 94 +#define SRST_USB_GRF_P 95 + +/* cru_softrst_con6 */ +#define SRST_CPU_BOOST 96 +#define SRST_CPU_BOOST_P 97 +#define SRST_PWM1_P 98 +#define SRST_PWM1 99 +#define SRST_PWM2_P 100 +#define SRST_PWM2 101 +#define SRST_PERI_NIU_A 104 +#define SRST_PERI_NIU_H 105 +#define SRST_PERI_NIU_p 106 +#define SRST_USB2OTG_H 107 +#define SRST_USB2OTG 108 +#define SRST_USB2OTG_ADP 109 +#define SRST_USB2HOST_H 110 +#define SRST_USB2HOST_ARB_H 111 + +/* cru_softrst_con7 */ +#define SRST_USB2HOST_AUX_H 112 +#define SRST_USB2HOST_EHCI 113 +#define SRST_USB2HOST 114 +#define SRST_USBPHYPOR 115 +#define SRST_UTMI0 116 +#define SRST_UTMI1 117 +#define SRST_SDIO_H 118 +#define SRST_EMMC_H 119 +#define SRST_SFC_H 120 +#define SRST_SFC 121 +#define SRST_SD_H 122 +#define SRST_NANDC_H 123 +#define SRST_NANDC_N 124 +#define SRST_MAC_A 125 +#define SRST_CAN_P 126 +#define SRST_OWIRE_P 127 + +/* cru_softrst_con8 */ +#define SRST_AUDIO_NIU_H 128 +#define SRST_AUDIO_NIU_P 129 +#define SRST_PDM_H 130 +#define SRST_PDM_M 131 +#define SRST_SPDIFTX_H 132 +#define SRST_SPDIFTX_M 133 +#define SRST_SPDIFRX_H 134 +#define SRST_SPDIFRX_M 135 +#define SRST_I2S0_8CH_H 136 +#define SRST_I2S0_8CH_TX_M 137 +#define SRST_I2S0_8CH_RX_M 138 +#define SRST_I2S1_8CH_H 139 +#define SRST_I2S1_8CH_TX_M 140 +#define SRST_I2S1_8CH_RX_M 141 +#define SRST_I2S2_8CH_H 142 +#define SRST_I2S2_8CH_TX_M 143 + +/* cru_softrst_con9 */ +#define SRST_I2S2_8CH_RX_M 144 +#define SRST_I2S3_8CH_H 145 +#define SRST_I2S3_8CH_TX_M 146 +#define SRST_I2S3_8CH_RX_M 147 +#define SRST_I2S0_2CH_H 148 +#define SRST_I2S0_2CH_M 149 +#define SRST_I2S1_2CH_H 150 +#define SRST_I2S1_2CH_M 151 +#define SRST_VAD_H 152 +#define SRST_ACODEC_P 153 + +#endif diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h new file mode 100644 index 0000000000..30917a99ad --- /dev/null +++ b/include/dt-bindings/power/px30-power.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ +#define __DT_BINDINGS_POWER_PX30_POWER_H__ + +/* VD_CORE */ +#define PX30_PD_A35_0 0 +#define PX30_PD_A35_1 1 +#define PX30_PD_A35_2 2 +#define PX30_PD_A35_3 3 +#define PX30_PD_SCU 4 + +/* VD_LOGIC */ +#define PX30_PD_USB 5 +#define PX30_PD_DDR 6 +#define PX30_PD_SDCARD 7 +#define PX30_PD_CRYPTO 8 +#define PX30_PD_GMAC 9 +#define PX30_PD_MMC_NAND 10 +#define PX30_PD_VPU 11 +#define PX30_PD_VO 12 +#define PX30_PD_VI 13 +#define PX30_PD_GPU 14 + +/* VD_PMU */ +#define PX30_PD_PMU 15 + +#endif diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h new file mode 100644 index 0000000000..4b0914c098 --- /dev/null +++ b/include/dt-bindings/soc/rockchip,boot-mode.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ROCKCHIP_BOOT_MODE_H +#define __ROCKCHIP_BOOT_MODE_H + +/*high 24 bits is tag, low 8 bits is type*/ +#define REBOOT_FLAG 0x5242C300 +/* normal boot */ +#define BOOT_NORMAL (REBOOT_FLAG + 0) +/* enter bootloader rockusb mode */ +#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) +/* enter recovery */ +#define BOOT_RECOVERY (REBOOT_FLAG + 3) + /* enter fastboot mode */ +#define BOOT_FASTBOOT (REBOOT_FLAG + 9) + +#endif diff --git a/include/env_internal.h b/include/env_internal.h index 88c36b32a1..d520e6a55b 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -58,21 +58,12 @@ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) # define ENV_IS_EMBEDDED # endif -# if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND) -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT -# endif # ifdef CONFIG_ENV_IS_EMBEDDED # error "do not define CONFIG_ENV_IS_EMBEDDED in your board config" # error "it is calculated automatically for you" # endif #endif /* CONFIG_ENV_IS_IN_FLASH */ -#if defined(CONFIG_ENV_IS_IN_MMC) -# ifdef CONFIG_ENV_OFFSET_REDUND -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT -# endif -#endif - #if defined(CONFIG_ENV_IS_IN_NAND) # if defined(CONFIG_ENV_OFFSET_OOB) # ifdef CONFIG_ENV_OFFSET_REDUND @@ -85,9 +76,6 @@ extern unsigned long nand_env_oob_offset; # ifndef CONFIG_ENV_OFFSET # error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND" # endif -# ifdef CONFIG_ENV_OFFSET_REDUND -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT -# endif # endif /* CONFIG_ENV_OFFSET_OOB */ # ifndef CONFIG_ENV_SIZE # error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND" @@ -101,9 +89,6 @@ extern unsigned long nand_env_oob_offset; # ifndef CONFIG_ENV_UBI_VOLUME # error "Need to define CONFIG_ENV_UBI_VOLUME when using CONFIG_ENV_IS_IN_UBI" # endif -# if defined(CONFIG_ENV_UBI_IS_VOLUME_REDUND) -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT -# endif # ifndef CONFIG_ENV_SIZE # error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_UBI" # endif diff --git a/include/fdtdec.h b/include/fdtdec.h index f1e58f9732..696e0fd024 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1061,6 +1061,7 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * @param basename base name of the node to create * @param carveout information about the carveout region * @param phandlep return location for the phandle of the carveout region + * can be NULL if no phandle should be added * @return 0 on success or a negative error code on failure */ int fdtdec_add_reserved_memory(void *blob, const char *basename, diff --git a/include/host_arch.h b/include/host_arch.h new file mode 100644 index 0000000000..169d494513 --- /dev/null +++ b/include/host_arch.h @@ -0,0 +1,24 @@ +#if 0 +# SPDX SPDX-License-Identifier: GPL-2.0+ +# +# Constants defining the host architecture in assembler, C, and make files. +# The values are arbitrary. +# +# Copyright 2019 Heinrich Schuchardt <xypron.glpk@gmx.de> +#endif + +#if 0 +export HOST_ARCH_AARCH64=0xaa64 +export HOST_ARCH_ARM=0x00a7 +export HOST_ARCH_RISCV32=0x5032 +export HOST_ARCH_RISCV64=0x5064 +export HOST_ARCH_X86=0x0386 +export HOST_ARCH_X86_64=0x8664 +#endif + +#define HOST_ARCH_AARCH64 0xaa64 +#define HOST_ARCH_ARM 0x00a7 +#define HOST_ARCH_RISCV32 0x5032 +#define HOST_ARCH_RISCV64 0x5064 +#define HOST_ARCH_X86 0x0386 +#define HOST_ARCH_X86_64 0x8664 diff --git a/include/imximage.h b/include/imximage.h index 544babb53a..ace5cf8601 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -79,6 +79,7 @@ enum imximage_cmd { CMD_LOADER, CMD_SECOND_LOADER, CMD_DDR_FW, + CMD_ROM_VERSION, }; enum imximage_fld_types { diff --git a/include/tee/optee.h b/include/tee/optee.h index 9446928fd4..121b30a303 100644 --- a/include/tee/optee.h +++ b/include/tee/optee.h @@ -67,4 +67,13 @@ static inline int optee_verify_bootm_image(unsigned long image_addr, } #endif +#if defined(CONFIG_OPTEE) && defined(CONFIG_OF_LIBFDT) +int optee_copy_fdt_nodes(const void *old_blob, void *new_blob); +#else +static inline int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) +{ + return 0; +} +#endif + #endif /* _OPTEE_H */ diff --git a/include/test/optee.h b/include/test/optee.h new file mode 100644 index 0000000000..a8c6e6395f --- /dev/null +++ b/include/test/optee.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __TEST_OPTEE_H__ +#define __TEST_OPTEE_H__ + +#include <test/test.h> + +/* Declare a new environment test */ +#define OPTEE_TEST(_name, _flags) UNIT_TEST(_name, _flags, optee_test) + +#endif /* __TEST_OPTEE_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index 01bee09346..20970f08d6 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -28,6 +28,7 @@ int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_lib(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_optee(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index a6c12212a9..a2af381a66 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -8,12 +8,14 @@ #ifndef __DWC2_USB_GADGET #define __DWC2_USB_GADGET +#include <dm/ofnode.h> + #define PHY0_SLEEP (1 << 5) #define DWC2_MAX_HW_ENDPOINTS 16 struct dwc2_plat_otg_data { void *priv; - int phy_of_node; + ofnode phy_of_node; int (*phy_control)(int on); uintptr_t regs_phy; uintptr_t regs_otg; |