diff options
Diffstat (limited to 'include')
122 files changed, 3425 insertions, 855 deletions
diff --git a/include/config_defaults.h b/include/config_defaults.h index 7ef928bbe1..4ed09683b6 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -16,7 +16,4 @@ #define CONFIG_BOOTM_RTEMS 1 #define CONFIG_BOOTM_VXWORKS 1 -#define CONFIG_GZIP 1 -#define CONFIG_ZLIB 1 - #endif diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index e2c70605b2..57edeee941 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -34,8 +34,6 @@ #define CONFIG_MXC_UART -#define CONFIG_MXC_OCOTP - /* SATA Configs */ #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 @@ -217,7 +215,6 @@ /* Framebuffer */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/alt.h b/include/configs/alt.h index 3f7f379e06..3a515eef00 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -39,7 +39,8 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" + "bootm_size=0x10000000\0" \ + "usb_pgood_delay=2000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0834ff5021..7721907d8f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -240,7 +240,6 @@ * add mass storage support and for gadget we add both RNDIS ethernet * and DFU. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h new file mode 100644 index 0000000000..8bde198313 --- /dev/null +++ b/include/configs/am335x_guardian.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * am335x_guardian_.h + * + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + * Copyright (C) 2018 sjoerd Simons <sjoerd.simons@collabora.co.uk> + * + */ + +#ifndef __CONFIG_AM335X_GUARDIAN_H +#define __CONFIG_AM335X_GUARDIAN_H + +#include <configs/ti_am335x_common.h> + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_TIMESTAMP +#endif + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#ifndef CONFIG_SPL_BUILD + +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x80000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + AM335XX_BOARD_FDTFILE \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV \ + "bootlimit=3\0" \ + "altbootcmd=" \ + "setenv boot_config \"extlinux-rollback.conf\"; " \ + "run distro_bootcmd\0" + +#endif /* CONFIG_SPL_BUILD */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 + +/* Bootcount using the RTC block */ +#define CONFIG_SYS_BOOTCOUNT_LE + +#ifdef CONFIG_NAND +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_OFFSET_REDUND 0x340000 +#define CONFIG_ENV_SIZE 0x040000 + +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 256 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) + +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ + } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 26 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW +#define MTDIDS_DEFAULT "nand0=nand.0" + +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + +#endif /* CONFIG_NAND */ + +#endif /* ! __CONFIG_AM335X_GUARDIAN_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 5a6080645a..37d058ebbc 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -120,12 +120,6 @@ #define CONFIG_ENV_OFFSET_REDUND 0x120000 #endif -/* SPI */ -#define CONFIG_TI_SPI_MMAP -#define CONFIG_QSPI_SEL_GPIO 48 -#define CONFIG_QSPI_QUAD_SUPPORT -#define CONFIG_TI_EDMA3 - #ifndef CONFIG_SPL_BUILD #include <environment/ti/dfu.h> #include <environment/ti/mmc.h> diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 48999847ee..c14b010550 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -92,11 +92,6 @@ #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ -#define CONFIG_TI_EDMA3 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 -/* SPI */ -#define CONFIG_TI_SPI_MMAP -#define CONFIG_QSPI_QUAD_SUPPORT - #endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/ap152.h b/include/configs/ap152.h new file mode 100644 index 0000000000..c948a44054 --- /dev/null +++ b/include/configs/ap152.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 375 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 25000000 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f060000" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 + +/* Miscellaneous configurable options */ + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index ba4e96da50..96169f55f0 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Toradex, Inc. + * Copyright 2013-2019 Toradex, Inc. * * Configuration settings for the Toradex Apalis iMX6 */ @@ -34,17 +34,12 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* I2C Configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ #define CONFIG_FSL_USDHC @@ -57,9 +52,6 @@ * SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 #endif @@ -82,11 +74,7 @@ /* Client */ #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_MASS_STORAGE - /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN @@ -115,37 +103,36 @@ #define CONFIG_LOADADDR 0x12000000 -#ifdef CONFIG_CMD_SATA -#define CONFIG_DRIVE_SATA "sata " -#else -#define CONFIG_DRIVE_SATA -#endif - -#ifdef CONFIG_CMD_MMC -#define CONFIG_DRIVE_MMC "mmc " -#else -#define CONFIG_DRIVE_MMC -#endif - -#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif /* CONFIG_SPL_BUILD */ #define DFU_ALT_EMMC_INFO \ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ "boot part 0 1;" \ "rootfs part 0 2;" \ - "uImage fat 0 1;" \ - "imx6q-colibri-eval-v3.dtb fat 0 1;" \ - "imx6q-colibri-cam-eval-v3.dtb fat 0 1" + "zImage fat 0 1;" \ + "imx6q-apalis-eval.dtb fat 0 1;" \ + "imx6q-apalis-cam-eval.dtb fat 0 1" #define EMMC_BOOTCMD \ - "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "emmcboot=run setup; " \ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ "${vidargs}; echo Booting from internal eMMC chip...; " \ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" @@ -155,7 +142,9 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ - "ramdisk_addr_r=0x12100000\0" + "pxefile_addr_r=0x17100000\0" \ + "ramdisk_addr_r=0x12100000\0" \ + "scriptaddr=0x17000000\0" #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ @@ -163,30 +152,30 @@ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" -#define SD_BOOTCMD \ - "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "sdboot=run setup; " \ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ "${vidargs}; echo Booting from SD card; " \ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define USB_BOOTCMD \ - "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ + "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" @@ -197,11 +186,12 @@ #define FDT_FILE "imx6q-apalis_v1_0-eval.dtb" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ - "run nfsboot ; echo ; echo nfsboot failed ; " \ - "usb start ;" \ + "run distro_bootcmd ; " \ + "usb start ; " \ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ - "boot_file=uImage\0" \ + "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off vmalloc=400M\0" \ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ @@ -214,8 +204,10 @@ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ - "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ + "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \ + " ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "setup=setenv setupargs fec_mac=${ethaddr} " \ "consoleblank=0 no_console_suspend=1 console=tty1 " \ @@ -255,7 +247,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* environment organization */ - #define CONFIG_ENV_SIZE (8 * 1024) #if defined(CONFIG_ENV_IS_IN_MMC) @@ -266,8 +257,6 @@ #define CONFIG_SYS_MMC_ENV_PART 1 #endif -#define CONFIG_OF_SYSTEM_SETUP - #define CONFIG_CMD_TIME #endif /* __CONFIG_H */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 4f28f52402..a24814673c 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -187,7 +187,6 @@ /* UBI support */ /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 /* check this console not needed, after test remove it */ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/baltos.h b/include/configs/baltos.h index ccbdc0a335..98ec0d626e 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -251,7 +251,6 @@ * add mass storage support and for gadget we add both RNDIS ethernet * and DFU. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_HOST #define CONFIG_AM335X_USB1 diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index fb9c2a6d04..3d4d08aa70 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -387,7 +387,6 @@ DEFAULT_LINUX_BOOT_ENV \ * add mass storage support and for gadget we add both RNDIS ethernet * and DFU. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index a012705870..05ebb7d9c5 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -1,24 +1,271 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * * Copyright 2016 3ADEV <http://3adev.com> * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> * - * Configuration settings for the phytec PCM-052 SoM-based BK4R1. + * Configuration settings for BK4R1. */ +#ifndef __CONFIG_H +#define __CONFIG_H + /* Define the BK4r1-specific env commands */ -#define PCM052_EXTRA_ENV_SETTINGS \ +#define BK4_EXTRA_ENV_SETTINGS \ + "bootlimit=3\0" \ + "eraseuserdata=false\0" \ + "altbootcmd=led 5 on; " \ + "boot\0" \ "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ - "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0" + "set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \ + "set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\ + "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\ + "set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\ + "manage_userdata=" MANAGE_USERDATA "\0"\ + "ncenable=true\0"\ + "ncserverip=192.168.0.77\0"\ + "if_netconsole=ping $ncserverip\0"\ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \ + "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "preboot=" BK4_NET_INIT \ + "if ${ncenable}; then run if_netconsole start_netconsole; fi\0" /* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ -#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; " +#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \ + "run manage_userdata; " + +/* Enable PREBOOT variable */ +#define CONFIG_PREBOOT + +/* Set ARP_TIMEOUT to 500ms */ +#define CONFIG_ARP_TIMEOUT 500UL + +/* Set ARP_TIMEOUT_COUNT to 3 repetitions */ +#define CONFIG_NET_RETRY_COUNT 5 /* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ -#define PCM052_NET_INIT "run set_gpio122; " +#define BK4_NET_INIT "run set_gpio122;" + +/* Check if userdata volume shall be erased */ +#define MANAGE_USERDATA "if ${eraseuserdata}; " \ + "then ubi part system; " \ + "ubi remove userdata; " \ + "ubi create userdata; " \ + "ubi detach; " \ + "setenv eraseuserdata false; " \ + "saveenv; " \ + "fi; " + +/* Autoboot options */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "Enter passphrase to stop autoboot, booting in %d seconds\n" +#define CONFIG_AUTOBOOT_STOP_STR "123" + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define IMX_FEC1_BASE ENET1_BASE_ADDR + +/* QSPI Configs*/ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE (SZ_16M) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_BOARD_SIZE_LIMIT 520192 + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND BK4_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BK4_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ + "dtbkernel_file=fitImage\0" \ + "dtbkernel_addr=0x82000000\0" \ + "ram_file=uRamdisk\0" \ + "ram_addr=0x83000000\0" \ + "filesys=rootfs.ubifs\0" \ + "sys_addr=0x81000000\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "tftptimeout=1000\0" \ + "tftptimeoutcountmax=1000000\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "ipaddr=192.168.0.60\0" \ + "serverip=192.168.0.1\0" \ + "bootargs_base=setenv bootargs rw " \ + "console=ttyLP1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "ubi.mtd=5 rootfstype=" \ + "ubifs root=ubi0:rootfs${active_workset}\0" \ + "bootargs_ram=setenv bootargs ${bootargs} " \ + "root=/dev/ram rw initrd=${ram_addr}\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ + "fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \ + "ubi part dtbkernel; " \ + "ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \ + "led 0 on; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "nand read ${ram_addr} root; " \ + "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ + "update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \ + "${blimg_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; "\ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \ + "${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \ + "${tftpdir}${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \ + "${ram_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "then sf probe; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \ + "${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "setup_dtbkernel=nand erase.part dtbkernel; " \ + "ubi part dtbkernel; " \ + "ubi create dtbkernel1 972000 s; " \ + "ubi create dtbkernel2 972000 s; " \ + "ubi detach\0" \ + "setup_system=nand erase.part system; " \ + "ubi part system; " \ + "ubi create rootfs1 15E15000 d; " \ + "ubi create rootfs2 15E15000 d; " \ + "ubi create userdata; " \ + "ubi detach\0" \ + "setup_nor1=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \ + "then sf probe 0:0; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor1fs; " \ + "ubi write ${sys_addr} nor1fs ${filesize}; " \ + "ubi detach; fi\0" \ + "setup_nor2=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \ + "then sf probe 0:1; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor2fs; " \ + "ubi write ${sys_addr} nor2fs ${filesize}; " \ + "ubi detach; fi\0" \ + "prepare_install_bk4r1_envs=" \ + "echo 'Preparing envs for SD card recovery!';" \ + "setenv ipaddr 192.168.0.99;" \ + "setenv serverip 192.168.0.50;" \ + "\0" \ + "install_bk4r1rs="\ + "led 0 on; " \ + "nand erase.chip; mtdparts default; "\ + "led 1 on; "\ + "run setup_dtbkernel; " \ + "run setup_system; " \ + "led 2 on;" \ + "run update_bootloader_from_sd; "\ + "run update_dtbkernel_from_sd; "\ + "run update_rootfs_from_sd; "\ + "setenv bootcmd 'run bootcmd_nand'; "\ + "saveenv; " \ + "led 3 on; " \ + "echo Finished - Please Power off, REMOVE SDCARD and set boot" \ + "source to NAND\0" \ + "active_workset=1\0" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical memory map */ +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (SZ_512M) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* add NOR to MTD env */ +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* now include standard PCM052 config */ +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_SIZE (SZ_8K) +#define CONFIG_ENV_OFFSET 0x200000 +#define CONFIG_ENV_SIZE_REDUND (SZ_8K) +#define CONFIG_ENV_OFFSET_REDUND 0x220000 +#endif -#include "configs/pcm052.h" +#endif /* __CONFIG_H */ diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 5834e1e2a2..2de6f21861 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -30,6 +30,13 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif /* CONFIG_NAND */ + /* * bcm963158 */ diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h index 6126a8879e..355f3ef5be 100644 --- a/include/configs/broadcom_bcm968380gerg.h +++ b/include/configs/broadcom_bcm968380gerg.h @@ -7,3 +7,10 @@ #include <configs/bmips_bcm6838.h> #define CONFIG_ENV_SIZE (8 * 1024) + +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif /* CONFIG_NAND */ diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h index 1c0945e140..52b4f55f7c 100644 --- a/include/configs/broadcom_bcm968580xref.h +++ b/include/configs/broadcom_bcm968580xref.h @@ -29,6 +29,13 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif /* CONFIG_NAND */ + /* * 968580xref */ diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index ae9b75bb87..84c801d10a 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -182,9 +182,6 @@ NANDTGTS \ #define CONFIG_NAND_OMAP_GPMC_WSCFG 1 #endif /* CONFIG_NAND */ -/* USB configuration */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT - #if defined(CONFIG_SPI) /* SPI Flash */ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 601b30dffd..7309e7d483 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -68,9 +68,6 @@ BUR_COMMON_ENV \ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -/* USB configuration */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT - /* Environment */ #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index ad0a64a936..07c6409e8f 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -60,7 +60,6 @@ #define CONFIG_USBD_HS /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 4372280d2b..db990fcb2b 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -148,7 +148,6 @@ /* USB configuration */ #define CONFIG_ARCH_MISC_INIT -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h deleted file mode 100644 index bf2bb44d48..0000000000 --- a/include/configs/cl-som-am57x.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for CompuLab CL-SOM-AM57x board - * - * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ - * - * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> - */ - -#ifndef __CONFIG_CL_SOM_AM57X_H -#define __CONFIG_CL_SOM_AM57X_H - -#define CONSOLEDEV "ttyO2" -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ - -#define CONFIG_SYS_OMAP_ABE_SYSCK - -#define PARTS_DEFAULT - -#include <configs/ti_omap5_common.h> - -/* misc */ -#define CONFIG_REVISION_TAG - -/* PMIC I2C bus number */ -#define CONFIG_SYS_SPD_BUS_NUM 3 - -/* SPI Flash support */ -#define CONFIG_TI_SPI_MMAP - -/* SPI SPL defines */ -/* Offsets: 0K - SPL1, 64K - SPL2, 128K - SPL3, 192K - SPL4, 256K - U-Boot */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) -#define CONFIG_SPL_SPI_SUPPORT - -/* SD/MMC RAW/FS boot */ -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */ - -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_OFFSET (768 * 1024) - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 3 - -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_EEPROM_SIZE 256 - -#ifndef CONFIG_SPL_BUILD -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -/* PCA9555 GPIO expander support */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } - -#endif /* !CONFIG_SPL_BUILD */ - -/* USB xHCI HOST */ -#define CONFIG_USB_XHCI_OMAP - -#define CONFIG_OMAP_USB3PHY1_HOST - -/* USB Networking options */ - -/* CPSW Ethernet */ -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_PHY_ATHEROS -#define CONFIG_SYS_RX_ETH_BUFFER 64 -#define PHY_ANEG_TIMEOUT 8000 - -#define CONFIG_BOOTP_DNS2 -#define CONFIG_NET_RETRY_COUNT 10 - -/* Default environment */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "autoload=no\0" \ - "baudrate=115200\0" \ - "console=ttyO2,115200n8\0" \ - "bootdelay=3\0" \ - "fdtfile=am57xx-sbc-am57x.dtb\0" \ - "kernel=zImage-cl-som-am57x\0" \ - "bootscr=bootscr.img\0" \ - "displaytype=hdmi\0" \ - "bootkernel=bootz ${loadaddr} - ${fdtaddr}\0" \ - "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ - "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ - "emmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ - "emmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ - "load_mmc=mmc dev ${mmcdev} && mmc rescan && " \ - "run mmcloadkernel && run mmcloadfdt\0" \ - "mmcroot=/dev/mmcblk1p2\0" \ - "mmcrootfstype=ext4 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "mmcbootscript=setenv mmcdev 0; mmc dev ${mmcdev} && mmc rescan && " \ - "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \ - "echo Running bootscript from MMC/SD Card ... && " \ - "source ${loadaddr}\0" \ - "mmcboot=setenv mmcdev 0 && run load_mmc && " \ - "run mmcargs && echo Booting from MMC/SD Card ... && " \ - "run bootkernel\0" \ - "emmcroot=/dev/mmcblk0p2\0" \ - "emmcrootfstype=ext4 rw rootwait\0" \ - "emmcargs=setenv bootargs console=${console} " \ - "root=${emmcroot} " \ - "rootfstype=${emmcrootfstype}\0" \ - "emmcbootscript=setenv mmcdev 1; mmc dev ${mmcdev} && mmc rescan && " \ - "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \ - "echo Running bootscript from eMMC ... && " \ - "source ${loadaddr}\0" \ - "emmcboot=setenv mmcdev 1 && run load_mmc && " \ - "run emmcargs && echo Booting from eMMC ... && " \ - "run bootkernel\0" \ - "sataroot=/dev/sda2\0" \ - "satarootfstype=ext4 rw rootwait\0" \ - "load_sata=load scsi 0 ${loadaddr} ${kernel} && " \ - "load scsi 0 ${fdtaddr} ${fdtfile}\0" \ - "sataargs=setenv bootargs console=${console} " \ - "root=${sataroot} " \ - "rootfstype=${satarootfstype}\0" \ - "satabootscript=load scsi 0 ${loadaddr} ${bootscr} && " \ - "echo Running bootscript from SATA ... && " \ - "source ${loadaddr}\0" \ - "sataboot=run load_sata && run sataargs && " \ - "echo Booting from SATA ... && " \ - "run bootkernel\0" - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND \ - "run mmcbootscript || run mmcboot || " \ - "run satabootscript || run sataboot || " \ - "run emmcbootscript || run emmcboot" - - -#endif /* __CONFIG_CL_SOM_AM57X_H */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index c51cf28450..9f8d3cc9e5 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -21,8 +21,6 @@ * Commands configuration */ -/* SPI NOR flash default params, used by sf commands */ - /* * SDIO/MMC Card Configuration */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index dfd96ff8d5..2e8dda8ab8 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -212,7 +212,6 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) /* Display */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_IMX_HDMI #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index ffe4a44c86..e4e37e5bbb 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -53,9 +53,6 @@ #define CONFIG_USB_XHCI_OMAP #define CONFIG_AM437X_USB2PHY2_HOST -/* SPI Flash support */ -#define CONFIG_TI_SPI_MMAP - /* Power */ #define CONFIG_POWER #define CONFIG_POWER_I2C diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 2d40ceb24e..803c9be064 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Toradex, Inc. + * Copyright 2013-2019 Toradex, Inc. * * Configuration settings for the Toradex Colibri iMX6 */ @@ -32,17 +32,12 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* I2C Configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ #define CONFIG_FSL_USDHC @@ -70,11 +65,7 @@ /* Client */ #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_MASS_STORAGE - /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN @@ -103,31 +94,35 @@ #define CONFIG_LOADADDR 0x12000000 -#ifdef CONFIG_CMD_MMC -#define CONFIG_DRIVE_MMC "mmc " -#else -#define CONFIG_DRIVE_MMC -#endif - -#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif /* CONFIG_SPL_BUILD */ #define DFU_ALT_EMMC_INFO \ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ "boot part 0 1;" \ "rootfs part 0 2;" \ - "uImage fat 0 1;" \ - "imx6q-colibri-eval-v3.dtb fat 0 1;" \ - "imx6q-colibri-cam-eval-v3.dtb fat 0 1" + "zImage fat 0 1;" \ + "imx6dl-colibri-eval-v3.dtb fat 0 1;" \ + "imx6dl-colibri-cam-eval-v3.dtb fat 0 1" #define EMMC_BOOTCMD \ - "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "emmcboot=run setup; " \ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ "${vidargs}; echo Booting from internal eMMC chip...; " \ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" @@ -137,7 +132,9 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ - "ramdisk_addr_r=0x12100000\0" + "pxefile_addr_r=0x17100000\0" \ + "ramdisk_addr_r=0x12100000\0" \ + "scriptaddr=0x17000000\0" #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ @@ -145,40 +142,41 @@ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" -#define SD_BOOTCMD \ - "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "sdboot=run setup; " \ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ "${vidargs}; echo Booting from SD card; " \ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define USB_BOOTCMD \ - "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ + "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define FDT_FILE "imx6dl-colibri-eval-v3.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ - "run nfsboot ; echo ; echo nfsboot failed ; " \ - "usb start ;" \ + "run distro_bootcmd ; " \ + "usb start ; " \ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ - "boot_file=uImage\0" \ + "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ @@ -240,8 +238,6 @@ #define CONFIG_SYS_MMC_ENV_PART 1 #endif -#define CONFIG_OF_SYSTEM_SETUP - #define CONFIG_CMD_TIME #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 31ff8a00a6..0d57e303a1 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015-2016 Toradex, Inc. + * Copyright 2015-2019 Toradex, Inc. * * Configuration settings for the Toradex VF50/VF61 modules. * @@ -12,15 +12,12 @@ #define __CONFIG_H #include <asm/arch/imx-regs.h> +#include <linux/sizes.h> #define CONFIG_SYS_FSL_CLK #define CONFIG_SKIP_LOWLEVEL_INIT -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - #ifdef CONFIG_VIDEO_FSL_DCU_FB #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_VIDEO_LOGO @@ -32,7 +29,7 @@ #endif /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -40,17 +37,6 @@ /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR - -/* Dynamic MTD partition support */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET1_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 @@ -62,13 +48,15 @@ /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 -#define SD_BOOTCMD \ - "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ - "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ - "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \ - "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ @@ -79,7 +67,15 @@ "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ -#define UBI_BOOTCMD \ +#define SD_BOOTCMD \ + "sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ + "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ + "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ @@ -90,36 +86,43 @@ "ubi read ${fdt_addr_r} dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ -#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" +#define CONFIG_BOOTCOMMAND "run ubiboot; " \ + "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x82000000\0" \ - "fdt_addr_r=0x84000000\0" \ - "kernel_file=zImage\0" \ - "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + UBI_BOOTCMD \ + "console=ttyLP0\0" \ + "defargs=user_debug=30\0" \ + "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ - "defargs=\0" \ - "console=ttyLP0\0" \ - "setup=setenv setupargs " \ - "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs}\0" \ + "kernel_file=zImage\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setsdupdate=mmc rescan && set interface mmc && " \ - "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setusbupdate=usb start && set interface usb && " \ - "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs}\0" \ "setupdate=run setsdupdate || run setusbupdate\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ - "video-mode=dcufb:640x480-16@60,monitor=lcd\0" \ + "setusbupdate=usb start && set interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - SD_BOOTCMD \ - NFS_BOOTCMD \ - UBI_BOOTCMD + "video-mode=dcufb:640x480-16@60,monitor=lcd\0" /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -133,7 +136,7 @@ /* Physical memory map */ #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (256 * SZ_1M) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -145,13 +148,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ - -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (12 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#endif - #ifdef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE (64 * 2048) #define CONFIG_ENV_RANGE (4 * 64 * 2048) @@ -159,13 +155,10 @@ #endif /* USB Host Support */ -#define CONFIG_USB_EHCI_VF #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* USB DFU */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024) - -/* USB Storage */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #endif /* __CONFIG_H */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 749a67d4b0..e85f684e32 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -72,6 +72,7 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT #endif /* Ethernet */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 583f994807..94848f5128 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -48,7 +48,8 @@ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE +#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 55968c2749..63194d58a2 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -32,8 +32,6 @@ #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -/* SPI NOR flash default params, used by sf commands */ - /* Environment in SPI NOR flash */ #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index f1bdc2d3e7..2fdc845029 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -16,8 +16,6 @@ * Commands configuration */ -/* SPI NOR flash default params, used by sf commands */ - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index d378052a8f..ec2405bbb4 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -24,12 +24,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* - * SPI Flash configuration for the environemnt access - */ - -/* SPI NOR flash default params, used by sf commands */ - -/* * SDIO/MMC Card Configuration */ #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index b78dbcb6b9..1f9d24b19b 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -29,8 +29,6 @@ #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -/* SPI NOR flash default params, used by sf commands */ - /* Environment in SPI NOR flash */ #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h new file mode 100644 index 0000000000..0f75ad7185 --- /dev/null +++ b/include/configs/db-xc3-24g4xg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + */ + +#ifndef _CONFIG_DB_XC3_24G4G_H +#define _CONFIG_DB_XC3_24G4G_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ + +/* NAND */ +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 96 + +#endif /* _CONFIG_DB_XC3_24G4G_H */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 48514ff076..3eee382a64 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -48,11 +48,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_ARP_TIMEOUT 200UL -/* Fuses */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 10eac20aa0..f6be6595fe 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -72,10 +72,6 @@ #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_PHY_TI -/* SPI */ -#define CONFIG_TI_SPI_MMAP -#define CONFIG_QSPI_QUAD_SUPPORT - /* * Default to using SPI for environment, etc. * 0x000000 - 0x040000 : QSPI.SPL (256KiB) @@ -98,7 +94,6 @@ #endif /* SPI SPL */ -#define CONFIG_TI_EDMA3 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #define CONFIG_SUPPORT_EMMC_BOOT @@ -133,7 +128,7 @@ 50, 51, 52, 53, 54, 55, 56, 57, } #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000 /* NAND: SPL related configs */ /* NAND: SPL falcon mode configs */ #ifdef CONFIG_SPL_OS_BOOT diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 275a2b4788..192c055c5c 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -28,8 +28,6 @@ #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 -/* SPI NOR flash default params, used by sf commands */ - /* Environment in SPI NOR flash */ #define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 5142680e7d..858bed012c 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -86,7 +86,6 @@ #endif /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 3336578071..196f114c60 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -35,8 +35,6 @@ #define CONFIG_MXC_UART -#define CONFIG_MXC_OCOTP - /* SATA Configs */ #ifdef CONFIG_CMD_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 @@ -45,10 +43,6 @@ #define CONFIG_LBA48 #endif -/* MMC Configs */ -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - /* USB Configs */ #ifdef CONFIG_USB #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -77,12 +71,37 @@ #define CONFIG_LOADADDR 0x12000000 +#ifdef CONFIG_NFS_CMD +#define NETWORKBOOT \ + "setnetworkboot=" \ + "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ + "setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \ + "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ + "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ + "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ + "setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \ + "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ + "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ + "networkboot=" \ + "run setnetworkboot; " \ + "nfs ${loadaddr} /srv/nfs/fitImage; " \ + "bootm ${loadaddr}#conf@${confidx}\0" \ + +#define CONFIG_NETWORKBOOTCOMMAND \ + "run networkboot; " \ + +#else +#define NETWORKBOOT \ + +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORKBOOT \ "bootcause=POR\0" \ "image=/boot/fitImage\0" \ "fdt_high=0xffffffff\0" \ "dev=mmc\0" \ - "devnum=1\0" \ + "devnum=2\0" \ "rootdev=mmcblk0p\0" \ "quiet=quiet loglevel=0\0" \ "console=" CONSOLE_DEV "\0" \ @@ -140,13 +159,14 @@ #define CONFIG_USBBOOTCOMMAND \ "echo Unsupported; " \ -#ifdef CONFIG_CMD_USB +#ifdef CONFIG_NFS_CMD +#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND +#elif CONFIG_CMD_USB #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND #else #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND #endif -#define CONFIG_ARP_TIMEOUT 200UL /* Miscellaneous configurable options */ @@ -176,18 +196,10 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 /* Framebuffer */ -#define CONFIG_VIDEO -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_FG_COL 0xFF -#define CONFIG_SYS_CONSOLE_BG_COL 0x00 #define CONFIG_HIDE_LOGO_VERSION #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP #define CONFIG_CMD_BMP -#endif #define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 84ee44e872..93608e5aec 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -132,7 +132,6 @@ #define CONFIG_NETCONSOLE /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_LOGO #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/helios4.h b/include/configs/helios4.h index df4d8bcb3b..b2badab15e 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -23,8 +23,6 @@ * Commands configuration */ -/* SPI NOR flash default params, used by sf commands */ - /* * SDIO/MMC Card Configuration */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index a9e38a70e6..6094d1bf18 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -230,7 +230,6 @@ #define CONFIG_MXC_GPIO -#define CONFIG_MXC_OCOTP #define CONFIG_CMD_FUSE /* I2C Configs */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 2c0e4cbe92..547127490c 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -40,10 +40,6 @@ #include <configs/ti_armv7_keystone2.h> -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c100000 - - #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* NAND Configuration */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index b1aec98a37..3ec5a5acf5 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -72,9 +72,6 @@ "bootm ${fit_loadaddr}#${name_fdt}" #endif -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c0a0000 - /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 0b909a1bf6..d4f2e96bab 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -40,9 +40,6 @@ #include <configs/ti_armv7_keystone2.h> -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c200000 - #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* NAND Configuration */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 59e6b09673..cfdb36e2d7 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -40,9 +40,6 @@ #include <configs/ti_armv7_keystone2.h> -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c100000 - #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* NAND Configuration */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index b6b27ee1d5..d2ebf92953 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -31,11 +31,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_ARP_TIMEOUT 200UL -/* Fuses */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 72e62658d0..55c4e63325 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -76,9 +76,9 @@ "kernel_addr=0x00800000\0" \ "ramdisk_addr=0x01000000\0" \ "fdt_addr=0x00ff0000\0" \ - "bootcmd_legacy=ide reset " \ - "&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \ - "&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ + "bootcmd_legacy=sata init " \ + "&& load sata ${hdpart} ${kernel_addr} /uImage.buffalo "\ + "&& load sata ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ "&& bootm ${kernel_addr} ${ramdisk_addr}\0" \ "bootcmd_net=bootp ${kernel_addr} vmlinuz " \ "&& tftpboot ${ramdisk_addr} initrd.img " \ @@ -86,11 +86,11 @@ "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ "&& bootz ${kernel_addr} " \ "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ - "bootcmd_hdd=ide reset " \ - "&& load ide ${hdpart} ${kernel_addr} /vmlinuz " \ - "&& load ide ${hdpart} ${ramdisk_addr} /initrd.img " \ + "bootcmd_hdd=sata init " \ + "&& load sata ${hdpart} ${kernel_addr} /vmlinuz " \ + "&& load sata ${hdpart} ${ramdisk_addr} /initrd.img " \ "&& setenv ramdisk_len ${filesize} " \ - "&& load ide ${hdpart} ${fdt_addr} /dtb " \ + "&& load sata ${hdpart} ${fdt_addr} /dtb " \ "&& bootz ${kernel_addr} " \ "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ "bootcmd_usb=usb start " \ @@ -131,13 +131,10 @@ #undef CONFIG_RESET_PHY_R #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_IDE -#undef CONFIG_SYS_IDE_MAXBUS -#define CONFIG_SYS_IDE_MAXBUS 1 -#undef CONFIG_SYS_IDE_MAXDEVICE -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#ifdef CONFIG_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_SYS_64BIT_LBA +#define CONFIG_LBA48 #endif #endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 51456fbe55..84d061339e 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -138,7 +138,6 @@ * LCD */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index f4972b64dc..b28f3b9408 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -49,10 +49,6 @@ /* End of 16M scrubbed by training in bootrom */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) -/* - * SPI Flash configuration - */ - #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index eb172c97b3..9bf9773c69 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -68,7 +68,6 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 3ed5ee3c57..1e3ea88b77 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -161,7 +161,6 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT -#define CONFIG_VIDEO_IPUV3 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 816164e87e..2d18f05423 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -178,7 +178,6 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index d2a8e6571a..f002324fdd 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -30,10 +30,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - /* Eth Configs */ #define CONFIG_FEC_MXC @@ -89,10 +85,10 @@ "nfsroot=/opt/springdale/rd\0" \ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ - "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \ - "set getcmd dhcp; else set kern_ipconf " \ + "choose_ip=if test $use_dhcp = 1; then setenv kern_ipconf ip=dhcp; " \ + "setenv getcmd dhcp; else setenv kern_ipconf " \ "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \ - "set getcmd tftp; fi\0" \ + "setenv getcmd tftp; fi\0" \ "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ "${nfsserver}:${image}; bootm ${loadaddr}\0" \ @@ -101,7 +97,7 @@ "image=/boot/fitImage\0" \ "fdt_high=0xffffffff\0" \ "dev=mmc\0" \ - "devnum=0\0" \ + "devnum=2\0" \ "rootdev=mmcblk0p\0" \ "quiet=quiet loglevel=0\0" \ "console=" CONSOLE_DEV "\0" \ @@ -219,9 +215,4 @@ #define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66666000 -/* Framebuffer and LCD */ -#ifdef CONFIG_VIDEO - #define CONFIG_VIDEO_IPUV3 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index cdc8833778..6b20c6db58 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -57,9 +57,6 @@ /* MMC */ #define CONFIG_FSL_USDHC -/* Fuses */ -#define CONFIG_MXC_OCOTP - /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index a62e14f7c6..7b4ae2102e 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -35,7 +35,6 @@ #define CONFIG_PHY_ATHEROS /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 6fe0467229..c137612b01 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -185,7 +185,6 @@ #endif /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index a895c936aa..cc7e87269e 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -42,9 +42,6 @@ /* MMC */ #define CONFIG_FSL_USDHC -/* Fuses */ -#define CONFIG_MXC_OCOTP - #define CONFIG_ARMV7_SECURE_BASE 0x00900000 #define CONFIG_ARMV7_PSCI_1_0 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index d941caa905..afaa908406 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -58,7 +58,6 @@ #define CONFIG_MXC_USB_FLAGS 0 /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/novena.h b/include/configs/novena.h index 25736f3c03..bb5bf808c2 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -125,7 +125,6 @@ /* Video output */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 1786e099ad..6680c3e503 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -43,6 +43,9 @@ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE +#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 + /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index e125a38e7d..fb8f3c8609 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -9,6 +9,7 @@ #define __CONFIG_H #include <asm/arch/imx-regs.h> +#include <linux/sizes.h> #define CONFIG_SKIP_LOWLEVEL_INIT @@ -16,7 +17,7 @@ #define CONFIG_CMDLINE_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -24,48 +25,14 @@ /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION -#ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR - -#define CONFIG_JFFS2_NAND - -/* Dynamic MTD partition support */ - -#endif - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - /* QSPI Configs*/ - #ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_SIZE (SZ_16M) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE #endif -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC - -/* RTC (actually an RV-4162 but M41T62-compatible) */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_RTC_BUS_NUM 2 - -/* EEPROM (24FC256) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 - #define CONFIG_LOADADDR 0x82000000 @@ -188,7 +155,7 @@ /* Physical memory map */ #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) +#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -201,17 +168,17 @@ /* environment organization */ #ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE (SZ_8K) -#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_OFFSET (12 * SZ_64K) #define CONFIG_SYS_MMC_ENV_DEV 0 #endif #ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_SIZE (SZ_8K) #define CONFIG_ENV_OFFSET 0xA0000 -#define CONFIG_ENV_SIZE_REDUND (8 * 1024) +#define CONFIG_ENV_SIZE_REDUND (SZ_8K) #define CONFIG_ENV_OFFSET_REDUND 0xC0000 #endif diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 48f1f7bacc..a535d0c2f2 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -157,7 +157,6 @@ * board schematic and physical port wired to each. Then for host we * add mass storage support. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h new file mode 100644 index 0000000000..afcd22b664 --- /dev/null +++ b/include/configs/sama5d2_icp.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D2 ICP Board. + * + * Copyright (C) 2018 Microchip Corporation + * Eugen Hristev <eugen.hristev@microchip.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_MISC_INIT_R + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* SPI flash */ +#define CONFIG_SF_DEFAULT_SPEED 66000000 + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_SD_BOOT +/* u-boot env in sd/mmc card */ +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +#endif + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index f44a4280f4..1170f24748 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -150,8 +150,6 @@ /* * USB configuration */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT - #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 09c9b7ca9e..f9e2cdc1b3 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -338,6 +338,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "scriptaddr=0x02100000\0" \ "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ + "socfpga_legacy_reset_compat=1\0" \ BOOTENV #endif diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 701298cab8..737dfd6a5c 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -10,17 +10,17 @@ #include <linux/sizes.h> #include <asm/arch/stm32.h> -#define CONFIG_PREBOOT - /* * Number of clock ticks in 1 sec */ #define CONFIG_SYS_HZ 1000 +#ifndef CONFIG_STM32MP1_TRUSTED /* PSCI support */ #define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE #define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE +#endif /* * malloc() pool size @@ -53,6 +53,9 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN SZ_32M + /* SPL support */ #ifdef CONFIG_SPL /* BOOTROM load address */ @@ -69,36 +72,65 @@ STM32_SYSRAM_SIZE) #endif /* #ifdef CONFIG_SPL */ +#define CONFIG_SYS_MEMTEST_START STM32_DDR_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_64M) +#define CONFIG_SYS_MEMTEST_SCRATCH (CONFIG_SYS_MEMTEST_END + 4) + /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 #define CONFIG_SUPPORT_EMMC_BOOT -#if !defined(CONFIG_SPL) || !defined(CONFIG_SPL_BUILD) +/*****************************************************************************/ +#ifdef CONFIG_DISTRO_DEFAULTS +/*****************************************************************************/ + +#if !defined(CONFIG_SPL_BUILD) #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(MMC, mmc, 2) +/* + * bootcmd for stm32mp1: + * for serial/usb: execute the stm32prog command + * for mmc boot (eMMC, SD card), boot only on the same device + * for nand boot, boot with on ubifs partition on nand + * for nor boot, use the default order + */ +#define CONFIG_PREBOOT -#include <config_distro_bootcmd.h> +#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "if test ${boot_device} = serial || test ${boot_device} = usb;" \ + "then stm32prog ${boot_device} ${boot_instance}; " \ + "else " \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "if test ${boot_device} = nand;" \ + "then env set boot_targets ubifs0; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" -#define STM32MP_PREBOOT \ - "echo \"Boot over ${boot_device}${boot_instance}!\"; " \ - "if test \"${boot_device}\" = \"mmc\"; then " \ - "env set boot_targets \"mmc${boot_instance}\"; "\ - "fi;" +#include <config_distro_bootcmd.h> +/* + * memory layout for 32M uncompressed/compressed kernel, + * 1M fdt, 1M script, 1M pxe and 1M for splashimage + * and the ramdisk at the end. + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "scriptaddr=0xC0000000\0" \ - "pxefile_addr_r=0xC0000000\0" \ - "kernel_addr_r=0xC1000000\0" \ - "fdt_addr_r=0xC4000000\0" \ - "ramdisk_addr_r=0xC4100000\0" \ + "kernel_addr_r=0xc2000000\0" \ + "fdt_addr_r=0xc4000000\0" \ + "scriptaddr=0xc4100000\0" \ + "pxefile_addr_r=0xc4200000\0" \ + "splashimage=0xc4300000\0" \ + "ramdisk_addr_r=0xc4400000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "preboot=" STM32MP_PREBOOT "\0" \ + STM32MP_BOOTCMD \ BOOTENV #endif /* ifndef CONFIG_SPL_BUILD */ +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b01d1c3c84..a498393472 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -104,13 +104,7 @@ #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ #ifdef CONFIG_AHCI -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SUNXI_AHCI #define CONFIG_SYS_64BIT_LBA -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) #endif #define CONFIG_SETUP_MEMORY_TAGS @@ -449,7 +443,6 @@ extern int soft_i2c_gpio_scl; "stdout=serial,vga\0" \ "stderr=serial,vga\0" #elif CONFIG_DM_VIDEO -#define CONFIG_SYS_WHITE_ON_BLACK #define CONSOLE_STDOUT_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b06c90939c..a753d41835 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -40,13 +40,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ -/* Filesystems / image support */ - -/* MMC */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT - /* Ethernet */ #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC @@ -58,7 +51,6 @@ /* Framebuffer */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP @@ -77,11 +69,11 @@ #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA #endif /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #ifdef CONFIG_CMD_USB_MASS_STORAGE @@ -98,23 +90,6 @@ #endif /* CONFIG_USB_KEYBOARD */ #endif /* CONFIG_CMD_USB */ -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1307 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#endif - -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_EDID -#endif - /* Environment organization */ #define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */ #define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 59b2546f0b..cd92835112 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -39,8 +39,6 @@ #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -/* SPI NOR flash default params, used by sf commands */ - /* Environment in SPI NOR flash */ #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index fb8c082c1d..eeca085f9f 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -22,7 +22,7 @@ /* Memory Configuration */ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_ISW_ENTRY_ADDR - \ GENERATED_GBL_DATA_SIZE) #ifdef CONFIG_SYS_MALLOC_F_LEN @@ -32,9 +32,10 @@ #endif /* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR #define CONFIG_SPL_PAD_TO 65536 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_ISW_ENTRY_ADDR + \ CONFIG_SPL_MAX_SIZE) #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ @@ -132,9 +133,6 @@ #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -/* SerDes */ -#define CONFIG_TI_KEYSTONE_SERDES - #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE /* I2C Configuration */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index ba57c40182..7c08e47d3d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -56,6 +56,7 @@ #include <environment/ti/boot.h> #include <environment/ti/mmc.h> +#include <environment/ti/nand.h> #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -65,6 +66,7 @@ DEFAULT_FDT_TI_ARGS \ DFUARGS \ NETARGS \ + NANDARGS \ /* * SPL related defines. The Public RAM memory map the ROM defines the @@ -100,7 +102,6 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) - #ifdef CONFIG_SPL_BUILD #undef CONFIG_TIMER #endif diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 5d5394e3e5..0de40eddcb 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -63,10 +63,6 @@ #define CONFIG_I2C_MV #define CONFIG_SYS_I2C_SLAVE 0x0 -/* - * SPI Flash configuration - */ - /* Environment in SPI NOR flash */ #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 038f6398eb..c7805cf36b 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -34,9 +34,6 @@ # define CONFIG_WATCHDOG #endif -/* SPI NOR flash default params, used by sf commands */ -#define CONFIG_SPI_FLASH_SPANSION - /* * SDIO/MMC Card Configuration */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 2840c7b815..8c68372026 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -10,7 +10,7 @@ /* Onboard devices */ -#define CONFIG_SYS_MALLOC_LEN 0x100000 +#define CONFIG_SYS_MALLOC_LEN 0x1F0000 #define CONFIG_SYS_LOAD_ADDR 0x00100000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 @@ -27,7 +27,7 @@ #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) #define CONFIG_ENV_OFFSET (1024 * 1024) -#define CONFIG_ENV_SIZE (256 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_ENV_SECT_SIZE (256 * 1024) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 686a383739..ba85bc91e7 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -19,10 +19,6 @@ /* Enable passing of ATAGs */ #define CONFIG_CMDLINE_TAG -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index b03a1c550c..2e6262f0f4 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -32,26 +32,11 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -64,8 +49,6 @@ #define CONFIG_PHY_ATHEROS /* Framebuffer */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN @@ -74,7 +57,6 @@ #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 27a8e4d490..91ae7088a5 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -108,15 +108,6 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -/* EEPROM */ -#ifdef CONFIG_ZYNQMP_EEPROM -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -# define CONFIG_SYS_EEPROM_SIZE (64 * 1024) -#endif - #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #define CONFIG_CLOCKS diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 94177c6fcb..3ab783e3a8 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -69,7 +69,7 @@ # define CONFIG_THOR_RESET_OFF # define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ - "set dfu_alt_info " \ + "setenv dfu_alt_info " \ "${kernel_image} ram 0x3000000 0x500000\\\\;" \ "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \ "${ramdisk_image} ram 0x2000000 0x600000\0" \ @@ -79,7 +79,7 @@ # if defined(CONFIG_MMC_SDHCI_ZYNQ) # define DFU_ALT_INFO_MMC \ "dfu_mmc_info=" \ - "set dfu_alt_info " \ + "setenv dfu_alt_info " \ "${kernel_image} fat 0 1\\\\;" \ "${devicetree_image} fat 0 1\\\\;" \ "${ramdisk_image} fat 0 1\0" \ @@ -227,9 +227,9 @@ "env run importbootenv; " \ "fi; " \ "fi; \0" \ - "sd_loadbootenv=set bootenv_dev mmc && " \ + "sd_loadbootenv=setenv bootenv_dev mmc && " \ "run setbootenv \0" \ - "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \ + "usb_loadbootenv=setenv bootenv_dev usb && usb start && run setbootenv \0" \ "preboot=if test $modeboot = sdboot; then " \ "run sd_loadbootenv; " \ "echo Checking if uenvcmd is set ...; " \ diff --git a/include/cpsw.h b/include/cpsw.h index 9f8ce8850f..96ff254f98 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -16,6 +16,23 @@ #ifndef _CPSW_H_ #define _CPSW_H_ +/* reg offset */ +#define CPSW_HOST_PORT_OFFSET 0x108 +#define CPSW_SLAVE0_OFFSET 0x208 +#define CPSW_SLAVE1_OFFSET 0x308 +#define CPSW_SLAVE_SIZE 0x100 +#define CPSW_CPDMA_OFFSET 0x800 +#define CPSW_HW_STATS 0x900 +#define CPSW_STATERAM_OFFSET 0xa00 +#define CPSW_CPTS_OFFSET 0xc00 +#define CPSW_ALE_OFFSET 0xd00 +#define CPSW_SLIVER0_OFFSET 0xd80 +#define CPSW_SLIVER1_OFFSET 0xdc0 +#define CPSW_BD_OFFSET 0x2000 +#define CPSW_MDIO_DIV 0xff + +#define AM335X_GMII_SEL_OFFSET 0x630 + struct cpsw_slave_data { u32 slave_reg_ofs; u32 sliver_reg_ofs; @@ -50,10 +67,16 @@ struct cpsw_platform_data { u32 active_slave; bool rmii_clock_external; u8 version; + const char *phy_sel_compat; + u32 syscon_addr; + const char *macid_sel_compat; }; int cpsw_register(struct cpsw_platform_data *data); -int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr); +int ti_cm_get_macid_addr(struct udevice *dev, int slave, + struct cpsw_platform_data *data); +void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data, + u8 *mac_addr); int cpsw_get_slave_phy_addr(struct udevice *dev, int slave); #endif /* _CPSW_H_ */ diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index ff2b82e7c2..63a7d55b88 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -355,18 +355,6 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph); int pinctrl_decode_pin_config(const void *blob, int node); /** - * pinctrl_decode_pin_config_dm() - decode pin configuration flags - * - * This decodes some of the PIN_CONFIG values into flags, with each value - * being (1 << pin_cfg). This does not support things with values like the - * slew rate. - * - * @pinconfig: Pinconfig udevice - * @return decoded flag value, or -ve on error - */ -int pinctrl_decode_pin_config_dm(struct udevice *dev); - -/** * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO * * This allows the raw mux value for a GPIO to be obtained. It is diff --git a/include/dm/util.h b/include/dm/util.h index 9ff6531d1b..60d3b93dec 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -40,32 +40,6 @@ static inline void dm_dump_devres(void) #endif /** - * Check if a dt node should be or was bound before relocation. - * - * Devicetree nodes can be marked as needed to be bound - * in the loader stages via special devicetree properties. - * - * Before relocation this function can be used to check if nodes - * are required in either SPL or TPL stages. - * - * After relocation and jumping into the real U-Boot binary - * it is possible to determine if a node was bound in one of - * SPL/TPL stages. - * - * There are 3 settings currently in use - * - - * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL - * Existing platforms only use it to indicate nodes needed in - * SPL. Should probably be replaced by u-boot,dm-spl for - * existing platforms. - * @blob: devicetree - * @offset: node offset - * - * Returns true if node is needed in SPL/TL, false otherwise. - */ -bool dm_fdt_pre_reloc(const void *blob, int offset); - -/** * Check if an of node should be or was bound before relocation. * * Devicetree nodes can be marked as needed to be bound diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h new file mode 100644 index 0000000000..745b87f3a0 --- /dev/null +++ b/include/dt-bindings/clock/mt8516-clk.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 BayLibre, SAS + * Copyright (c) 2018 MediaTek Inc. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8516_H +#define _DT_BINDINGS_CLK_MT8516_H + + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_APLL1 4 +#define CLK_APMIXED_APLL2 5 +#define CLK_APMIXED_NR_CLK 6 + +/* TOPCKGEN */ + +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_I2S_INFRA_BCK 1 +#define CLK_TOP_MEMPLL 2 +#define CLK_TOP_DMPLL 3 +#define CLK_TOP_MAINPLL_D2 4 +#define CLK_TOP_MAINPLL_D4 5 +#define CLK_TOP_MAINPLL_D8 6 +#define CLK_TOP_MAINPLL_D16 7 +#define CLK_TOP_MAINPLL_D11 8 +#define CLK_TOP_MAINPLL_D22 9 +#define CLK_TOP_MAINPLL_D3 10 +#define CLK_TOP_MAINPLL_D6 11 +#define CLK_TOP_MAINPLL_D12 12 +#define CLK_TOP_MAINPLL_D5 13 +#define CLK_TOP_MAINPLL_D10 14 +#define CLK_TOP_MAINPLL_D20 15 +#define CLK_TOP_MAINPLL_D40 16 +#define CLK_TOP_MAINPLL_D7 17 +#define CLK_TOP_MAINPLL_D14 18 +#define CLK_TOP_UNIVPLL_D2 19 +#define CLK_TOP_UNIVPLL_D4 20 +#define CLK_TOP_UNIVPLL_D8 21 +#define CLK_TOP_UNIVPLL_D16 22 +#define CLK_TOP_UNIVPLL_D3 23 +#define CLK_TOP_UNIVPLL_D6 24 +#define CLK_TOP_UNIVPLL_D12 25 +#define CLK_TOP_UNIVPLL_D24 26 +#define CLK_TOP_UNIVPLL_D5 27 +#define CLK_TOP_UNIVPLL_D20 28 +#define CLK_TOP_MMPLL380M 29 +#define CLK_TOP_MMPLL_D2 30 +#define CLK_TOP_MMPLL_200M 31 +#define CLK_TOP_USB_PHY48M 32 +#define CLK_TOP_APLL1 33 +#define CLK_TOP_APLL1_D2 34 +#define CLK_TOP_APLL1_D4 35 +#define CLK_TOP_APLL1_D8 36 +#define CLK_TOP_APLL2 37 +#define CLK_TOP_APLL2_D2 38 +#define CLK_TOP_APLL2_D4 39 +#define CLK_TOP_APLL2_D8 40 +#define CLK_TOP_CLK26M 41 +#define CLK_TOP_CLK26M_D2 42 +#define CLK_TOP_AHB_INFRA_D2 43 +#define CLK_TOP_NFI1X 44 +#define CLK_TOP_ETH_D2 45 +#define CLK_TOP_UART0_SEL 46 +#define CLK_TOP_GFMUX_EMI1X_SEL 47 +#define CLK_TOP_EMI_DDRPHY_SEL 48 +#define CLK_TOP_AHB_INFRA_SEL 49 +#define CLK_TOP_CSW_MUX_MFG_SEL 50 +#define CLK_TOP_MSDC0_SEL 51 +#define CLK_TOP_PWM_MM_SEL 52 +#define CLK_TOP_UART1_SEL 53 +#define CLK_TOP_MSDC1_SEL 54 +#define CLK_TOP_SPM_52M_SEL 55 +#define CLK_TOP_PMICSPI_SEL 56 +#define CLK_TOP_QAXI_AUD26M_SEL 57 +#define CLK_TOP_AUD_INTBUS_SEL 58 +#define CLK_TOP_NFI2X_PAD_SEL 59 +#define CLK_TOP_NFI1X_PAD_SEL 60 +#define CLK_TOP_MFG_MM_SEL 61 +#define CLK_TOP_DDRPHYCFG_SEL 62 +#define CLK_TOP_USB_78M_SEL 63 +#define CLK_TOP_SPINOR_SEL 64 +#define CLK_TOP_MSDC2_SEL 65 +#define CLK_TOP_ETH_SEL 66 +#define CLK_TOP_AXI_MFG_IN_SEL 67 +#define CLK_TOP_SLOW_MFG_SEL 68 +#define CLK_TOP_AUD1_SEL 69 +#define CLK_TOP_AUD2_SEL 70 +#define CLK_TOP_AUD_ENGEN1_SEL 71 +#define CLK_TOP_AUD_ENGEN2_SEL 72 +#define CLK_TOP_I2C_SEL 73 +#define CLK_TOP_AUD_I2S0_M_SEL 74 +#define CLK_TOP_AUD_I2S1_M_SEL 75 +#define CLK_TOP_AUD_I2S2_M_SEL 76 +#define CLK_TOP_AUD_I2S3_M_SEL 77 +#define CLK_TOP_AUD_I2S4_M_SEL 78 +#define CLK_TOP_AUD_I2S5_M_SEL 79 +#define CLK_TOP_AUD_SPDIF_B_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_SPI_SEL 82 +#define CLK_TOP_AUD_SPDIFIN_SEL 83 +#define CLK_TOP_UART2_SEL 84 +#define CLK_TOP_BSI_SEL 85 +#define CLK_TOP_DBG_ATCLK_SEL 86 +#define CLK_TOP_CSW_NFIECC_SEL 87 +#define CLK_TOP_NFIECC_SEL 88 +#define CLK_TOP_APLL12_CK_DIV0 89 +#define CLK_TOP_APLL12_CK_DIV1 90 +#define CLK_TOP_APLL12_CK_DIV2 91 +#define CLK_TOP_APLL12_CK_DIV3 92 +#define CLK_TOP_APLL12_CK_DIV4 93 +#define CLK_TOP_APLL12_CK_DIV4B 94 +#define CLK_TOP_APLL12_CK_DIV5 95 +#define CLK_TOP_APLL12_CK_DIV5B 96 +#define CLK_TOP_APLL12_CK_DIV6 97 +#define CLK_TOP_NR_CLK 98 + +/* TOPCKGEN Gates */ +#define CLK_TOP_PWM_MM 0 +#define CLK_TOP_MFG_MM 1 +#define CLK_TOP_SPM_52M 2 +#define CLK_TOP_THEM 3 +#define CLK_TOP_APDMA 4 +#define CLK_TOP_I2C0 5 +#define CLK_TOP_I2C1 6 +#define CLK_TOP_AUXADC1 7 +#define CLK_TOP_NFI 8 +#define CLK_TOP_NFIECC 9 +#define CLK_TOP_DEBUGSYS 10 +#define CLK_TOP_PWM 11 +#define CLK_TOP_UART0 12 +#define CLK_TOP_UART1 13 +#define CLK_TOP_BTIF 14 +#define CLK_TOP_USB 15 +#define CLK_TOP_FLASHIF_26M 16 +#define CLK_TOP_AUXADC2 17 +#define CLK_TOP_I2C2 18 +#define CLK_TOP_MSDC0 19 +#define CLK_TOP_MSDC1 20 +#define CLK_TOP_NFI2X 21 +#define CLK_TOP_PMICWRAP_AP 22 +#define CLK_TOP_SEJ 23 +#define CLK_TOP_MEMSLP_DLYER 24 +#define CLK_TOP_SPI 25 +#define CLK_TOP_APXGPT 26 +#define CLK_TOP_AUDIO 27 +#define CLK_TOP_PMICWRAP_MD 28 +#define CLK_TOP_PMICWRAP_CONN 29 +#define CLK_TOP_PMICWRAP_26M 30 +#define CLK_TOP_AUX_ADC 31 +#define CLK_TOP_AUX_TP 32 +#define CLK_TOP_MSDC2 33 +#define CLK_TOP_RBIST 34 +#define CLK_TOP_NFI_BUS 35 +#define CLK_TOP_GCE 36 +#define CLK_TOP_TRNG 37 +#define CLK_TOP_SEJ_13M 38 +#define CLK_TOP_AES 39 +#define CLK_TOP_PWM_B 40 +#define CLK_TOP_PWM1_FB 41 +#define CLK_TOP_PWM2_FB 42 +#define CLK_TOP_PWM3_FB 43 +#define CLK_TOP_PWM4_FB 44 +#define CLK_TOP_PWM5_FB 45 +#define CLK_TOP_USB_1P 46 +#define CLK_TOP_FLASHIF_FREERUN 47 +#define CLK_TOP_66M_ETH 48 +#define CLK_TOP_133M_ETH 49 +#define CLK_TOP_FETH_25M 50 +#define CLK_TOP_FETH_50M 51 +#define CLK_TOP_FLASHIF_AXI 52 +#define CLK_TOP_USBIF 53 +#define CLK_TOP_UART2 54 +#define CLK_TOP_BSI 55 +#define CLK_TOP_MSDC0_INFRA 56 +#define CLK_TOP_MSDC1_INFRA 57 +#define CLK_TOP_MSDC2_INFRA 58 +#define CLK_TOP_USB_78M 59 +#define CLK_TOP_RG_SPINOR 60 +#define CLK_TOP_RG_MSDC2 61 +#define CLK_TOP_RG_ETH 62 +#define CLK_TOP_RG_AXI_MFG 63 +#define CLK_TOP_RG_SLOW_MFG 64 +#define CLK_TOP_RG_AUD1 65 +#define CLK_TOP_RG_AUD2 66 +#define CLK_TOP_RG_AUD_ENGEN1 67 +#define CLK_TOP_RG_AUD_ENGEN2 68 +#define CLK_TOP_RG_I2C 69 +#define CLK_TOP_RG_PWM_INFRA 70 +#define CLK_TOP_RG_AUD_SPDIF_IN 71 +#define CLK_TOP_RG_UART2 72 +#define CLK_TOP_RG_BSI 73 +#define CLK_TOP_RG_DBG_ATCLK 74 +#define CLK_TOP_RG_NFIECC 75 +#define CLK_TOP_RG_APLL1_D2_EN 76 +#define CLK_TOP_RG_APLL1_D4_EN 77 +#define CLK_TOP_RG_APLL1_D8_EN 78 +#define CLK_TOP_RG_APLL2_D2_EN 79 +#define CLK_TOP_RG_APLL2_D4_EN 80 +#define CLK_TOP_RG_APLL2_D8_EN 81 +#define CLK_TOP_APLL12_DIV0 82 +#define CLK_TOP_APLL12_DIV1 83 +#define CLK_TOP_APLL12_DIV2 84 +#define CLK_TOP_APLL12_DIV3 85 +#define CLK_TOP_APLL12_DIV4 86 +#define CLK_TOP_APLL12_DIV4B 87 +#define CLK_TOP_APLL12_DIV5 88 +#define CLK_TOP_APLL12_DIV5B 89 +#define CLK_TOP_APLL12_DIV6 90 + +/* INFRACFG */ + +#define CLK_IFR_MUX1_SEL 0 +#define CLK_IFR_ETH_25M_SEL 1 +#define CLK_IFR_I2C0_SEL 2 +#define CLK_IFR_I2C1_SEL 3 +#define CLK_IFR_I2C2_SEL 4 +#define CLK_IFR_NR_CLK 5 + +/* AUDIOTOP */ + +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_HDMI 7 +#define CLK_AUD_SPDF 8 +#define CLK_AUD_ADC 9 +#define CLK_AUD_DAC 10 +#define CLK_AUD_DAC_PREDIS 11 +#define CLK_AUD_TML 12 +#define CLK_AUD_NR_CLK 13 + +/* MFGCFG */ + +#define CLK_MFG_BAXI 0 +#define CLK_MFG_BMEM 1 +#define CLK_MFG_BG3D 2 +#define CLK_MFG_B26M 3 +#define CLK_MFG_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT8516_H */ diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h index 1625b8bf34..c5955b56b3 100644 --- a/include/dt-bindings/clock/r8a7790-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h index e8823410c0..aadd06c566 100644 --- a/include/dt-bindings/clock/r8a7791-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7791-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h index 72ce85cb2f..829c44db02 100644 --- a/include/dt-bindings/clock/r8a7792-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7792-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h index 7318d45d4e..49c66d8ed1 100644 --- a/include/dt-bindings/clock/r8a7793-clock.h +++ b/include/dt-bindings/clock/r8a7793-clock.h @@ -1,16 +1,8 @@ -/* +/* SPDX-License-Identifier: GPL-2.0 + * * r8a7793 clock definition * * Copyright (C) 2014 Renesas Electronics Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h index 8809b0f62d..d1ff646c31 100644 --- a/include/dt-bindings/clock/r8a7793-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7793-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index 93e99c3ffc..649f005782 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -1,11 +1,7 @@ -/* +/* SPDX-License-Identifier: GPL-2.0+ + * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright 2013 Ideas On Board SPRL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h index 9d720311ae..6314e23b51 100644 --- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h index f047eaf261..92b3e2a951 100644 --- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ @@ -54,7 +50,7 @@ #define R8A7795_CLK_CANFD 39 #define R8A7795_CLK_HDMI 40 #define R8A7795_CLK_CSI0 41 -#define R8A7795_CLK_CSIREF 42 +/* CLK_CSIREF was removed */ #define R8A7795_CLK_CP 43 #define R8A7795_CLK_CPEX 44 #define R8A7795_CLK_R 45 diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h index 1e5942695f..c0957cf458 100644 --- a/include/dt-bindings/clock/r8a7796-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2016 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2016 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ @@ -60,7 +56,7 @@ #define R8A7796_CLK_CANFD 45 #define R8A7796_CLK_HDMI 46 #define R8A7796_CLK_CSI0 47 -#define R8A7796_CLK_CSIREF 48 +/* CLK_CSIREF was removed */ #define R8A7796_CLK_CP 49 #define R8A7796_CLK_CPEX 50 #define R8A7796_CLK_R 51 diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h index 4e8ae3dee5..fd701c4e87 100644 --- a/include/dt-bindings/clock/r8a77995-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2017 Glider bvba +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2017 Glider bvba */ #ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ @@ -39,8 +35,8 @@ #define R8A77995_CLK_CRD2 24 #define R8A77995_CLK_SD0H 25 #define R8A77995_CLK_SD0 26 -#define R8A77995_CLK_SSP2 27 -#define R8A77995_CLK_SSP1 28 +/* CLK_SSP2 was removed */ +/* CLK_SSP1 was removed */ #define R8A77995_CLK_RPC 29 #define R8A77995_CLK_RPCD2 30 #define R8A77995_CLK_ZA2 31 @@ -53,5 +49,6 @@ #define R8A77995_CLK_LV0 38 #define R8A77995_CLK_LV1 39 #define R8A77995_CLK_CP 40 +#define R8A77995_CLK_CPEX 41 #endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h new file mode 100644 index 0000000000..25164d7678 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-tcon-top.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */ + +#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ +#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ + +#define CLK_TCON_TOP_TV0 0 +#define CLK_TCON_TOP_TV1 1 +#define CLK_TCON_TOP_DSI 2 + +#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/include/dt-bindings/dma/k3-udma.h b/include/dt-bindings/dma/k3-udma.h new file mode 100644 index 0000000000..670e1232b4 --- /dev/null +++ b/include/dt-bindings/dma/k3-udma.h @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + */ + +#ifndef __DT_TI_UDMA_H +#define __DT_TI_UDMA_H + +#define UDMA_TR_MODE 0 +#define UDMA_PKT_MODE 1 + +#define UDMA_DIR_TX 0 +#define UDMA_DIR_RX 1 + +#define PSIL_STATIC_TR_NONE 0 +#define PSIL_STATIC_TR_XY 1 +#define PSIL_STATIC_TR_MCAN 2 + +#define UDMA_PDMA_TR_XY(id) \ + ti,psil-config##id { \ + linux,udma-mode = <UDMA_TR_MODE>; \ + statictr-type = <PSIL_STATIC_TR_XY>; \ + } + +#define UDMA_PDMA_PKT_XY(id) \ + ti,psil-config##id { \ + linux,udma-mode = <UDMA_PKT_MODE>; \ + statictr-type = <PSIL_STATIC_TR_XY>; \ + } + +#endif /* __DT_TI_UDMA_H */ diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h new file mode 100644 index 0000000000..b2d6c83462 --- /dev/null +++ b/include/dt-bindings/mfd/st,stpmic1.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Philippe Peurichard <philippe.peurichard@st.com>, + * Pascal Paillet <p.paillet@st.com> for STMicroelectronics. + */ + +#ifndef __DT_BINDINGS_STPMIC1_H__ +#define __DT_BINDINGS_STPMIC1_H__ + +/* IRQ definitions */ +#define IT_PONKEY_F 0 +#define IT_PONKEY_R 1 +#define IT_WAKEUP_F 2 +#define IT_WAKEUP_R 3 +#define IT_VBUS_OTG_F 4 +#define IT_VBUS_OTG_R 5 +#define IT_SWOUT_F 6 +#define IT_SWOUT_R 7 + +#define IT_CURLIM_BUCK1 8 +#define IT_CURLIM_BUCK2 9 +#define IT_CURLIM_BUCK3 10 +#define IT_CURLIM_BUCK4 11 +#define IT_OCP_OTG 12 +#define IT_OCP_SWOUT 13 +#define IT_OCP_BOOST 14 +#define IT_OVP_BOOST 15 + +#define IT_CURLIM_LDO1 16 +#define IT_CURLIM_LDO2 17 +#define IT_CURLIM_LDO3 18 +#define IT_CURLIM_LDO4 19 +#define IT_CURLIM_LDO5 20 +#define IT_CURLIM_LDO6 21 +#define IT_SHORT_SWOTG 22 +#define IT_SHORT_SWOUT 23 + +#define IT_TWARN_F 24 +#define IT_TWARN_R 25 +#define IT_VINLOW_F 26 +#define IT_VINLOW_R 27 +#define IT_SWIN_F 30 +#define IT_SWIN_R 31 + +#endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/include/dt-bindings/mfd/st,stpmu1.h b/include/dt-bindings/mfd/st,stpmu1.h deleted file mode 100644 index 81982ebe2c..0000000000 --- a/include/dt-bindings/mfd/st,stpmu1.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of stpmu1 pmic driver - * - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author: Pascal Paillet <p.paillet@st.com> for STMicroelectronics. - * - * License type: GPLv2 - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __DT_BINDINGS_STPMU1_H__ -#define __DT_BINDINGS_STPMU1_H__ - -/* IRQ definitions */ -#define IT_PONKEY_F 0 -#define IT_PONKEY_R 1 -#define IT_WAKEUP_F 2 -#define IT_WAKEUP_R 3 -#define IT_VBUS_OTG_F 4 -#define IT_VBUS_OTG_R 5 -#define IT_SWOUT_F 6 -#define IT_SWOUT_R 7 - -#define IT_CURLIM_BUCK1 8 -#define IT_CURLIM_BUCK2 9 -#define IT_CURLIM_BUCK3 10 -#define IT_CURLIM_BUCK4 11 -#define IT_OCP_OTG 12 -#define IT_OCP_SWOUT 13 -#define IT_OCP_BOOST 14 -#define IT_OVP_BOOST 15 - -#define IT_CURLIM_LDO1 16 -#define IT_CURLIM_LDO2 17 -#define IT_CURLIM_LDO3 18 -#define IT_CURLIM_LDO4 19 -#define IT_CURLIM_LDO5 20 -#define IT_CURLIM_LDO6 21 -#define IT_SHORT_SWOTG 22 -#define IT_SHORT_SWOUT 23 - -#define IT_TWARN_F 24 -#define IT_TWARN_R 25 -#define IT_VINLOW_F 26 -#define IT_VINLOW_R 27 -#define IT_SWIN_F 30 -#define IT_SWIN_R 31 - -#endif /* __DT_BINDINGS_STPMU1_H__ */ diff --git a/include/dt-bindings/mscc/jr2_data.h b/include/dt-bindings/mscc/jr2_data.h new file mode 100644 index 0000000000..2f06fc5c5d --- /dev/null +++ b/include/dt-bindings/mscc/jr2_data.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _JR2_DATA_H_ +#define _JR2_DATA_H_ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(10) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(17) +#define SERDES_MAX (SERDES6G_MAX + 1) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/include/efi.h b/include/efi.h index d98441ab19..3c9d20f8c0 100644 --- a/include/efi.h +++ b/include/efi.h @@ -190,7 +190,7 @@ enum efi_mem_type { #define EFI_MEM_DESC_VERSION 1 #define EFI_PAGE_SHIFT 12 -#define EFI_PAGE_SIZE (1UL << EFI_PAGE_SHIFT) +#define EFI_PAGE_SIZE (1ULL << EFI_PAGE_SHIFT) #define EFI_PAGE_MASK (EFI_PAGE_SIZE - 1) struct efi_mem_desc { diff --git a/include/efi_loader.h b/include/efi_loader.h index 00b81c6010..f7bf732827 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -344,6 +344,9 @@ efi_status_t efi_remove_protocol(const efi_handle_t handle, void *protocol_interface); /* Delete all protocols from a handle */ efi_status_t efi_remove_all_protocols(const efi_handle_t handle); +/* Install multiple protocol interfaces */ +efi_status_t EFIAPI efi_install_multiple_protocol_interfaces + (efi_handle_t *handle, ...); /* Call this to create an event */ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( diff --git a/include/environment/ti/nand.h b/include/environment/ti/nand.h new file mode 100644 index 0000000000..f838cb3ed1 --- /dev/null +++ b/include/environment/ti/nand.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for NAND on TI boards. + */ + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#else +#define NANDARGS "" +#endif + diff --git a/include/exception.h b/include/exception.h new file mode 100644 index 0000000000..fc02490223 --- /dev/null +++ b/include/exception.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * The 'exception' command can be used for testing exception handling. + * + * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de> + */ + +static int do_exception(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + cmd_tbl_t *cp; + + if (argc != 2) + return CMD_RET_USAGE; + + /* drop sub-command parameter */ + argc--; + argv++; + + cp = find_cmd_tbl(argv[0], cmd_sub, ARRAY_SIZE(cmd_sub)); + + if (cp) + return cp->cmd(cmdtp, flag, argc, argv); + + return CMD_RET_USAGE; +} + +static int exception_complete(int argc, char * const argv[], char last_char, + int maxv, char *cmdv[]) +{ + int len = 0; + int i = 0; + cmd_tbl_t *cmdtp; + + switch (argc) { + case 1: + break; + case 2: + len = strlen(argv[1]); + break; + default: + return 0; + } + for (cmdtp = cmd_sub; cmdtp != cmd_sub + ARRAY_SIZE(cmd_sub); cmdtp++) { + if (i >= maxv - 1) + return i; + if (!strncmp(argv[1], cmdtp->name, len)) + cmdv[i++] = cmdtp->name; + } + cmdv[i] = NULL; + return i; +} + +U_BOOT_CMD_COMPLETE( + exception, 2, 0, do_exception, + "Forces an exception to occur", + exception_help_text, exception_complete +); diff --git a/include/fdtdec.h b/include/fdtdec.h index b7e35cd87c..266c58271f 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -23,15 +23,44 @@ */ typedef phys_addr_t fdt_addr_t; typedef phys_size_t fdt_size_t; + +static inline fdt32_t fdt_addr_unpack(fdt_addr_t addr, fdt32_t *upper) +{ + if (upper) +#ifdef CONFIG_PHYS_64BIT + *upper = addr >> 32; +#else + *upper = 0; +#endif + + return addr; +} + +static inline fdt32_t fdt_size_unpack(fdt_size_t size, fdt32_t *upper) +{ + if (upper) +#ifdef CONFIG_PHYS_64BIT + *upper = size >> 32; +#else + *upper = 0; +#endif + + return size; +} + #ifdef CONFIG_PHYS_64BIT #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) #define fdt_size_to_cpu(reg) be64_to_cpu(reg) +#define cpu_to_fdt_addr(reg) cpu_to_be64(reg) +#define cpu_to_fdt_size(reg) cpu_to_be64(reg) typedef fdt64_t fdt_val_t; #else #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) #define fdt_size_to_cpu(reg) be32_to_cpu(reg) +#define cpu_to_fdt_addr(reg) cpu_to_be32(reg) +#define cpu_to_fdt_size(reg) cpu_to_be32(reg) typedef fdt32_t fdt_val_t; #endif @@ -918,6 +947,26 @@ int fdtdec_decode_display_timing(const void *blob, int node, int index, struct display_timing *config); /** + * fdtdec_setup_mem_size_base_fdt() - decode and setup gd->ram_size and + * gd->ram_start + * + * Decode the /memory 'reg' property to determine the size and start of the + * first memory bank, populate the global data with the size and start of the + * first bank of memory. + * + * This function should be called from a boards dram_init(). This helper + * function allows for boards to query the device tree for DRAM size and start + * address instead of hard coding the value in the case where the memory size + * and start address cannot be detected automatically. + * + * @param blob FDT blob + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_mem_size_base_fdt(const void *blob); + +/** * fdtdec_setup_mem_size_base() - decode and setup gd->ram_size and * gd->ram_start * @@ -936,6 +985,25 @@ int fdtdec_decode_display_timing(const void *blob, int node, int index, int fdtdec_setup_mem_size_base(void); /** + * fdtdec_setup_memory_banksize_fdt() - decode and populate gd->bd->bi_dram + * + * Decode the /memory 'reg' property to determine the address and size of the + * memory banks. Use this data to populate the global data board info with the + * phys address and size of memory banks. + * + * This function should be called from a boards dram_init_banksize(). This + * helper function allows for boards to query the device tree for memory bank + * information instead of hard coding the information in cases where it cannot + * be detected automatically. + * + * @param blob FDT blob + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_memory_banksize_fdt(const void *blob); + +/** * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram * * Decode the /memory 'reg' property to determine the address and size of the @@ -953,6 +1021,146 @@ int fdtdec_setup_mem_size_base(void); int fdtdec_setup_memory_banksize(void); /** + * fdtdec_set_phandle() - sets the phandle of a given node + * + * @param blob FDT blob + * @param node offset in the FDT blob of the node whose phandle is to + * be set + * @param phandle phandle to set for the given node + * @return 0 on success or a negative error code on failure + */ +int fdtdec_set_phandle(void *blob, int node, uint32_t phandle); + +/** + * fdtdec_add_reserved_memory() - add or find a reserved-memory node + * + * If a reserved-memory node already exists for the given carveout, a phandle + * for that node will be returned. Otherwise a new node will be created and a + * phandle corresponding to it will be returned. + * + * See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + * for details on how to use reserved memory regions. + * + * As an example, consider the following code snippet: + * + * struct fdt_memory fb = { + * .start = 0x92cb3000, + * .end = 0x934b2fff, + * }; + * uint32_t phandle; + * + * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle); + * + * This results in the following subnode being added to the top-level + * /reserved-memory node: + * + * reserved-memory { + * #address-cells = <0x00000002>; + * #size-cells = <0x00000002>; + * ranges; + * + * framebuffer@92cb3000 { + * reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>; + * phandle = <0x0000004d>; + * }; + * }; + * + * If the top-level /reserved-memory node does not exist, it will be created. + * The phandle returned from the function call can be used to reference this + * reserved memory region from other nodes. + * + * See fdtdec_set_carveout() for a more elaborate example. + * + * @param blob FDT blob + * @param basename base name of the node to create + * @param carveout information about the carveout region + * @param phandlep return location for the phandle of the carveout region + * @return 0 on success or a negative error code on failure + */ +int fdtdec_add_reserved_memory(void *blob, const char *basename, + const struct fdt_memory *carveout, + uint32_t *phandlep); + +/** + * fdtdec_get_carveout() - reads a carveout from an FDT + * + * Reads information about a carveout region from an FDT. The carveout is a + * referenced by its phandle that is read from a given property in a given + * node. + * + * @param blob FDT blob + * @param node name of a node + * @param name name of the property in the given node that contains + * the phandle for the carveout + * @param index index of the phandle for which to read the carveout + * @param carveout return location for the carveout information + * @return 0 on success or a negative error code on failure + */ +int fdtdec_get_carveout(const void *blob, const char *node, const char *name, + unsigned int index, struct fdt_memory *carveout); + +/** + * fdtdec_set_carveout() - sets a carveout region for a given node + * + * Sets a carveout region for a given node. If a reserved-memory node already + * exists for the carveout, the phandle for that node will be reused. If no + * such node exists, a new one will be created and a phandle to it stored in + * a specified property of the given node. + * + * As an example, consider the following code snippet: + * + * const char *node = "/host1x@50000000/dc@54240000"; + * struct fdt_memory fb = { + * .start = 0x92cb3000, + * .end = 0x934b2fff, + * }; + * + * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", &fb); + * + * dc@54200000 is a display controller and was set up by the bootloader to + * scan out the framebuffer specified by "fb". This would cause the following + * reserved memory region to be added: + * + * reserved-memory { + * #address-cells = <0x00000002>; + * #size-cells = <0x00000002>; + * ranges; + * + * framebuffer@92cb3000 { + * reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>; + * phandle = <0x0000004d>; + * }; + * }; + * + * A "memory-region" property will also be added to the node referenced by the + * offset parameter. + * + * host1x@50000000 { + * ... + * + * dc@54240000 { + * ... + * memory-region = <0x0000004d>; + * ... + * }; + * + * ... + * }; + * + * @param blob FDT blob + * @param node name of the node to add the carveout to + * @param prop_name name of the property in which to store the phandle of + * the carveout + * @param index index of the phandle to store + * @param name base name of the reserved-memory node to create + * @param carveout information about the carveout to add + * @return 0 on success or a negative error code on failure + */ +int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, + unsigned int index, const char *name, + const struct fdt_memory *carveout); + +/** * Set up the device tree ready for use */ int fdtdec_setup(void); diff --git a/include/fpga.h b/include/fpga.h index 195f0bdd57..51de5c55f8 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -41,7 +41,7 @@ typedef struct { /* typedef fpga_desc */ unsigned int blocksize; char *interface; char *dev_part; - char *filename; + const char *filename; int fstype; } fpga_fs_info; diff --git a/include/i2c.h b/include/i2c.h index ccffc19552..a5c760c711 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -68,9 +68,11 @@ struct dm_i2c_chip { * I2C bus udevice. * * @speed_hz: Bus speed in hertz (typically 100000) + * @max_transaction_bytes: Maximal size of single I2C transfer */ struct dm_i2c_bus { int speed_hz; + int max_transaction_bytes; }; /* diff --git a/include/image.h b/include/image.h index 765ffecee0..889305cbef 100644 --- a/include/image.h +++ b/include/image.h @@ -306,6 +306,7 @@ enum { IH_COMP_COUNT, }; +#define LZ4F_MAGIC 0x184D2204 /* LZ4 Magic Number */ #define IH_MAGIC 0x27051956 /* Image Magic Number */ #define IH_NMLEN 32 /* Image Name Length */ @@ -1312,6 +1313,7 @@ int android_image_get_second(const struct andr_img_hdr *hdr, ulong *second_data, ulong *second_len); ulong android_image_get_end(const struct andr_img_hdr *hdr); ulong android_image_get_kload(const struct andr_img_hdr *hdr); +ulong android_image_get_kcomp(const struct andr_img_hdr *hdr); void android_print_contents(const struct andr_img_hdr *hdr); #endif /* CONFIG_ANDROID_BOOT_IMAGE */ diff --git a/include/linux/completion.h b/include/linux/completion.h new file mode 100644 index 0000000000..9835826d28 --- /dev/null +++ b/include/linux/completion.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPLETION_H +#define __LINUX_COMPLETION_H + +/* + * (C) Copyright 2001 Linus Torvalds + * + * Atomic wait-for-completion handler data structures. + * See kernel/sched/completion.c for details. + */ +#ifndef __UBOOT__ +#include <linux/wait.h> +#endif /* __UBOOT__ */ + +/* + * struct completion - structure used to maintain state for a "completion" + * + * This is the opaque structure used to maintain the state for a "completion". + * Completions currently use a FIFO to queue threads that have to wait for + * the "completion" event. + * + * See also: complete(), wait_for_completion() (and friends _timeout, + * _interruptible, _interruptible_timeout, and _killable), init_completion(), + * reinit_completion(), and macros DECLARE_COMPLETION(), + * DECLARE_COMPLETION_ONSTACK(). + */ +struct completion { + unsigned int done; +#ifndef __UBOOT__ + wait_queue_head_t wait; +#endif /* __UBOOT__ */ +}; + +#define init_completion_map(x, m) __init_completion(x) +#define init_completion(x) __init_completion(x) +static inline void complete_acquire(struct completion *x) {} +static inline void complete_release(struct completion *x) {} + +#define COMPLETION_INITIALIZER(work) \ + { 0, __WAIT_QUEUE_HEAD_INITIALIZER((work).wait) } + +#define COMPLETION_INITIALIZER_ONSTACK_MAP(work, map) \ + (*({ init_completion_map(&(work), &(map)); &(work); })) + +#define COMPLETION_INITIALIZER_ONSTACK(work) \ + (*({ init_completion(&work); &work; })) + +/** + * DECLARE_COMPLETION - declare and initialize a completion structure + * @work: identifier for the completion structure + * + * This macro declares and initializes a completion structure. Generally used + * for static declarations. You should use the _ONSTACK variant for automatic + * variables. + */ +#define DECLARE_COMPLETION(work) \ + struct completion work = COMPLETION_INITIALIZER(work) + +/* + * Lockdep needs to run a non-constant initializer for on-stack + * completions - so we use the _ONSTACK() variant for those that + * are on the kernel stack: + */ +/** + * DECLARE_COMPLETION_ONSTACK - declare and initialize a completion structure + * @work: identifier for the completion structure + * + * This macro declares and initializes a completion structure on the kernel + * stack. + */ +#ifdef CONFIG_LOCKDEP +# define DECLARE_COMPLETION_ONSTACK(work) \ + struct completion work = COMPLETION_INITIALIZER_ONSTACK(work) +# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) \ + struct completion work = COMPLETION_INITIALIZER_ONSTACK_MAP(work, map) +#else +# define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work) +# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) DECLARE_COMPLETION(work) +#endif + +/** + * init_completion - Initialize a dynamically allocated completion + * @x: pointer to completion structure that is to be initialized + * + * This inline function will initialize a dynamically created completion + * structure. + */ +static inline void __init_completion(struct completion *x) +{ + x->done = 0; +#ifndef __UBOOT__ + init_waitqueue_head(&x->wait); +#endif /* __UBOOT__ */ +} + +/** + * reinit_completion - reinitialize a completion structure + * @x: pointer to completion structure that is to be reinitialized + * + * This inline function should be used to reinitialize a completion structure so it can + * be reused. This is especially important after complete_all() is used. + */ +static inline void reinit_completion(struct completion *x) +{ + x->done = 0; +} + +#ifndef __UBOOT__ +extern void wait_for_completion(struct completion *); +extern void wait_for_completion_io(struct completion *); +extern int wait_for_completion_interruptible(struct completion *x); +extern int wait_for_completion_killable(struct completion *x); +extern unsigned long wait_for_completion_timeout(struct completion *x, + unsigned long timeout); +extern unsigned long wait_for_completion_io_timeout(struct completion *x, + unsigned long timeout); +extern long wait_for_completion_interruptible_timeout( + struct completion *x, unsigned long timeout); +extern long wait_for_completion_killable_timeout( + struct completion *x, unsigned long timeout); +extern bool try_wait_for_completion(struct completion *x); +extern bool completion_done(struct completion *x); + +extern void complete(struct completion *); +extern void complete_all(struct completion *); + +#else /* __UBOOT __ */ + +#define wait_for_completion(x) do {} while (0) +#define wait_for_completion_io(x) do {} while (0) + +inline int wait_for_completion_interruptible(struct completion *x) +{ + return 1; +} +inline int wait_for_completion_killable(struct completion *x) +{ + return 1; +} +inline unsigned long wait_for_completion_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline unsigned long wait_for_completion_io_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline long wait_for_completion_interruptible_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline long wait_for_completion_killable_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline bool try_wait_for_completion(struct completion *x) +{ + return 1; +} +inline bool completion_done(struct completion *x) +{ + return 1; +} + +#define complete(x) do {} while (0) +#define complete_all(x) do {} while (0) +#endif /* __UBOOT__ */ + +#endif diff --git a/include/linux/io.h b/include/linux/io.h index 9badab49b0..79847886be 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -65,8 +65,8 @@ static inline void __iomem *ioremap(resource_size_t offset, static inline void iounmap(void __iomem *addr) { } +#endif #define devm_ioremap(dev, offset, size) ioremap(offset, size) -#endif #endif /* _LINUX_IO_H */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index cd1f557a2f..e3549f0a46 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -392,7 +392,7 @@ static inline void mtd_set_ooblayout(struct mtd_info *mtd, mtd->ooblayout = ooblayout; } -static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops) +static inline u32 mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops) { return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize; } diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 9f5dc81aca..bd373b9617 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -15,6 +15,7 @@ #include <config.h> +#include <dm/device.h> #include <linux/compat.h> #include <linux/mtd/mtd.h> #include <linux/mtd/flashchip.h> @@ -498,6 +499,13 @@ struct nand_hw_control { struct nand_chip *active; }; +static inline void nand_hw_control_init(struct nand_hw_control *nfc) +{ + nfc->active = NULL; + spin_lock_init(&nfc->lock); + init_waitqueue_head(&nfc->wq); +} + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -961,6 +969,17 @@ struct nand_chip { void *priv; }; +static inline void nand_set_flash_node(struct nand_chip *chip, + ofnode node) +{ + chip->flash_node = ofnode_to_offset(node); +} + +static inline ofnode nand_get_flash_node(struct nand_chip *chip) +{ + return offset_to_ofnode(chip->flash_node); +} + static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) { return container_of(mtd, struct nand_chip, mtd); @@ -1280,4 +1299,34 @@ int nand_maximize_ecc(struct nand_chip *chip, /* Reset and initialize a NAND device */ int nand_reset(struct nand_chip *chip, int chipnr); + +/* NAND operation helpers */ +int nand_reset_op(struct nand_chip *chip); +int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, + unsigned int len); +int nand_status_op(struct nand_chip *chip, u8 *status); +int nand_exit_status_op(struct nand_chip *chip); +int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); +int nand_read_page_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, void *buf, unsigned int len); +int nand_change_read_column_op(struct nand_chip *chip, + unsigned int offset_in_page, void *buf, + unsigned int len, bool force_8bit); +int nand_read_oob_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, void *buf, unsigned int len); +int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, const void *buf, + unsigned int len); +int nand_prog_page_end_op(struct nand_chip *chip); +int nand_prog_page_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, const void *buf, + unsigned int len); +int nand_change_write_column_op(struct nand_chip *chip, + unsigned int offset_in_page, const void *buf, + unsigned int len, bool force_8bit); +int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, + bool force_8bit); +int nand_write_data_op(struct nand_chip *chip, const void *buf, + unsigned int len, bool force_8bit); + #endif /* __LINUX_MTD_RAWNAND_H */ diff --git a/include/linux/soc/ti/cppi5.h b/include/linux/soc/ti/cppi5.h new file mode 100644 index 0000000000..34038b31f7 --- /dev/null +++ b/include/linux/soc/ti/cppi5.h @@ -0,0 +1,995 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * CPPI5 descriptors interface + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + */ + +#ifndef __TI_CPPI5_H__ +#define __TI_CPPI5_H__ + +#include <hexdump.h> +#include <linux/bitops.h> + +/** + * Descriptor header, present in all types of descriptors + */ +struct cppi5_desc_hdr_t { + u32 pkt_info0; /* Packet info word 0 (n/a in Buffer desc) */ + u32 pkt_info1; /* Packet info word 1 (n/a in Buffer desc) */ + u32 pkt_info2; /* Packet info word 2 Buffer reclamation info */ + u32 src_dst_tag; /* Packet info word 3 (n/a in Buffer desc) */ +} __packed; + +/** + * Host-mode packet and buffer descriptor definition + */ +struct cppi5_host_desc_t { + struct cppi5_desc_hdr_t hdr; + u64 next_desc; /* w4/5: Linking word */ + u64 buf_ptr; /* w6/7: Buffer pointer */ + u32 buf_info1; /* w8: Buffer valid data length */ + u32 org_buf_len; /* w9: Original buffer length */ + u64 org_buf_ptr; /* w10/11: Original buffer pointer */ + u32 epib[0]; /* Extended Packet Info Data (optional, 4 words) */ + /* + * Protocol Specific Data (optional, 0-128 bytes in multiples of 4), + * and/or Other Software Data (0-N bytes, optional) + */ +} __packed; + +#define CPPI5_DESC_MIN_ALIGN (16U) + +#define CPPI5_INFO0_HDESC_EPIB_SIZE (16U) +#define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE (128U) + +#define CPPI5_INFO0_HDESC_TYPE_SHIFT (30U) +#define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30) +#define CPPI5_INFO0_DESC_TYPE_VAL_HOST (1U) +#define CPPI5_INFO0_DESC_TYPE_VAL_MONO (2U) +#define CPPI5_INFO0_DESC_TYPE_VAL_TR (3U) +#define CPPI5_INFO0_HDESC_EPIB_PRESENT BIT(29) +/* + * Protocol Specific Words location: + * 0 - located in the descriptor, + * 1 = located in the SOP Buffer immediately prior to the data. + */ +#define CPPI5_INFO0_HDESC_PSINFO_LOCATION BIT(28) +#define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT (22U) +#define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22) +#define CPPI5_INFO0_HDESC_PKTLEN_SHIFT (0) +#define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0) + +#define CPPI5_INFO1_DESC_PKTERROR_SHIFT (28U) +#define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28) +#define CPPI5_INFO1_HDESC_PSFLGS_SHIFT (24U) +#define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24) +#define CPPI5_INFO1_DESC_PKTID_SHIFT (14U) +#define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14) +#define CPPI5_INFO1_DESC_FLOWID_SHIFT (0) +#define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0) + +#define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT (27U) +#define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27) +/* Return Policy: 0 - Entire packet 1 - Each buffer */ +#define CPPI5_INFO2_HDESC_RETPOLICY BIT(18) +/* + * Early Return: + * 0 = desc pointers should be returned after all reads have been completed + * 1 = desc pointers should be returned immediately upon fetching + * the descriptor and beginning to transfer data. + */ +#define CPPI5_INFO2_HDESC_EARLYRET BIT(17) +/* + * Return Push Policy: + * 0 = Descriptor must be returned to tail of queue + * 1 = Descriptor must be returned to head of queue + */ +#define CPPI5_INFO2_DESC_RETPUSHPOLICY BIT(16) +#define CPPI5_INFO2_DESC_RETQ_SHIFT (0) +#define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0) + +#define CPPI5_INFO3_DESC_SRCTAG_SHIFT (16U) +#define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16) +#define CPPI5_INFO3_DESC_DSTTAG_SHIFT (0) +#define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0) + +#define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT (0) +#define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0) + +#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT (0) +#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0) + +/* + * Host Packet Descriptor Extended Packet Info Block + */ +struct cppi5_desc_epib_t { + u32 timestamp; /* w0: application specific timestamp */ + u32 sw_info0; /* w1: Software Info 0 */ + u32 sw_info1; /* w2: Software Info 1 */ + u32 sw_info2; /* w3: Software Info 2 */ +}; + +/** + * Monolithic-mode packet descriptor + */ +struct cppi5_monolithic_desc_t { + struct cppi5_desc_hdr_t hdr; + u32 epib[0]; /* Extended Packet Info Data (optional, 4 words) */ + /* + * Protocol Specific Data (optional, 0-128 bytes in multiples of 4), + * and/or Other Software Data (0-N bytes, optional) + */ +}; + +#define CPPI5_INFO2_MDESC_DATA_OFFSET_SHIFT (18U) +#define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK GENMASK(26, 18) + +/* + * Reload Enable: + * 0 = Finish the packet and place the descriptor back on the return queue + * 1 = Vector to the Reload Index and resume processing + */ +#define CPPI5_INFO0_TRDESC_RLDCNT_SHIFT (20U) +#define CPPI5_INFO0_TRDESC_RLDCNT_MASK GENMASK(28, 20) +#define CPPI5_INFO0_TRDESC_RLDCNT_MAX (0x1ff) +#define CPPI5_INFO0_TRDESC_RLDCNT_INFINITE CPPI5_INFO0_TRDESC_RLDCNT_MAX +#define CPPI5_INFO0_TRDESC_RLDIDX_SHIFT (14U) +#define CPPI5_INFO0_TRDESC_RLDIDX_MASK GENMASK(19, 14) +#define CPPI5_INFO0_TRDESC_RLDIDX_MAX (0x3f) +#define CPPI5_INFO0_TRDESC_LASTIDX_SHIFT (0) +#define CPPI5_INFO0_TRDESC_LASTIDX_MASK GENMASK(13, 0) + +#define CPPI5_INFO1_TRDESC_RECSIZE_SHIFT (24U) +#define CPPI5_INFO1_TRDESC_RECSIZE_MASK GENMASK(26, 24) +#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_16B (0) +#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_32B (1U) +#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_64B (2U) +#define CPPI5_INFO1_TRDESC_RECSIZE_VAL_128B (3U) + +static inline void cppi5_desc_dump(void *desc, u32 size) +{ + print_hex_dump(KERN_ERR "dump udmap_desc: ", DUMP_PREFIX_NONE, + 32, 4, desc, size, false); +} + +/** + * cppi5_desc_get_type - get descriptor type + * @desc_hdr: packet descriptor/TR header + * + * Returns descriptor type: + * CPPI5_INFO0_DESC_TYPE_VAL_HOST + * CPPI5_INFO0_DESC_TYPE_VAL_MONO + * CPPI5_INFO0_DESC_TYPE_VAL_TR + */ +static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr) +{ + WARN_ON(!desc_hdr); + + return (desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_TYPE_MASK) >> + CPPI5_INFO0_HDESC_TYPE_SHIFT; +} + +/** + * cppi5_desc_get_errflags - get Error Flags from Desc + * @desc_hdr: packet/TR descriptor header + * + * Returns Error Flags from Packet/TR Descriptor + */ +static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr) +{ + WARN_ON(!desc_hdr); + + return (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTERROR_MASK) >> + CPPI5_INFO1_DESC_PKTERROR_SHIFT; +} + +/** + * cppi5_desc_get_pktids - get Packet and Flow ids from Desc + * @desc_hdr: packet/TR descriptor header + * @pkt_id: Packet ID + * @flow_id: Flow ID + * + * Returns Packet and Flow ids from packet/TR descriptor + */ +static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr, + u32 *pkt_id, u32 *flow_id) +{ + WARN_ON(!desc_hdr); + + *pkt_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTID_MASK) >> + CPPI5_INFO1_DESC_PKTID_SHIFT; + *flow_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_FLOWID_MASK) >> + CPPI5_INFO1_DESC_FLOWID_SHIFT; +} + +/** + * cppi5_desc_set_pktids - set Packet and Flow ids in Desc + * @desc_hdr: packet/TR descriptor header + * @pkt_id: Packet ID + * @flow_id: Flow ID + */ +static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr, + u32 pkt_id, u32 flow_id) +{ + WARN_ON(!desc_hdr); + + desc_hdr->pkt_info1 |= (pkt_id << CPPI5_INFO1_DESC_PKTID_SHIFT) & + CPPI5_INFO1_DESC_PKTID_MASK; + desc_hdr->pkt_info1 |= (flow_id << CPPI5_INFO1_DESC_FLOWID_SHIFT) & + CPPI5_INFO1_DESC_FLOWID_MASK; +} + +/** + * cppi5_desc_set_retpolicy - set Packet Return Policy in Desc + * @desc_hdr: packet/TR descriptor header + * @flags: fags, supported values + * CPPI5_INFO2_HDESC_RETPOLICY + * CPPI5_INFO2_HDESC_EARLYRET + * CPPI5_INFO2_DESC_RETPUSHPOLICY + * @return_ring_id: Packet Return Queue/Ring id, value 0xFFFF reserved + */ +static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr, + u32 flags, u32 return_ring_id) +{ + WARN_ON(!desc_hdr); + + desc_hdr->pkt_info2 |= flags; + desc_hdr->pkt_info2 |= return_ring_id & CPPI5_INFO2_DESC_RETQ_MASK; +} + +/** + * cppi5_desc_get_tags_ids - get Packet Src/Dst Tags from Desc + * @desc_hdr: packet/TR descriptor header + * @src_tag_id: Source Tag + * @dst_tag_id: Dest Tag + * + * Returns Packet Src/Dst Tags from packet/TR descriptor + */ +static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr, + u32 *src_tag_id, u32 *dst_tag_id) +{ + WARN_ON(!desc_hdr); + + if (src_tag_id) + *src_tag_id = (desc_hdr->src_dst_tag & + CPPI5_INFO3_DESC_SRCTAG_MASK) >> + CPPI5_INFO3_DESC_SRCTAG_SHIFT; + if (dst_tag_id) + *dst_tag_id = desc_hdr->src_dst_tag & + CPPI5_INFO3_DESC_DSTTAG_MASK; +} + +/** + * cppi5_desc_set_tags_ids - set Packet Src/Dst Tags in HDesc + * @desc_hdr: packet/TR descriptor header + * @src_tag_id: Source Tag + * @dst_tag_id: Dest Tag + * + * Returns Packet Src/Dst Tags from packet/TR descriptor + */ +static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr, + u32 src_tag_id, u32 dst_tag_id) +{ + WARN_ON(!desc_hdr); + + desc_hdr->src_dst_tag = (src_tag_id << CPPI5_INFO3_DESC_SRCTAG_SHIFT) & + CPPI5_INFO3_DESC_SRCTAG_MASK; + desc_hdr->src_dst_tag |= dst_tag_id & CPPI5_INFO3_DESC_DSTTAG_MASK; +} + +/** + * cppi5_hdesc_calc_size - Calculate Host Packet Descriptor size + * @epib: is EPIB present + * @psdata_size: PSDATA size + * @sw_data_size: SWDATA size + * + * Returns required Host Packet Descriptor size + * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE + */ +static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size, + u32 sw_data_size) +{ + u32 desc_size; + + if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE) + return 0; + //TODO_GS: align + desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size + + sw_data_size; + + if (epib) + desc_size += CPPI5_INFO0_HDESC_EPIB_SIZE; + + return ALIGN(desc_size, CPPI5_DESC_MIN_ALIGN); +} + +/** + * cppi5_hdesc_init - Init Host Packet Descriptor size + * @desc: Host packet descriptor + * @flags: supported values + * CPPI5_INFO0_HDESC_EPIB_PRESENT + * CPPI5_INFO0_HDESC_PSINFO_LOCATION + * @psdata_size: PSDATA size + * + * Returns required Host Packet Descriptor size + * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE + */ +static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags, + u32 psdata_size) +{ + WARN_ON(!desc); + WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE); + WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT | + CPPI5_INFO0_HDESC_PSINFO_LOCATION)); + + desc->hdr.pkt_info0 = (CPPI5_INFO0_DESC_TYPE_VAL_HOST << + CPPI5_INFO0_HDESC_TYPE_SHIFT) | (flags); + desc->hdr.pkt_info0 |= ((psdata_size >> 2) << + CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) & + CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK; + desc->next_desc = 0; +} + +/** + * cppi5_hdesc_update_flags - Replace descriptor flags + * @desc: Host packet descriptor + * @flags: supported values + * CPPI5_INFO0_HDESC_EPIB_PRESENT + * CPPI5_INFO0_HDESC_PSINFO_LOCATION + */ +static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc, + u32 flags) +{ + WARN_ON(!desc); + WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT | + CPPI5_INFO0_HDESC_PSINFO_LOCATION)); + + desc->hdr.pkt_info0 &= ~(CPPI5_INFO0_HDESC_EPIB_PRESENT | + CPPI5_INFO0_HDESC_PSINFO_LOCATION); + desc->hdr.pkt_info0 |= flags; +} + +/** + * cppi5_hdesc_update_psdata_size - Replace PSdata size + * @desc: Host packet descriptor + * @psdata_size: PSDATA size + */ +static inline void cppi5_hdesc_update_psdata_size( + struct cppi5_host_desc_t *desc, u32 psdata_size) +{ + WARN_ON(!desc); + WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE); + + desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK; + desc->hdr.pkt_info0 |= ((psdata_size >> 2) << + CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) & + CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK; +} + +/** + * cppi5_hdesc_get_psdata_size - get PSdata size in bytes + * @desc: Host packet descriptor + */ +static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc) +{ + u32 psdata_size = 0; + + WARN_ON(!desc); + + if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)) + psdata_size = (desc->hdr.pkt_info0 & + CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >> + CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT; + + return (psdata_size << 2); +} + +/** + * cppi5_hdesc_get_pktlen - get Packet Length from HDesc + * @desc: Host packet descriptor + * + * Returns Packet Length from Host Packet Descriptor + */ +static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc) +{ + WARN_ON(!desc); + + return (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PKTLEN_MASK); +} + +/** + * cppi5_hdesc_set_pktlen - set Packet Length in HDesc + * @desc: Host packet descriptor + */ +static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc, + u32 pkt_len) +{ + WARN_ON(!desc); + + desc->hdr.pkt_info0 |= (pkt_len & CPPI5_INFO0_HDESC_PKTLEN_MASK); +} + +/** + * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc + * @desc: Host packet descriptor + * + * Returns Protocol Specific Flags from Host Packet Descriptor + */ +static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc) +{ + WARN_ON(!desc); + + return (desc->hdr.pkt_info1 & CPPI5_INFO1_HDESC_PSFLGS_MASK) >> + CPPI5_INFO1_HDESC_PSFLGS_SHIFT; +} + +/** + * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc + * @desc: Host packet descriptor + */ +static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc, + u32 ps_flags) +{ + WARN_ON(!desc); + + desc->hdr.pkt_info1 |= (ps_flags << + CPPI5_INFO1_HDESC_PSFLGS_SHIFT) & + CPPI5_INFO1_HDESC_PSFLGS_MASK; +} + +/** + * cppi5_hdesc_get_errflags - get Packet Type from HDesc + * @desc: Host packet descriptor + */ +static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc) +{ + WARN_ON(!desc); + + return (desc->hdr.pkt_info2 & CPPI5_INFO2_HDESC_PKTTYPE_MASK) >> + CPPI5_INFO2_HDESC_PKTTYPE_SHIFT; +} + +/** + * cppi5_hdesc_get_errflags - set Packet Type in HDesc + * @desc: Host packet descriptor + * @pkt_type: Packet Type + */ +static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc, + u32 pkt_type) +{ + WARN_ON(!desc); + desc->hdr.pkt_info2 |= + (pkt_type << CPPI5_INFO2_HDESC_PKTTYPE_SHIFT) & + CPPI5_INFO2_HDESC_PKTTYPE_MASK; +} + +/** + * cppi5_hdesc_attach_buf - attach buffer to HDesc + * @desc: Host packet descriptor + * @buf: Buffer physical address + * @buf_data_len: Buffer length + * @obuf: Original Buffer physical address + * @obuf_len: Original Buffer length + * + * Attaches buffer to Host Packet Descriptor + */ +static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc, + dma_addr_t buf, u32 buf_data_len, + dma_addr_t obuf, u32 obuf_len) +{ + WARN_ON(!desc); + WARN_ON(!buf && !obuf); + + desc->buf_ptr = buf; + desc->buf_info1 = buf_data_len & CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK; + desc->org_buf_ptr = obuf; + desc->org_buf_len = obuf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK; +} + +static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc, + dma_addr_t *obuf, u32 *obuf_len) +{ + WARN_ON(!desc); + WARN_ON(!obuf); + WARN_ON(!obuf_len); + + *obuf = desc->org_buf_ptr; + *obuf_len = desc->org_buf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK; +} + +static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc) +{ + WARN_ON(!desc); + + desc->buf_ptr = desc->org_buf_ptr; + desc->buf_info1 = desc->org_buf_len; +} + +/** + * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc + * @desc: Host Packet Descriptor + * @buf_desc: Host Buffer Descriptor physical address + * + * add and link Host Buffer Descriptor to HDesc + */ +static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc, + dma_addr_t hbuf_desc) +{ + WARN_ON(!desc); + WARN_ON(!hbuf_desc); + + desc->next_desc = hbuf_desc; +} + +static inline dma_addr_t cppi5_hdesc_get_next_hbdesc( + struct cppi5_host_desc_t *desc) +{ + WARN_ON(!desc); + + return (dma_addr_t)desc->next_desc; +} + +static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc) +{ + WARN_ON(!desc); + + desc->hdr = (struct cppi5_desc_hdr_t) { 0 }; + desc->next_desc = 0; +} + +/** + * cppi5_hdesc_epib_present - check if EPIB present + * @desc_hdr: packet descriptor/TR header + * + * Returns true if EPIB present in the packet + */ +static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr) +{ + WARN_ON(!desc_hdr); + return !!(desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_EPIB_PRESENT); +} + +/** + * cppi5_hdesc_get_psdata - Get pointer on PSDATA + * @desc: Host packet descriptor + * + * Returns pointer on PSDATA in HDesc. + * NULL - if ps_data placed at the start of data buffer. + */ +static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc) +{ + u32 psdata_size; + void *psdata; + + WARN_ON(!desc); + + if (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION) + return NULL; + + psdata_size = (desc->hdr.pkt_info0 & + CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >> + CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT; + + if (!psdata_size) + return NULL; + + psdata = &desc->epib; + + if (cppi5_hdesc_epib_present(&desc->hdr)) + psdata += CPPI5_INFO0_HDESC_EPIB_SIZE; + + return psdata; +} + +static inline u32 *cppi5_hdesc_get_psdata32(struct cppi5_host_desc_t *desc) +{ + return (u32 *)cppi5_hdesc_get_psdata(desc); +} + +/** + * cppi5_hdesc_get_swdata - Get pointer on swdata + * @desc: Host packet descriptor + * + * Returns pointer on SWDATA in HDesc. + * NOTE. It's caller responsibility to be sure hdesc actually has swdata. + */ +static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc) +{ + u32 psdata_size = 0; + void *swdata; + + WARN_ON(!desc); + + if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)) + psdata_size = (desc->hdr.pkt_info0 & + CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >> + CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT; + + swdata = &desc->epib; + + if (cppi5_hdesc_epib_present(&desc->hdr)) + swdata += CPPI5_INFO0_HDESC_EPIB_SIZE; + + swdata += (psdata_size << 2); + + return swdata; +} + +/* ================================== TR ================================== */ + +#define CPPI5_TR_TYPE_SHIFT (0U) +#define CPPI5_TR_TYPE_MASK GENMASK(3, 0) +#define CPPI5_TR_STATIC BIT(4) +#define CPPI5_TR_WAIT BIT(5) +#define CPPI5_TR_EVENT_SIZE_SHIFT (6U) +#define CPPI5_TR_EVENT_SIZE_MASK GENMASK(7, 6) +#define CPPI5_TR_TRIGGER0_SHIFT (8U) +#define CPPI5_TR_TRIGGER0_MASK GENMASK(9, 8) +#define CPPI5_TR_TRIGGER0_TYPE_SHIFT (10U) +#define CPPI5_TR_TRIGGER0_TYPE_MASK GENMASK(11, 10) +#define CPPI5_TR_TRIGGER1_SHIFT (12U) +#define CPPI5_TR_TRIGGER1_MASK GENMASK(13, 12) +#define CPPI5_TR_TRIGGER1_TYPE_SHIFT (14U) +#define CPPI5_TR_TRIGGER1_TYPE_MASK GENMASK(15, 14) +#define CPPI5_TR_CMD_ID_SHIFT (16U) +#define CPPI5_TR_CMD_ID_MASK GENMASK(23, 16) +#define CPPI5_TR_CSF_FLAGS_SHIFT (24U) +#define CPPI5_TR_CSF_FLAGS_MASK GENMASK(31, 24) +#define CPPI5_TR_CSF_SA_INDIRECT BIT(0) +#define CPPI5_TR_CSF_DA_INDIRECT BIT(1) +#define CPPI5_TR_CSF_SUPR_EVT BIT(2) +#define CPPI5_TR_CSF_EOL_ADV_SHIFT (4U) +#define CPPI5_TR_CSF_EOL_ADV_MASK GENMASK(6, 4) +#define CPPI5_TR_CSF_EOP BIT(7) + +/* Udmap TR flags Type field specifies the type of TR. */ +enum cppi5_tr_types { + /* type0: One dimensional data move */ + CPPI5_TR_TYPE0 = 0, + /* type1: Two dimensional data move */ + CPPI5_TR_TYPE1, + /* type2: Three dimensional data move */ + CPPI5_TR_TYPE2, + /* type3: Four dimensional data move */ + CPPI5_TR_TYPE3, + /* type4: Four dimensional data move with data formatting */ + CPPI5_TR_TYPE4, + /* type5: Four dimensional Cache Warm */ + CPPI5_TR_TYPE5, + /* type6-7: Reserved */ + /* type8: Four Dimensional Block Move */ + CPPI5_TR_TYPE8 = 8, + /* type9: Four Dimensional Block Move with Repacking */ + CPPI5_TR_TYPE9, + /* type10: Two Dimensional Block Move */ + CPPI5_TR_TYPE10, + /* type11: Two Dimensional Block Move with Repacking */ + CPPI5_TR_TYPE11, + /* type12-14: Reserved */ + /* type15 Four Dimensional Block Move with Repacking and Indirection */ + CPPI5_TR_TYPE15 = 15, + CPPI5_TR_TYPE_MAX +}; + +/* + * Udmap TR Flags EVENT_SIZE field specifies when an event is generated + * for each TR. + */ +enum cppi5_tr_event_size { + /* When TR is complete and all status for the TR has been received */ + CPPI5_TR_EVENT_SIZE_COMPLETION, + /* + * Type 0: when the last data transaction is sent for the TR; + * Type 1-11: when ICNT1 is decremented + */ + CPPI5_TR_EVENT_SIZE_ICNT1_DEC, + /* + * Type 0-1,10-11: when the last data transaction is sent for the TR; + * All other types: when ICNT2 is decremented + */ + CPPI5_TR_EVENT_SIZE_ICNT2_DEC, + /* + * Type 0-2,10-11: when the last data transaction is sent for the TR; + * All other types: when ICNT3 is decremented + */ + CPPI5_TR_EVENT_SIZE_ICNT3_DEC, + CPPI5_TR_EVENT_SIZE_MAX +}; + +/* + * Udmap TR Flags TRIGGERx field specifies the type of trigger used to + * enable the TR to transfer data as specified by TRIGGERx_TYPE field. + */ +enum cppi5_tr_trigger { + CPPI5_TR_TRIGGER_NONE, /* No Trigger */ + CPPI5_TR_TRIGGER_GLOBAL0, /* Global Trigger 0 */ + CPPI5_TR_TRIGGER_GLOBAL1, /* Global Trigger 1 */ + CPPI5_TR_TRIGGER_LOCAL_EVENT, /* Local Event */ + CPPI5_TR_TRIGGER_MAX +}; + +/* + * Udmap TR Flags TRIGGERx_TYPE field specifies the type of data transfer + * that will be enabled by receiving a trigger as specified by TRIGGERx. + */ +enum cppi5_tr_trigger_type { + /* The second inner most loop (ICNT1) will be decremented by 1 */ + CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC, + /* The third inner most loop (ICNT2) will be decremented by 1 */ + CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, + /* The outer most loop (ICNT3) will be decremented by 1 */ + CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC, + /* The entire TR will be allowed to complete */ + CPPI5_TR_TRIGGER_TYPE_ALL, + CPPI5_TR_TRIGGER_TYPE_MAX +}; + +typedef u32 cppi5_tr_flags_t; + +/* Type 0 (One dimensional data move) TR (16 byte) */ +struct cppi5_tr_type0_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 unused; + u64 addr; +} __aligned(16) __packed; + +/* Type 1 (Two dimensional data move) TR (32 byte) */ +struct cppi5_tr_type1_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; +} __aligned(32) __packed; + +/* Type 2 (Three dimensional data move) TR (32 byte) */ +struct cppi5_tr_type2_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; + u16 icnt2; + u16 unused; + s32 dim2; +} __aligned(32) __packed; + +/* Type 3 (Four dimensional data move) TR (32 byte) */ +struct cppi5_tr_type3_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; + u16 icnt2; + u16 icnt3; + s32 dim2; + s32 dim3; +} __aligned(32) __packed; + +/* + * Type 15 (Four Dimensional Block Copy with Repacking and + * Indirection Support) TR (64 byte). + */ +struct cppi5_tr_type15_t { + cppi5_tr_flags_t flags; + u16 icnt0; + u16 icnt1; + u64 addr; + s32 dim1; + u16 icnt2; + u16 icnt3; + s32 dim2; + s32 dim3; + u32 _reserved; + s32 ddim1; + u64 daddr; + s32 ddim2; + s32 ddim3; + u16 dicnt0; + u16 dicnt1; + u16 dicnt2; + u16 dicnt3; +} __aligned(64) __packed; + +struct cppi5_tr_resp_t { + u8 status; + u8 reserved; + u8 cmd_id; + u8 flags; +} __packed; + +#define CPPI5_TR_RESPONSE_STATUS_TYPE_SHIFT (0U) +#define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK GENMASK(3, 0) +#define CPPI5_TR_RESPONSE_STATUS_INFO_SHIFT (4U) +#define CPPI5_TR_RESPONSE_STATUS_INFO_MASK GENMASK(7, 4) +#define CPPI5_TR_RESPONSE_CMDID_SHIFT (16U) +#define CPPI5_TR_RESPONSE_CMDID_MASK GENMASK(23, 16) +#define CPPI5_TR_RESPONSE_CFG_SPECIFIC_SHIFT (24U) +#define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK GENMASK(31, 24) + +/* + * Udmap TR Response Status Type field is used to determine + * what type of status is being returned. + */ +enum cppi5_tr_resp_status_type { + CPPI5_TR_RESPONSE_STATUS_COMPLETE, /* None */ + CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR, /* Transfer Error */ + CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR, /* Aborted Error */ + CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR, /* Submission Error */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR, /* Unsup. Feature */ + CPPI5_TR_RESPONSE_STATUS_MAX +}; + +/* + * Udmap TR Response Status field values which corresponds + * CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR + */ +enum cppi5_tr_resp_status_submission { + /* ICNT0 was 0 */ + CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0, + /* Channel FIFO was full when TR received */ + CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL, + /* Channel is not owned by the submitter */ + CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN, + CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX +}; + +/* + * Udmap TR Response Status field values which corresponds + * CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR + */ +enum cppi5_tr_resp_status_unsupported { + /* TR Type not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE, + /* STATIC not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC, + /* EOL not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL, + /* CONFIGURATION SPECIFIC not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC, + /* AMODE not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE, + /* ELTYPE not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE, + /* DFMT not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT, + /* SECTR not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR, + /* AMODE SPECIFIC field not supported */ + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC, + CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX +}; + +/** + * cppi5_trdesc_calc_size - Calculate TR Descriptor size + * @tr_count: number of TR records + * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128] + * + * Returns required TR Descriptor size + */ +static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size) +{ + /* + * The Size of a TR descriptor is: + * 1 x tr_size : the first 16 bytes is used by the packet info block + + * tr_count x tr_size : Transfer Request Records + + * tr_count x sizeof(struct cppi5_tr_resp_t) : Transfer Response Records + */ + return tr_size * (tr_count + 1) + + sizeof(struct cppi5_tr_resp_t) * tr_count; +} + +/** + * cppi5_trdesc_init - Init TR Descriptor + * @desc: TR Descriptor + * @tr_count: number of TR records + * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128] + * @reload_idx: Absolute index to jump to on the 2nd and following passes + * through the TR packet. + * @reload_count: Number of times to jump from last entry to reload_idx. 0x1ff + * indicates infinite looping. + * + * Init TR Descriptor + */ +static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr, + u32 tr_count, u32 tr_size, u32 reload_idx, + u32 reload_count) +{ + WARN_ON(!desc_hdr); + WARN_ON(tr_count & ~CPPI5_INFO0_TRDESC_LASTIDX_MASK); + WARN_ON(reload_idx > CPPI5_INFO0_TRDESC_RLDIDX_MAX); + WARN_ON(reload_count > CPPI5_INFO0_TRDESC_RLDCNT_MAX); + + desc_hdr->pkt_info0 = CPPI5_INFO0_DESC_TYPE_VAL_TR << + CPPI5_INFO0_HDESC_TYPE_SHIFT; + desc_hdr->pkt_info0 |= (reload_count << CPPI5_INFO0_TRDESC_RLDCNT_SHIFT) & + CPPI5_INFO0_TRDESC_RLDCNT_MASK; + desc_hdr->pkt_info0 |= (reload_idx << CPPI5_INFO0_TRDESC_RLDIDX_SHIFT) & + CPPI5_INFO0_TRDESC_RLDIDX_MASK; + desc_hdr->pkt_info0 |= (tr_count - 1) & CPPI5_INFO0_TRDESC_LASTIDX_MASK; + + desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) << + CPPI5_INFO1_TRDESC_RECSIZE_SHIFT) & + CPPI5_INFO1_TRDESC_RECSIZE_MASK; +} + +/** + * cppi5_tr_init - Init TR record + * @flags: Pointer to the TR's flags + * @type: TR type + * @static_tr: TR is static + * @wait: Wait for TR completion before allow the next TR to start + * @event_size: output event generation cfg + * @cmd_id: TR identifier (application specifics) + * + * Init TR record + */ +static inline void cppi5_tr_init(cppi5_tr_flags_t *flags, + enum cppi5_tr_types type, bool static_tr, + bool wait, enum cppi5_tr_event_size event_size, + u32 cmd_id) +{ + WARN_ON(!flags); + + *flags = type; + *flags |= (event_size << CPPI5_TR_EVENT_SIZE_SHIFT) & + CPPI5_TR_EVENT_SIZE_MASK; + + *flags |= (cmd_id << CPPI5_TR_CMD_ID_SHIFT) & + CPPI5_TR_CMD_ID_MASK; + + if (static_tr && (type == CPPI5_TR_TYPE8 || type == CPPI5_TR_TYPE9)) + *flags |= CPPI5_TR_STATIC; + + if (wait) + *flags |= CPPI5_TR_WAIT; +} + +/** + * cppi5_tr_set_trigger - Configure trigger0/1 and trigger0/1_type + * @flags: Pointer to the TR's flags + * @trigger0: trigger0 selection + * @trigger0_type: type of data transfer that will be enabled by trigger0 + * @trigger1: trigger1 selection + * @trigger1_type: type of data transfer that will be enabled by trigger1 + * + * Configure the triggers for the TR + */ +static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags, + enum cppi5_tr_trigger trigger0, + enum cppi5_tr_trigger_type trigger0_type, + enum cppi5_tr_trigger trigger1, + enum cppi5_tr_trigger_type trigger1_type) +{ + WARN_ON(!flags); + + *flags |= (trigger0 << CPPI5_TR_TRIGGER0_SHIFT) & + CPPI5_TR_TRIGGER0_MASK; + *flags |= (trigger0_type << CPPI5_TR_TRIGGER0_TYPE_SHIFT) & + CPPI5_TR_TRIGGER0_TYPE_MASK; + + *flags |= (trigger1 << CPPI5_TR_TRIGGER1_SHIFT) & + CPPI5_TR_TRIGGER1_MASK; + *flags |= (trigger1_type << CPPI5_TR_TRIGGER1_TYPE_SHIFT) & + CPPI5_TR_TRIGGER1_TYPE_MASK; +} + +/** + * cppi5_tr_cflag_set - Update the Configuration specific flags + * @flags: Pointer to the TR's flags + * @csf: Configuration specific flags + * + * Set a bit in Configuration Specific Flags section of the TR flags. + */ +static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf) +{ + WARN_ON(!flags); + + *flags |= (csf << CPPI5_TR_CSF_FLAGS_SHIFT) & + CPPI5_TR_CSF_FLAGS_MASK; +} + +#endif /* __TI_CPPI5_H__ */ diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h new file mode 100644 index 0000000000..487dfe9859 --- /dev/null +++ b/include/linux/soc/ti/k3-navss-ringacc.h @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + */ + +#ifndef __SOC_TI_K3_NAVSS_RINGACC_API_H_ +#define __SOC_TI_K3_NAVSS_RINGACC_API_H_ + +#include <dm/ofnode.h> + +/** + * enum k3_nav_ring_mode - &struct k3_nav_ring_cfg mode + * + * RA ring operational modes + * + * @K3_NAV_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access + * @K3_NAV_RINGACC_RING_MODE_MESSAGE: Messaging mode. Messaging mode requires + * that all accesses to the queue must go through this IP so that all + * accesses to the memory are controlled and ordered. This IP then + * controls the entire state of the queue, and SW has no directly control, + * such as through doorbells and cannot access the storage memory directly. + * This is particularly useful when more than one SW or HW entity can be + * the producer and/or consumer at the same time + * @K3_NAV_RINGACC_RING_MODE_CREDENTIALS: Credentials mode is message mode plus + * stores credentials with each message, requiring the element size to be + * doubled to fit the credentials. Any exposed memory should be protected + * by a firewall from unwanted access + * @K3_NAV_RINGACC_RING_MODE_QM: Queue manager mode. This takes the credentials + * mode and adds packet length per element, along with additional read only + * fields for element count and accumulated queue length. The QM mode only + * operates with an 8 byte element size (any other element size is + * illegal), and like in credentials mode each operation uses 2 element + * slots to store the credentials and length fields + */ +enum k3_nav_ring_mode { + K3_NAV_RINGACC_RING_MODE_RING = 0, + K3_NAV_RINGACC_RING_MODE_MESSAGE, + K3_NAV_RINGACC_RING_MODE_CREDENTIALS, + K3_NAV_RINGACC_RING_MODE_QM, + k3_NAV_RINGACC_RING_MODE_INVALID +}; + +/** + * enum k3_nav_ring_size - &struct k3_nav_ring_cfg elm_size + * + * RA ring element's sizes in bytes. + */ +enum k3_nav_ring_size { + K3_NAV_RINGACC_RING_ELSIZE_4 = 0, + K3_NAV_RINGACC_RING_ELSIZE_8, + K3_NAV_RINGACC_RING_ELSIZE_16, + K3_NAV_RINGACC_RING_ELSIZE_32, + K3_NAV_RINGACC_RING_ELSIZE_64, + K3_NAV_RINGACC_RING_ELSIZE_128, + K3_NAV_RINGACC_RING_ELSIZE_256, + K3_NAV_RINGACC_RING_ELSIZE_INVALID +}; + +struct k3_nav_ringacc; +struct k3_nav_ring; + +/** + * enum k3_nav_ring_cfg - RA ring configuration structure + * + * @size: Ring size, number of elements + * @elm_size: Ring element size + * @mode: Ring operational mode + * @flags: Ring configuration flags. Possible values: + * @K3_NAV_RINGACC_RING_SHARED: when set allows to request the same ring + * few times. It's usable when the same ring is used as Free Host PD ring + * for different flows, for example. + * Note: Locking should be done by consumer if required + */ +struct k3_nav_ring_cfg { + u32 size; + enum k3_nav_ring_size elm_size; + enum k3_nav_ring_mode mode; +#define K3_NAV_RINGACC_RING_SHARED BIT(1) + u32 flags; +}; + +#define K3_NAV_RINGACC_RING_ID_ANY (-1) +#define K3_NAV_RINGACC_RING_USE_PROXY BIT(1) + +/** + * k3_nav_ringacc_request_ring - request ring from ringacc + * @ringacc: pointer on ringacc + * @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring + * @flags: + * @K3_NAV_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and + * used to access ring memory. Sopported only for rings in + * Message/Credentials/Queue mode. + * + * Returns pointer on the Ring - struct k3_nav_ring + * or NULL in case of failure. + */ +struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc, + int id, u32 flags); + +/** + * k3_nav_ringacc_get_dev - get pointer on RA device + * @ringacc: pointer on RA + * + * Returns device pointer + */ +struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc); + +/** + * k3_nav_ringacc_ring_reset - ring reset + * @ring: pointer on Ring + * + * Resets ring internal state ((hw)occ, (hw)idx). + * TODO_GS: ? Ring can be reused without reconfiguration + */ +void k3_nav_ringacc_ring_reset(struct k3_nav_ring *ring); +/** + * k3_nav_ringacc_ring_reset - ring reset for DMA rings + * @ring: pointer on Ring + * + * Resets ring internal state ((hw)occ, (hw)idx). Should be used for rings + * which are read by K3 UDMA, like TX or Free Host PD rings. + */ +void k3_nav_ringacc_ring_reset_dma(struct k3_nav_ring *ring, u32 occ); + +/** + * k3_nav_ringacc_ring_free - ring free + * @ring: pointer on Ring + * + * Resets ring and free all alocated resources. + */ +int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring); + +/** + * k3_nav_ringacc_get_ring_id - Get the Ring ID + * @ring: pointer on ring + * + * Returns the Ring ID + */ +u32 k3_nav_ringacc_get_ring_id(struct k3_nav_ring *ring); + +/** + * k3_nav_ringacc_ring_cfg - ring configure + * @ring: pointer on ring + * @cfg: Ring configuration parameters (see &struct k3_nav_ring_cfg) + * + * Configures ring, including ring memory allocation. + * Returns 0 on success, errno otherwise. + */ +int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring, + struct k3_nav_ring_cfg *cfg); + +/** + * k3_nav_ringacc_ring_get_size - get ring size + * @ring: pointer on ring + * + * Returns ring size in number of elements. + */ +u32 k3_nav_ringacc_ring_get_size(struct k3_nav_ring *ring); + +/** + * k3_nav_ringacc_ring_get_free - get free elements + * @ring: pointer on ring + * + * Returns number of free elements in the ring. + */ +u32 k3_nav_ringacc_ring_get_free(struct k3_nav_ring *ring); + +/** + * k3_nav_ringacc_ring_get_occ - get ring occupancy + * @ring: pointer on ring + * + * Returns total number of valid entries on the ring + */ +u32 k3_nav_ringacc_ring_get_occ(struct k3_nav_ring *ring); + +/** + * k3_nav_ringacc_ring_is_full - checks if ring is full + * @ring: pointer on ring + * + * Returns true if the ring is full + */ +u32 k3_nav_ringacc_ring_is_full(struct k3_nav_ring *ring); + +/** + * k3_nav_ringacc_ring_push - push element to the ring tail + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * Push one ring element to the ring tail. Size of the ring element is + * determined by ring configuration &struct k3_nav_ring_cfg elm_size. + * + * Returns 0 on success, errno otherwise. + */ +int k3_nav_ringacc_ring_push(struct k3_nav_ring *ring, void *elem); + +/** + * k3_nav_ringacc_ring_pop - pop element from the ring head + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * Push one ring element from the ring head. Size of the ring element is + * determined by ring configuration &struct k3_nav_ring_cfg elm_size.. + * + * Returns 0 on success, errno otherwise. + */ +int k3_nav_ringacc_ring_pop(struct k3_nav_ring *ring, void *elem); + +/** + * k3_nav_ringacc_ring_push_head - push element to the ring head + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * Push one ring element to the ring head. Size of the ring element is + * determined by ring configuration &struct k3_nav_ring_cfg elm_size. + * + * Returns 0 on success, errno otherwise. + * Not Supported by ring modes: K3_NAV_RINGACC_RING_MODE_RING + */ +int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem); + +/** + * k3_nav_ringacc_ring_pop_tail - pop element from the ring tail + * @ring: pointer on ring + * @elem: pointer on ring element buffer + * + * Push one ring element from the ring tail. Size of the ring element is + * determined by ring configuration &struct k3_nav_ring_cfg elm_size. + * + * Returns 0 on success, errno otherwise. + * Not Supported by ring modes: K3_NAV_RINGACC_RING_MODE_RING + */ +int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem); + +#endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */ diff --git a/include/linux/soc/ti/ti-udma.h b/include/linux/soc/ti/ti-udma.h new file mode 100644 index 0000000000..e9d4226c48 --- /dev/null +++ b/include/linux/soc/ti/ti-udma.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> + */ + +#ifndef __TI_UDMA_H +#define __TI_UDMA_H + +/** + * struct ti_udma_drv_packet_data - TI UDMA transfer specific data + * + * @pkt_type: Packet Type - specific for each DMA client HW + * @dest_tag: Destination tag The source pointer. + * + * TI UDMA transfer specific data passed as part of DMA transfer to + * the DMA client HW in UDMA descriptors. + */ +struct ti_udma_drv_packet_data { + u32 pkt_type; + u32 dest_tag; +}; + +#endif /* __TI_UDMA_H */ diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 90d5053636..222cf66546 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -213,13 +213,42 @@ struct ti_sci_clk_ops { }; /** + * struct ti_sci_rm_core_ops - Resource management core operations + * @get_range: Get a range of resources belonging to ti sci host. + * @get_rage_from_shost: Get a range of resources belonging to + * specified host id. + * - s_host: Host processing entity to which the + * resources are allocated + * + * NOTE: for these functions, all the parameters are consolidated and defined + * as below: + * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * - dev_id: TISCI device ID. + * - subtype: Resource assignment subtype that is being requested + * from the given device. + * - range_start: Start index of the resource range + * - range_end: Number of resources in the range + */ +struct ti_sci_rm_core_ops { + int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id, + u8 subtype, u16 *range_start, u16 *range_num); + int (*get_range_from_shost)(const struct ti_sci_handle *handle, + u32 dev_id, u8 subtype, u8 s_host, + u16 *range_start, u16 *range_num); +}; + +/** * struct ti_sci_core_ops - SoC Core Operations * @reboot_device: Reboot the SoC * Returns 0 for successful request(ideally should never return), * else returns corresponding error value. + * @query_msmc: Query the size of available msmc + * Return 0 for successful query else appropriate error value. */ struct ti_sci_core_ops { int (*reboot_device)(const struct ti_sci_handle *handle); + int (*query_msmc)(const struct ti_sci_handle *handle, + u64 *msmc_start, u64 *msmc_end); }; /** @@ -257,6 +286,230 @@ struct ti_sci_proc_ops { u32 *sts_flags); }; +#define TI_SCI_RING_MODE_RING (0) +#define TI_SCI_RING_MODE_MESSAGE (1) +#define TI_SCI_RING_MODE_CREDENTIALS (2) +#define TI_SCI_RING_MODE_QM (3) + +#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8 + +/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0) +/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1) + /* RA config.count parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2) +/* RA config.mode parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3) +/* RA config.size parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4) +/* RA config.order_id parameter is valid for RM ring configure TISCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5) + +#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \ + (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID) + +/** + * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations + * @config: configure the SoC Navigator Subsystem Ring Accelerator ring + * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring + * configuration + */ +struct ti_sci_rm_ringacc_ops { + int (*config)(const struct ti_sci_handle *handle, + u32 valid_params, u16 nav_id, u16 index, + u32 addr_lo, u32 addr_hi, u32 count, u8 mode, + u8 size, u8 order_id + ); + int (*get_config)(const struct ti_sci_handle *handle, + u32 nav_id, u32 index, u8 *mode, + u32 *addr_lo, u32 *addr_hi, u32 *count, + u8 *size, u8 *order_id); +}; + +/** + * struct ti_sci_rm_psil_ops - PSI-L thread operations + * @pair: pair PSI-L source thread to a destination thread. + * If the src_thread is mapped to UDMA tchan, the corresponding channel's + * TCHAN_THRD_ID register is updated. + * If the dst_thread is mapped to UDMA rchan, the corresponding channel's + * RCHAN_THRD_ID register is updated. + * @unpair: unpair PSI-L source thread from a destination thread. + * If the src_thread is mapped to UDMA tchan, the corresponding channel's + * TCHAN_THRD_ID register is cleared. + * If the dst_thread is mapped to UDMA rchan, the corresponding channel's + * RCHAN_THRD_ID register is cleared. + */ +struct ti_sci_rm_psil_ops { + int (*pair)(const struct ti_sci_handle *handle, u32 nav_id, + u32 src_thread, u32 dst_thread); + int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id, + u32 src_thread, u32 dst_thread); +}; + +/* UDMAP channel types */ +#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */ +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13 + +/* UDMAP channel atypes */ +#define TI_SCI_RM_UDMAP_ATYPE_PHYS 0 +#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE 1 +#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL 2 + +/* UDMAP channel scheduling priorities */ +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH 0 +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH 1 +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW 2 +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW 3 + +#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0 +#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2 + +/* UDMAP TX/RX channel valid_params common declarations */ +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8) + +/** + * Configures a Navigator Subsystem UDMAP transmit channel + * + * Configures a Navigator Subsystem UDMAP transmit channel registers. + * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req + */ +struct ti_sci_msg_rm_udmap_tx_ch_cfg { + u32 valid_params; +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) + u16 nav_id; + u16 index; + u8 tx_pause_on_err; + u8 tx_filt_einfo; + u8 tx_filt_pswords; + u8 tx_atype; + u8 tx_chan_type; + u8 tx_supr_tdpkt; + u16 tx_fetch_size; + u8 tx_credit_count; + u16 txcq_qnum; + u8 tx_priority; + u8 tx_qos; + u8 tx_orderid; + u16 fdepth; + u8 tx_sched_priority; +}; + +/** + * Configures a Navigator Subsystem UDMAP receive channel + * + * Configures a Navigator Subsystem UDMAP receive channel registers. + * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req + */ +struct ti_sci_msg_rm_udmap_rx_ch_cfg { + u32 valid_params; +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12) + u16 nav_id; + u16 index; + u16 rx_fetch_size; + u16 rxcq_qnum; + u8 rx_priority; + u8 rx_qos; + u8 rx_orderid; + u8 rx_sched_priority; + u16 flowid_start; + u16 flowid_cnt; + u8 rx_pause_on_err; + u8 rx_atype; + u8 rx_chan_type; + u8 rx_ignore_short; + u8 rx_ignore_long; +}; + +/** + * Configures a Navigator Subsystem UDMAP receive flow + * + * Configures a Navigator Subsystem UDMAP receive flow's registers. + * See @tis_ci_msg_rm_udmap_flow_cfg_req + */ +struct ti_sci_msg_rm_udmap_flow_cfg { + u32 valid_params; +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18) + u16 nav_id; + u16 flow_index; + u8 rx_einfo_present; + u8 rx_psinfo_present; + u8 rx_error_handling; + u8 rx_desc_type; + u16 rx_sop_offset; + u16 rx_dest_qnum; + u8 rx_src_tag_hi; + u8 rx_src_tag_lo; + u8 rx_dest_tag_hi; + u8 rx_dest_tag_lo; + u8 rx_src_tag_hi_sel; + u8 rx_src_tag_lo_sel; + u8 rx_dest_tag_hi_sel; + u8 rx_dest_tag_lo_sel; + u16 rx_fdq0_sz0_qnum; + u16 rx_fdq1_qnum; + u16 rx_fdq2_qnum; + u16 rx_fdq3_qnum; + u8 rx_ps_location; +}; + +/** + * struct ti_sci_rm_udmap_ops - UDMA Management operations + * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel. + * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel. + * @rx_flow_cfg: configure SoC Navigator Subsystem UDMA receive flow. + */ +struct ti_sci_rm_udmap_ops { + int (*tx_ch_cfg)(const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params); + int (*rx_ch_cfg)(const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params); + int (*rx_flow_cfg)( + const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_udmap_flow_cfg *params); +}; + /** * struct ti_sci_ops - Function support for TI SCI * @board_ops: Miscellaneous operations @@ -264,6 +517,7 @@ struct ti_sci_proc_ops { * @clk_ops: Clock specific operations * @core_ops: Core specific operations * @proc_ops: Processor specific operations + * @ring_ops: Ring Accelerator Management operations */ struct ti_sci_ops { struct ti_sci_board_ops board_ops; @@ -271,6 +525,10 @@ struct ti_sci_ops { struct ti_sci_clk_ops clk_ops; struct ti_sci_core_ops core_ops; struct ti_sci_proc_ops proc_ops; + struct ti_sci_rm_core_ops rm_core_ops; + struct ti_sci_rm_ringacc_ops rm_ring_ops; + struct ti_sci_rm_psil_ops rm_psil_ops; + struct ti_sci_rm_udmap_ops rm_udmap_ops; }; /** @@ -283,12 +541,42 @@ struct ti_sci_handle { struct ti_sci_version_info version; }; +#define TI_SCI_RESOURCE_NULL 0xffff + +/** + * struct ti_sci_resource_desc - Description of TI SCI resource instance range. + * @start: Start index of the resource. + * @num: Number of resources. + * @res_map: Bitmap to manage the allocation of these resources. + */ +struct ti_sci_resource_desc { + u16 start; + u16 num; + unsigned long *res_map; +}; + +/** + * struct ti_sci_resource - Structure representing a resource assigned + * to a device. + * @sets: Number of sets available from this resource type + * @desc: Array of resource descriptors. + */ +struct ti_sci_resource { + u16 sets; + struct ti_sci_resource_desc *desc; +}; + #if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL) const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev); const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev); const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev, const char *property); +u16 ti_sci_get_free_resource(struct ti_sci_resource *res); +void ti_sci_release_resource(struct ti_sci_resource *res, u16 id); +struct ti_sci_resource * +devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle, + struct udevice *dev, u32 dev_id, char *of_prop); #else /* CONFIG_TI_SCI_PROTOCOL */ @@ -309,6 +597,22 @@ const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev, { return ERR_PTR(-EINVAL); } + +static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res) +{ + return TI_SCI_RESOURCE_NULL; +} + +static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id) +{ +} + +static inline struct ti_sci_resource * +devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle, + struct udevice *dev, u32 dev_id, char *of_prop) +{ + return ERR_PTR(-EINVAL); +} #endif /* CONFIG_TI_SCI_PROTOCOL */ #endif /* __TISCI_PROTOCOL_H */ diff --git a/include/malloc.h b/include/malloc.h index b714fedf45..5efa6920b2 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -878,7 +878,6 @@ extern Void_t* sbrk(); #define memalign memalign_simple static inline void free(void *ptr) {} void *calloc(size_t nmemb, size_t size); -void *memalign_simple(size_t alignment, size_t bytes); void *realloc_simple(void *ptr, size_t size); void malloc_simple_info(void); #else @@ -914,6 +913,7 @@ int initf_malloc(void); /* Simple versions which can be used when space is tight */ void *malloc_simple(size_t size); +void *memalign_simple(size_t alignment, size_t bytes); #pragma GCC visibility push(hidden) # if __STD_C diff --git a/include/net.h b/include/net.h index dd52ed3f47..44b32385c4 100644 --- a/include/net.h +++ b/include/net.h @@ -92,12 +92,14 @@ enum eth_state_t { * @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env * @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_... * @max_speed: Maximum speed of Ethernet connection supported by MAC + * @priv_pdata: device specific platdata */ struct eth_pdata { phys_addr_t iobase; unsigned char enetaddr[ARP_HLEN]; int phy_interface; int max_speed; + void *priv_pdata; }; enum eth_recv_flags { diff --git a/include/pci.h b/include/pci.h index 5fb212cab1..9668503f09 100644 --- a/include/pci.h +++ b/include/pci.h @@ -545,7 +545,11 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#define MAX_PCI_REGIONS 7 +#ifdef CONFIG_NR_DRAM_BANKS +#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7) +#else +#define MAX_PCI_REGIONS 7 +#endif #define INDIRECT_TYPE_NO_PCIE_LINK 1 diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h new file mode 100644 index 0000000000..0e6721d852 --- /dev/null +++ b/include/power/stpmic1.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef __PMIC_STPMIC1_H_ +#define __PMIC_STPMIC1_H_ + +#define STPMIC1_MAIN_CR 0x10 +#define STPMIC1_BUCKS_MRST_CR 0x18 +#define STPMIC1_LDOS_MRST_CR 0x1a +#define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck)) +#define STPMIC1_REFDDR_MAIN_CR 0x24 +#define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo)) +#define STPMIC1_BST_SW_CR 0x40 +#define STPMIC1_NVM_SR 0xb8 +#define STPMIC1_NVM_CR 0xb9 + +/* Main PMIC Control Register (MAIN_CR) */ +#define STPMIC1_SWOFF BIT(0) +#define STPMIC1_RREQ_EN BIT(1) + +/* BUCKS_MRST_CR */ +#define STPMIC1_MRST_BUCK(buck) BIT(buck) +#define STPMIC1_MRST_BUCK_ALL GENMASK(3, 0) + +/* LDOS_MRST_CR */ +#define STPMIC1_MRST_LDO(ldo) BIT(ldo) +#define STPMIC1_MRST_LDO_ALL GENMASK(6, 0) + +/* BUCKx_MAIN_CR (x=1...4) */ +#define STPMIC1_BUCK_ENA BIT(0) +#define STPMIC1_BUCK_PREG_MODE BIT(1) +#define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2) +#define STPMIC1_BUCK_VOUT_SHIFT 2 +#define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT) + +#define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24) +#define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30) + +#define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39) + +/* REFDDR_MAIN_CR */ +#define STPMIC1_VREF_ENA BIT(0) + +/* LDOX_MAIN_CR */ +#define STPMIC1_LDO_ENA BIT(0) +#define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2) +#define STPMIC1_LDO12356_VOUT_SHIFT 2 +#define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT) + +#define STPMIC1_LDO3_MODE BIT(7) +#define STPMIC1_LDO3_DDR_SEL 31 +#define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9) + +#define STPMIC1_LDO4_UV 3300000 + +/* BST_SW_CR */ +#define STPMIC1_BST_ON BIT(0) +#define STPMIC1_VBUSOTG_ON BIT(1) +#define STPMIC1_SWOUT_ON BIT(2) +#define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON) + +/* NVM_SR */ +#define STPMIC1_NVM_BUSY BIT(0) + +/* NVM_CR */ +#define STPMIC1_NVM_CMD_PROGRAM 1 +#define STPMIC1_NVM_CMD_READ 2 + +/* Timeout */ +#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1 +#define STPMIC1_DEFAULT_STOP_DELAY_MS 5 +#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10 + +enum { + STPMIC1_BUCK1, + STPMIC1_BUCK2, + STPMIC1_BUCK3, + STPMIC1_BUCK4, + STPMIC1_MAX_BUCK, +}; + +enum { + STPMIC1_PREG_MODE_HP, + STPMIC1_PREG_MODE_LP, +}; + +enum { + STPMIC1_LDO1, + STPMIC1_LDO2, + STPMIC1_LDO3, + STPMIC1_LDO4, + STPMIC1_LDO5, + STPMIC1_LDO6, + STPMIC1_MAX_LDO, +}; + +enum { + STPMIC1_LDO_MODE_NORMAL, + STPMIC1_LDO_MODE_BYPASS, + STPMIC1_LDO_MODE_SINK_SOURCE, +}; + +enum { + STPMIC1_PWR_SW1, + STPMIC1_PWR_SW2, + STPMIC1_MAX_PWR_SW, +}; + +int stpmic1_shadow_read_byte(u8 addr, u8 *buf); +int stpmic1_shadow_write_byte(u8 addr, u8 *buf); +int stpmic1_nvm_read_byte(u8 addr, u8 *buf); +int stpmic1_nvm_write_byte(u8 addr, u8 *buf); +int stpmic1_nvm_read_all(u8 *buf, int buf_len); +int stpmic1_nvm_write_all(u8 *buf, int buf_len); +#endif diff --git a/include/power/stpmu1.h b/include/power/stpmu1.h deleted file mode 100644 index 5906fbf832..0000000000 --- a/include/power/stpmu1.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#ifndef __PMIC_STPMU1_H_ -#define __PMIC_STPMU1_H_ - -#define STPMU1_MASK_RESET_BUCK 0x18 -#define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck)) -#define STPMU1_VREF_CTRL_REG 0x24 -#define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo)) -#define STPMU1_USB_CTRL_REG 0x40 -#define STPMU1_NVM_USER_STATUS_REG 0xb8 -#define STPMU1_NVM_USER_CONTROL_REG 0xb9 - -#define STPMU1_MASK_RESET_BUCK3 BIT(2) - -#define STPMU1_BUCK_EN BIT(0) -#define STPMU1_BUCK_MODE BIT(1) -#define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2) -#define STPMU1_BUCK_OUTPUT_SHIFT 2 -#define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT) -#define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT) -#define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT) - -#define STPMU1_VREF_EN BIT(0) - -#define STPMU1_LDO_EN BIT(0) -#define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2) -#define STPMU1_LDO12356_OUTPUT_SHIFT 2 -#define STPMU1_LDO3_MODE BIT(7) -#define STPMU1_LDO3_DDR_SEL 31 -#define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT) -#define STPMU1_LDO4_UV 3300000 - -#define STPMU1_USB_BOOST_EN BIT(0) -#define STPMU1_USB_PWR_SW_EN GENMASK(2, 1) - -#define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0) -#define STPMU1_NVM_USER_CONTROL_READ BIT(1) - -#define STPMU1_NVM_USER_STATUS_BUSY BIT(0) -#define STPMU1_NVM_USER_STATUS_ERROR BIT(1) - -#define STPMU1_DEFAULT_START_UP_DELAY_MS 1 -#define STPMU1_DEFAULT_STOP_DELAY_MS 5 -#define STPMU1_USB_BOOST_START_UP_DELAY_MS 10 - -enum { - STPMU1_BUCK1, - STPMU1_BUCK2, - STPMU1_BUCK3, - STPMU1_BUCK4, - STPMU1_MAX_BUCK, -}; - -enum { - STPMU1_BUCK_MODE_HP, - STPMU1_BUCK_MODE_LP, -}; - -enum { - STPMU1_LDO1, - STPMU1_LDO2, - STPMU1_LDO3, - STPMU1_LDO4, - STPMU1_LDO5, - STPMU1_LDO6, - STPMU1_MAX_LDO, -}; - -enum { - STPMU1_LDO_MODE_NORMAL, - STPMU1_LDO_MODE_BYPASS, - STPMU1_LDO_MODE_SINK_SOURCE, -}; - -enum { - STPMU1_PWR_SW1, - STPMU1_PWR_SW2, - STPMU1_MAX_PWR_SW, -}; - -#endif diff --git a/include/reset.h b/include/reset.h index 65aa7a4ce5..a1a9ad5603 100644 --- a/include/reset.h +++ b/include/reset.h @@ -43,6 +43,8 @@ struct udevice; * @data: An optional data field for scenarios where a single integer ID is not * sufficient. If used, it can be populated through an .of_xlate op and * processed during the various reset ops. + * @polarity: An optional polarity field for drivers that support + * different reset polarities. * * Should additional information to identify and configure any reset signal * for any provider be required in the future, the struct could be expanded to @@ -59,6 +61,7 @@ struct reset_ctl { */ unsigned long id; unsigned long data; + unsigned long polarity; }; /** diff --git a/include/spi.h b/include/spi.h index 92427e5f32..378594163b 100644 --- a/include/spi.h +++ b/include/spi.h @@ -496,14 +496,15 @@ int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, * device and slave device. * * If no such slave exists, and drv_name is not NULL, then a new slave device - * is automatically bound on this chip select. + * is automatically bound on this chip select with requested speed and mode. * - * Ths new slave device is probed ready for use with the given speed and mode. + * Ths new slave device is probed ready for use with the speed and mode + * from platdata when available or the requested values. * * @busnum: SPI bus number * @cs: Chip select to look for - * @speed: SPI speed to use for this slave - * @mode: SPI mode to use for this slave + * @speed: SPI speed to use for this slave when not available in platdata + * @mode: SPI mode to use for this slave when not available in platdata * @drv_name: Name of driver to attach to this chip select * @dev_name: Name of the new device thus created * @busp: Returns bus device diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 4068de045d..a6c12212a9 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -9,6 +9,7 @@ #define __DWC2_USB_GADGET #define PHY0_SLEEP (1 << 5) +#define DWC2_MAX_HW_ENDPOINTS 16 struct dwc2_plat_otg_data { void *priv; @@ -22,8 +23,14 @@ struct dwc2_plat_otg_data { unsigned int rx_fifo_sz; unsigned int np_tx_fifo_sz; unsigned int tx_fifo_sz; + unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS]; + unsigned char tx_fifo_sz_nb; + bool force_b_session_valid; + bool activate_stm_id_vb_detection; }; int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata); +int dwc2_udc_B_session_valid(struct udevice *dev); + #endif /* __DWC2_USB_GADGET */ diff --git a/include/video.h b/include/video.h index 1d57b48b17..485071d072 100644 --- a/include/video.h +++ b/include/video.h @@ -70,6 +70,7 @@ enum video_log2_bpp { * the LCD is updated * @cmap: Colour map for 8-bit-per-pixel displays * @fg_col_idx: Foreground color code (bit 3 = bold, bit 0-2 = color) + * @bg_col_idx: Background color code (bit 3 = bold, bit 0-2 = color) */ struct video_priv { /* Things set up by the driver: */ @@ -92,6 +93,7 @@ struct video_priv { bool flush_dcache; ushort *cmap; u8 fg_col_idx; + u8 bg_col_idx; }; /* Placeholder - there are no video operations at present */ |