diff options
Diffstat (limited to 'include')
32 files changed, 1110 insertions, 17 deletions
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0834ff5021..7721907d8f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -240,7 +240,6 @@ * add mass storage support and for gadget we add both RNDIS ethernet * and DFU. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/baltos.h b/include/configs/baltos.h index ccbdc0a335..98ec0d626e 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -251,7 +251,6 @@ * add mass storage support and for gadget we add both RNDIS ethernet * and DFU. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_HOST #define CONFIG_AM335X_USB1 diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index fb9c2a6d04..3d4d08aa70 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -387,7 +387,6 @@ DEFAULT_LINUX_BOOT_ENV \ * add mass storage support and for gadget we add both RNDIS ethernet * and DFU. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 5834e1e2a2..2de6f21861 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -30,6 +30,13 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif /* CONFIG_NAND */ + /* * bcm963158 */ diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h index 6126a8879e..355f3ef5be 100644 --- a/include/configs/broadcom_bcm968380gerg.h +++ b/include/configs/broadcom_bcm968380gerg.h @@ -7,3 +7,10 @@ #include <configs/bmips_bcm6838.h> #define CONFIG_ENV_SIZE (8 * 1024) + +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif /* CONFIG_NAND */ diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h index 1c0945e140..52b4f55f7c 100644 --- a/include/configs/broadcom_bcm968580xref.h +++ b/include/configs/broadcom_bcm968580xref.h @@ -29,6 +29,13 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif /* CONFIG_NAND */ + /* * 968580xref */ diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index ae9b75bb87..84c801d10a 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -182,9 +182,6 @@ NANDTGTS \ #define CONFIG_NAND_OMAP_GPMC_WSCFG 1 #endif /* CONFIG_NAND */ -/* USB configuration */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT - #if defined(CONFIG_SPI) /* SPI Flash */ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 601b30dffd..7309e7d483 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -68,9 +68,6 @@ BUR_COMMON_ENV \ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -/* USB configuration */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT - /* Environment */ #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 4372280d2b..db990fcb2b 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -148,7 +148,6 @@ /* USB configuration */ #define CONFIG_ARCH_MISC_INIT -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 749a67d4b0..e85f684e32 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -72,6 +72,7 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT #endif /* Ethernet */ diff --git a/include/configs/libretech-ac.h b/include/configs/libretech-ac.h new file mode 100644 index 0000000000..419dc61587 --- /dev/null +++ b/include/configs/libretech-ac.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for LibreTech AC + * + * Copyright (C) 2017 Baylibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OFFSET (-0x10000) + +#define BOOT_TARGET_DEVICES(func) \ + func(ROMUSB, romusb, na) \ + func(MMC, mmc, 0) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <configs/meson64.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 48f1f7bacc..a535d0c2f2 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -157,7 +157,6 @@ * board schematic and physical port wired to each. Then for host we * add mass storage support. */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h new file mode 100644 index 0000000000..afcd22b664 --- /dev/null +++ b/include/configs/sama5d2_icp.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D2 ICP Board. + * + * Copyright (C) 2018 Microchip Corporation + * Eugen Hristev <eugen.hristev@microchip.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_MISC_INIT_R + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* SPI flash */ +#define CONFIG_SF_DEFAULT_SPEED 66000000 + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_SD_BOOT +/* u-boot env in sd/mmc card */ +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +#endif + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index f44a4280f4..1170f24748 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -150,8 +150,6 @@ /* * USB configuration */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT - #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL #define CONFIG_AM335X_USB1 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 09c9b7ca9e..f9e2cdc1b3 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -338,6 +338,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "scriptaddr=0x02100000\0" \ "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ + "socfpga_legacy_reset_compat=1\0" \ BOOTENV #endif diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100644 index 0000000000..8db01ffbeb --- /dev/null +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai <qiufang.dai@amlogic.com> + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB 0 +#define CLKID_AO_IR_IN 1 +#define CLKID_AO_I2C_M0 2 +#define CLKID_AO_I2C_S0 3 +#define CLKID_AO_UART 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_OUT 7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_MAILBOX 9 +#define CLKID_AO_M3 10 +#define CLKID_AO_AHB_SRAM 11 +#define CLKID_AO_RTI 12 +#define CLKID_AO_M4_FCLK 13 +#define CLKID_AO_M4_HCLK 14 +#define CLKID_AO_CLK81 15 +#define CLKID_AO_SAR_ADC_CLK 18 +#define CLKID_AO_32K 23 +#define CLKID_AO_CEC 27 +#define CLKID_AO_CTS_RTC_OSCIN 28 + +#endif diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 0000000000..83b657038d --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK81 10 +#define CLKID_MPLL0 11 +#define CLKID_MPLL1 12 +#define CLKID_MPLL2 13 +#define CLKID_MPLL3 14 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST 18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL301 21 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART0 28 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE 30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A 33 +#define CLKID_SD_EMMC_B 34 +#define CLKID_SD_EMMC_C 35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO 37 +#define CLKID_ETH 38 +#define CLKID_DEMUX 39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART1 42 +#define CLKID_G2D 43 +#define CLKID_RESET 44 +#define CLKID_PCIE_COMB 45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT656 54 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART2 57 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_A_CLK0 60 +#define CLKID_SD_EMMC_B_CLK0 61 +#define CLKID_SD_EMMC_C_CLK0 62 +#define CLKID_HIFI_PLL 74 +#define CLKID_VCLK2_VENCI0 80 +#define CLKID_VCLK2_VENCI1 81 +#define CLKID_VCLK2_VENCP0 82 +#define CLKID_VCLK2_VENCP1 83 +#define CLKID_VCLK2_VENCT0 84 +#define CLKID_VCLK2_VENCT1 85 +#define CLKID_VCLK2_OTHER 86 +#define CLKID_VCLK2_ENCI 87 +#define CLKID_VCLK2_ENCP 88 +#define CLKID_DAC_CLK 89 +#define CLKID_AOCLK 90 +#define CLKID_IEC958 91 +#define CLKID_ENC480P 92 +#define CLKID_RNG1 93 +#define CLKID_VCLK2_ENCT 94 +#define CLKID_VCLK2_ENCL 95 +#define CLKID_VCLK2_VENCLMMC 96 +#define CLKID_VCLK2_VENCL 97 +#define CLKID_VCLK2_OTHER1 98 +#define CLKID_FCLK_DIV2P5 99 +#define CLKID_DMA 105 +#define CLKID_EFUSE 106 +#define CLKID_ROM_BOOT 107 +#define CLKID_RESET_SEC 108 +#define CLKID_SEC_AHB_APB3 109 +#define CLKID_VPU_0_SEL 110 +#define CLKID_VPU_0 112 +#define CLKID_VPU_1_SEL 113 +#define CLKID_VPU_1 115 +#define CLKID_VPU 116 +#define CLKID_VAPB_0_SEL 117 +#define CLKID_VAPB_0 119 +#define CLKID_VAPB_1_SEL 120 +#define CLKID_VAPB_1 122 +#define CLKID_VAPB_SEL 123 +#define CLKID_VAPB 124 +#define CLKID_HDMI_PLL 128 +#define CLKID_VID_PLL 129 +#define CLKID_VCLK 138 +#define CLKID_VCLK2 139 +#define CLKID_VCLK_DIV1 148 +#define CLKID_VCLK_DIV2 149 +#define CLKID_VCLK_DIV4 150 +#define CLKID_VCLK_DIV6 151 +#define CLKID_VCLK_DIV12 152 +#define CLKID_VCLK2_DIV1 153 +#define CLKID_VCLK2_DIV2 154 +#define CLKID_VCLK2_DIV4 155 +#define CLKID_VCLK2_DIV6 156 +#define CLKID_VCLK2_DIV12 157 +#define CLKID_CTS_ENCI 162 +#define CLKID_CTS_ENCP 163 +#define CLKID_CTS_VDAC 164 +#define CLKID_HDMI_TX 165 +#define CLKID_HDMI 168 +#define CLKID_MALI_0_SEL 169 +#define CLKID_MALI_0 171 +#define CLKID_MALI_1_SEL 172 +#define CLKID_MALI_1 174 +#define CLKID_MALI 175 +#define CLKID_MPLL_5OM 177 + +#endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h new file mode 100644 index 0000000000..745b87f3a0 --- /dev/null +++ b/include/dt-bindings/clock/mt8516-clk.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 BayLibre, SAS + * Copyright (c) 2018 MediaTek Inc. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8516_H +#define _DT_BINDINGS_CLK_MT8516_H + + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_APLL1 4 +#define CLK_APMIXED_APLL2 5 +#define CLK_APMIXED_NR_CLK 6 + +/* TOPCKGEN */ + +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_I2S_INFRA_BCK 1 +#define CLK_TOP_MEMPLL 2 +#define CLK_TOP_DMPLL 3 +#define CLK_TOP_MAINPLL_D2 4 +#define CLK_TOP_MAINPLL_D4 5 +#define CLK_TOP_MAINPLL_D8 6 +#define CLK_TOP_MAINPLL_D16 7 +#define CLK_TOP_MAINPLL_D11 8 +#define CLK_TOP_MAINPLL_D22 9 +#define CLK_TOP_MAINPLL_D3 10 +#define CLK_TOP_MAINPLL_D6 11 +#define CLK_TOP_MAINPLL_D12 12 +#define CLK_TOP_MAINPLL_D5 13 +#define CLK_TOP_MAINPLL_D10 14 +#define CLK_TOP_MAINPLL_D20 15 +#define CLK_TOP_MAINPLL_D40 16 +#define CLK_TOP_MAINPLL_D7 17 +#define CLK_TOP_MAINPLL_D14 18 +#define CLK_TOP_UNIVPLL_D2 19 +#define CLK_TOP_UNIVPLL_D4 20 +#define CLK_TOP_UNIVPLL_D8 21 +#define CLK_TOP_UNIVPLL_D16 22 +#define CLK_TOP_UNIVPLL_D3 23 +#define CLK_TOP_UNIVPLL_D6 24 +#define CLK_TOP_UNIVPLL_D12 25 +#define CLK_TOP_UNIVPLL_D24 26 +#define CLK_TOP_UNIVPLL_D5 27 +#define CLK_TOP_UNIVPLL_D20 28 +#define CLK_TOP_MMPLL380M 29 +#define CLK_TOP_MMPLL_D2 30 +#define CLK_TOP_MMPLL_200M 31 +#define CLK_TOP_USB_PHY48M 32 +#define CLK_TOP_APLL1 33 +#define CLK_TOP_APLL1_D2 34 +#define CLK_TOP_APLL1_D4 35 +#define CLK_TOP_APLL1_D8 36 +#define CLK_TOP_APLL2 37 +#define CLK_TOP_APLL2_D2 38 +#define CLK_TOP_APLL2_D4 39 +#define CLK_TOP_APLL2_D8 40 +#define CLK_TOP_CLK26M 41 +#define CLK_TOP_CLK26M_D2 42 +#define CLK_TOP_AHB_INFRA_D2 43 +#define CLK_TOP_NFI1X 44 +#define CLK_TOP_ETH_D2 45 +#define CLK_TOP_UART0_SEL 46 +#define CLK_TOP_GFMUX_EMI1X_SEL 47 +#define CLK_TOP_EMI_DDRPHY_SEL 48 +#define CLK_TOP_AHB_INFRA_SEL 49 +#define CLK_TOP_CSW_MUX_MFG_SEL 50 +#define CLK_TOP_MSDC0_SEL 51 +#define CLK_TOP_PWM_MM_SEL 52 +#define CLK_TOP_UART1_SEL 53 +#define CLK_TOP_MSDC1_SEL 54 +#define CLK_TOP_SPM_52M_SEL 55 +#define CLK_TOP_PMICSPI_SEL 56 +#define CLK_TOP_QAXI_AUD26M_SEL 57 +#define CLK_TOP_AUD_INTBUS_SEL 58 +#define CLK_TOP_NFI2X_PAD_SEL 59 +#define CLK_TOP_NFI1X_PAD_SEL 60 +#define CLK_TOP_MFG_MM_SEL 61 +#define CLK_TOP_DDRPHYCFG_SEL 62 +#define CLK_TOP_USB_78M_SEL 63 +#define CLK_TOP_SPINOR_SEL 64 +#define CLK_TOP_MSDC2_SEL 65 +#define CLK_TOP_ETH_SEL 66 +#define CLK_TOP_AXI_MFG_IN_SEL 67 +#define CLK_TOP_SLOW_MFG_SEL 68 +#define CLK_TOP_AUD1_SEL 69 +#define CLK_TOP_AUD2_SEL 70 +#define CLK_TOP_AUD_ENGEN1_SEL 71 +#define CLK_TOP_AUD_ENGEN2_SEL 72 +#define CLK_TOP_I2C_SEL 73 +#define CLK_TOP_AUD_I2S0_M_SEL 74 +#define CLK_TOP_AUD_I2S1_M_SEL 75 +#define CLK_TOP_AUD_I2S2_M_SEL 76 +#define CLK_TOP_AUD_I2S3_M_SEL 77 +#define CLK_TOP_AUD_I2S4_M_SEL 78 +#define CLK_TOP_AUD_I2S5_M_SEL 79 +#define CLK_TOP_AUD_SPDIF_B_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_SPI_SEL 82 +#define CLK_TOP_AUD_SPDIFIN_SEL 83 +#define CLK_TOP_UART2_SEL 84 +#define CLK_TOP_BSI_SEL 85 +#define CLK_TOP_DBG_ATCLK_SEL 86 +#define CLK_TOP_CSW_NFIECC_SEL 87 +#define CLK_TOP_NFIECC_SEL 88 +#define CLK_TOP_APLL12_CK_DIV0 89 +#define CLK_TOP_APLL12_CK_DIV1 90 +#define CLK_TOP_APLL12_CK_DIV2 91 +#define CLK_TOP_APLL12_CK_DIV3 92 +#define CLK_TOP_APLL12_CK_DIV4 93 +#define CLK_TOP_APLL12_CK_DIV4B 94 +#define CLK_TOP_APLL12_CK_DIV5 95 +#define CLK_TOP_APLL12_CK_DIV5B 96 +#define CLK_TOP_APLL12_CK_DIV6 97 +#define CLK_TOP_NR_CLK 98 + +/* TOPCKGEN Gates */ +#define CLK_TOP_PWM_MM 0 +#define CLK_TOP_MFG_MM 1 +#define CLK_TOP_SPM_52M 2 +#define CLK_TOP_THEM 3 +#define CLK_TOP_APDMA 4 +#define CLK_TOP_I2C0 5 +#define CLK_TOP_I2C1 6 +#define CLK_TOP_AUXADC1 7 +#define CLK_TOP_NFI 8 +#define CLK_TOP_NFIECC 9 +#define CLK_TOP_DEBUGSYS 10 +#define CLK_TOP_PWM 11 +#define CLK_TOP_UART0 12 +#define CLK_TOP_UART1 13 +#define CLK_TOP_BTIF 14 +#define CLK_TOP_USB 15 +#define CLK_TOP_FLASHIF_26M 16 +#define CLK_TOP_AUXADC2 17 +#define CLK_TOP_I2C2 18 +#define CLK_TOP_MSDC0 19 +#define CLK_TOP_MSDC1 20 +#define CLK_TOP_NFI2X 21 +#define CLK_TOP_PMICWRAP_AP 22 +#define CLK_TOP_SEJ 23 +#define CLK_TOP_MEMSLP_DLYER 24 +#define CLK_TOP_SPI 25 +#define CLK_TOP_APXGPT 26 +#define CLK_TOP_AUDIO 27 +#define CLK_TOP_PMICWRAP_MD 28 +#define CLK_TOP_PMICWRAP_CONN 29 +#define CLK_TOP_PMICWRAP_26M 30 +#define CLK_TOP_AUX_ADC 31 +#define CLK_TOP_AUX_TP 32 +#define CLK_TOP_MSDC2 33 +#define CLK_TOP_RBIST 34 +#define CLK_TOP_NFI_BUS 35 +#define CLK_TOP_GCE 36 +#define CLK_TOP_TRNG 37 +#define CLK_TOP_SEJ_13M 38 +#define CLK_TOP_AES 39 +#define CLK_TOP_PWM_B 40 +#define CLK_TOP_PWM1_FB 41 +#define CLK_TOP_PWM2_FB 42 +#define CLK_TOP_PWM3_FB 43 +#define CLK_TOP_PWM4_FB 44 +#define CLK_TOP_PWM5_FB 45 +#define CLK_TOP_USB_1P 46 +#define CLK_TOP_FLASHIF_FREERUN 47 +#define CLK_TOP_66M_ETH 48 +#define CLK_TOP_133M_ETH 49 +#define CLK_TOP_FETH_25M 50 +#define CLK_TOP_FETH_50M 51 +#define CLK_TOP_FLASHIF_AXI 52 +#define CLK_TOP_USBIF 53 +#define CLK_TOP_UART2 54 +#define CLK_TOP_BSI 55 +#define CLK_TOP_MSDC0_INFRA 56 +#define CLK_TOP_MSDC1_INFRA 57 +#define CLK_TOP_MSDC2_INFRA 58 +#define CLK_TOP_USB_78M 59 +#define CLK_TOP_RG_SPINOR 60 +#define CLK_TOP_RG_MSDC2 61 +#define CLK_TOP_RG_ETH 62 +#define CLK_TOP_RG_AXI_MFG 63 +#define CLK_TOP_RG_SLOW_MFG 64 +#define CLK_TOP_RG_AUD1 65 +#define CLK_TOP_RG_AUD2 66 +#define CLK_TOP_RG_AUD_ENGEN1 67 +#define CLK_TOP_RG_AUD_ENGEN2 68 +#define CLK_TOP_RG_I2C 69 +#define CLK_TOP_RG_PWM_INFRA 70 +#define CLK_TOP_RG_AUD_SPDIF_IN 71 +#define CLK_TOP_RG_UART2 72 +#define CLK_TOP_RG_BSI 73 +#define CLK_TOP_RG_DBG_ATCLK 74 +#define CLK_TOP_RG_NFIECC 75 +#define CLK_TOP_RG_APLL1_D2_EN 76 +#define CLK_TOP_RG_APLL1_D4_EN 77 +#define CLK_TOP_RG_APLL1_D8_EN 78 +#define CLK_TOP_RG_APLL2_D2_EN 79 +#define CLK_TOP_RG_APLL2_D4_EN 80 +#define CLK_TOP_RG_APLL2_D8_EN 81 +#define CLK_TOP_APLL12_DIV0 82 +#define CLK_TOP_APLL12_DIV1 83 +#define CLK_TOP_APLL12_DIV2 84 +#define CLK_TOP_APLL12_DIV3 85 +#define CLK_TOP_APLL12_DIV4 86 +#define CLK_TOP_APLL12_DIV4B 87 +#define CLK_TOP_APLL12_DIV5 88 +#define CLK_TOP_APLL12_DIV5B 89 +#define CLK_TOP_APLL12_DIV6 90 + +/* INFRACFG */ + +#define CLK_IFR_MUX1_SEL 0 +#define CLK_IFR_ETH_25M_SEL 1 +#define CLK_IFR_I2C0_SEL 2 +#define CLK_IFR_I2C1_SEL 3 +#define CLK_IFR_I2C2_SEL 4 +#define CLK_IFR_NR_CLK 5 + +/* AUDIOTOP */ + +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_HDMI 7 +#define CLK_AUD_SPDF 8 +#define CLK_AUD_ADC 9 +#define CLK_AUD_DAC 10 +#define CLK_AUD_DAC_PREDIS 11 +#define CLK_AUD_TML 12 +#define CLK_AUD_NR_CLK 13 + +/* MFGCFG */ + +#define CLK_MFG_BAXI 0 +#define CLK_MFG_BMEM 1 +#define CLK_MFG_BG3D 2 +#define CLK_MFG_B26M 3 +#define CLK_MFG_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT8516_H */ diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h new file mode 100644 index 0000000000..f7bd69350d --- /dev/null +++ b/include/dt-bindings/gpio/meson-g12a-gpio.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H +#define _DT_BINDINGS_MESON_G12A_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOE_0 12 +#define GPIOE_1 13 +#define GPIOE_2 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define GPIOH_4 20 +#define GPIOH_5 21 +#define GPIOH_6 22 +#define GPIOH_7 23 +#define GPIOH_8 24 +#define BOOT_0 25 +#define BOOT_1 26 +#define BOOT_2 27 +#define BOOT_3 28 +#define BOOT_4 29 +#define BOOT_5 30 +#define BOOT_6 31 +#define BOOT_7 32 +#define BOOT_8 33 +#define BOOT_9 34 +#define BOOT_10 35 +#define BOOT_11 36 +#define BOOT_12 37 +#define BOOT_13 38 +#define BOOT_14 39 +#define BOOT_15 40 +#define GPIOC_0 41 +#define GPIOC_1 42 +#define GPIOC_2 43 +#define GPIOC_3 44 +#define GPIOC_4 45 +#define GPIOC_5 46 +#define GPIOC_6 47 +#define GPIOC_7 48 +#define GPIOA_0 49 +#define GPIOA_1 50 +#define GPIOA_2 51 +#define GPIOA_3 52 +#define GPIOA_4 53 +#define GPIOA_5 54 +#define GPIOA_6 55 +#define GPIOA_7 56 +#define GPIOA_8 57 +#define GPIOA_9 58 +#define GPIOA_10 59 +#define GPIOA_11 60 +#define GPIOA_12 61 +#define GPIOA_13 62 +#define GPIOA_14 63 +#define GPIOA_15 64 +#define GPIOX_0 65 +#define GPIOX_1 66 +#define GPIOX_2 67 +#define GPIOX_3 68 +#define GPIOX_4 69 +#define GPIOX_5 70 +#define GPIOX_6 71 +#define GPIOX_7 72 +#define GPIOX_8 73 +#define GPIOX_9 74 +#define GPIOX_10 75 +#define GPIOX_11 76 +#define GPIOX_12 77 +#define GPIOX_13 78 +#define GPIOX_14 79 +#define GPIOX_15 80 +#define GPIOX_16 81 +#define GPIOX_17 82 +#define GPIOX_18 83 +#define GPIOX_19 84 + +#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h new file mode 100644 index 0000000000..8063e8314e --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +/* 1 */ +#define RESET_DOS 2 +/* 3-4 */ +#define RESET_VIU 5 +#define RESET_AFIFO 6 +#define RESET_VID_PLL_DIV 7 +/* 8-9 */ +#define RESET_VENC 10 +#define RESET_ASSIST 11 +#define RESET_PCIE_CTRL_A 12 +#define RESET_VCBUS 13 +#define RESET_PCIE_PHY 14 +#define RESET_PCIE_APB 15 +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +/* 18 */ +#define RESET_HDMITX_CAPB3 19 +#define RESET_DVALIN_CAPB3 20 +#define RESET_DOS_CAPB3 21 +/* 22 */ +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +/* 27-31 */ +/* RESET1 */ +/* 32 */ +#define RESET_DEMUX 33 +#define RESET_USB 34 +#define RESET_DDR 35 +/* 36 */ +#define RESET_BT656 37 +#define RESET_AHB_SRAM 38 +/* 39 */ +#define RESET_PARSER 40 +/* 41 */ +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +#define RESET_SD_EMMC_A 44 +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +/* 47-60 */ +#define RESET_AUDIO_CODEC 61 +/* 62-63 */ +/* RESET2 */ +/* 64 */ +#define RESET_AUDIO 65 +#define RESET_HDMITX_PHY 66 +/* 67 */ +#define RESET_MIPI_DSI_HOST 68 +#define RESET_ALOCKER 69 +#define RESET_GE2D 70 +#define RESET_PARSER_REG 71 +#define RESET_PARSER_FETCH 72 +#define RESET_CTL 73 +#define RESET_PARSER_TOP 74 +/* 75-77 */ +#define RESET_DVALIN 78 +#define RESET_HDMITX 79 +/* 80-95 */ +/* RESET3 */ +/* 96-95 */ +#define RESET_DEMUX_TOP 105 +#define RESET_DEMUX_DES_PL 106 +#define RESET_DEMUX_S2P_0 107 +#define RESET_DEMUX_S2P_1 108 +#define RESET_DEMUX_0 109 +#define RESET_DEMUX_1 110 +#define RESET_DEMUX_2 111 +/* 112-127 */ +/* RESET4 */ +/* 128-129 */ +#define RESET_MIPI_DSI_PHY 130 +/* 131-132 */ +#define RESET_RDMA 133 +#define RESET_VENCI 134 +#define RESET_VENCP 135 +/* 136 */ +#define RESET_VDAC 137 +/* 138-139 */ +#define RESET_VDI6 140 +#define RESET_VENCL 141 +#define RESET_I2C_M1 142 +#define RESET_I2C_M2 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_GEN 192 +#define RESET_SPICC0 193 +#define RESET_SC 194 +#define RESET_SANA_3 195 +#define RESET_I2C_M0 196 +#define RESET_TS_PLL 197 +#define RESET_SPICC1 198 +#define RESET_STREAM 199 +#define RESET_TS_CPU 200 +#define RESET_UART0 201 +#define RESET_UART1_2 202 +#define RESET_ASYNC0 203 +#define RESET_ASYNC1 204 +#define RESET_SPIFC0 205 +#define RESET_I2C_M3 206 +/* 207-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +#define RESET_TS_GPU 228 +#define RESET_DEVICE_MMC_ARB 229 +#define RESET_DVALIN_DMC_PIPL 230 +#define RESET_VID_LOCK 231 +#define RESET_NIC_DMC_PIPL 232 +#define RESET_DMC_VPU_PIPL 233 +#define RESET_GE2D_DMC_PIPL 234 +#define RESET_HCODEC_DMC_PIPL 235 +#define RESET_WAVE420_DMC_PIPL 236 +#define RESET_HEVCF_DMC_PIPL 237 +/* 238-255 */ + +#endif diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h new file mode 100644 index 0000000000..bd2e233713 --- /dev/null +++ b/include/dt-bindings/reset/g12a-aoclkc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK + +#define RESET_AO_IR_IN 0 +#define RESET_AO_UART 1 +#define RESET_AO_I2C_M 2 +#define RESET_AO_I2C_S 3 +#define RESET_AO_SAR_ADC 4 +#define RESET_AO_UART2 5 +#define RESET_AO_IR_OUT 6 + +#endif diff --git a/include/exception.h b/include/exception.h new file mode 100644 index 0000000000..fc02490223 --- /dev/null +++ b/include/exception.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * The 'exception' command can be used for testing exception handling. + * + * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de> + */ + +static int do_exception(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + cmd_tbl_t *cp; + + if (argc != 2) + return CMD_RET_USAGE; + + /* drop sub-command parameter */ + argc--; + argv++; + + cp = find_cmd_tbl(argv[0], cmd_sub, ARRAY_SIZE(cmd_sub)); + + if (cp) + return cp->cmd(cmdtp, flag, argc, argv); + + return CMD_RET_USAGE; +} + +static int exception_complete(int argc, char * const argv[], char last_char, + int maxv, char *cmdv[]) +{ + int len = 0; + int i = 0; + cmd_tbl_t *cmdtp; + + switch (argc) { + case 1: + break; + case 2: + len = strlen(argv[1]); + break; + default: + return 0; + } + for (cmdtp = cmd_sub; cmdtp != cmd_sub + ARRAY_SIZE(cmd_sub); cmdtp++) { + if (i >= maxv - 1) + return i; + if (!strncmp(argv[1], cmdtp->name, len)) + cmdv[i++] = cmdtp->name; + } + cmdv[i] = NULL; + return i; +} + +U_BOOT_CMD_COMPLETE( + exception, 2, 0, do_exception, + "Forces an exception to occur", + exception_help_text, exception_complete +); diff --git a/include/image.h b/include/image.h index 765ffecee0..889305cbef 100644 --- a/include/image.h +++ b/include/image.h @@ -306,6 +306,7 @@ enum { IH_COMP_COUNT, }; +#define LZ4F_MAGIC 0x184D2204 /* LZ4 Magic Number */ #define IH_MAGIC 0x27051956 /* Image Magic Number */ #define IH_NMLEN 32 /* Image Name Length */ @@ -1312,6 +1313,7 @@ int android_image_get_second(const struct andr_img_hdr *hdr, ulong *second_data, ulong *second_len); ulong android_image_get_end(const struct andr_img_hdr *hdr); ulong android_image_get_kload(const struct andr_img_hdr *hdr); +ulong android_image_get_kcomp(const struct andr_img_hdr *hdr); void android_print_contents(const struct andr_img_hdr *hdr); #endif /* CONFIG_ANDROID_BOOT_IMAGE */ diff --git a/include/linux/completion.h b/include/linux/completion.h new file mode 100644 index 0000000000..9835826d28 --- /dev/null +++ b/include/linux/completion.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPLETION_H +#define __LINUX_COMPLETION_H + +/* + * (C) Copyright 2001 Linus Torvalds + * + * Atomic wait-for-completion handler data structures. + * See kernel/sched/completion.c for details. + */ +#ifndef __UBOOT__ +#include <linux/wait.h> +#endif /* __UBOOT__ */ + +/* + * struct completion - structure used to maintain state for a "completion" + * + * This is the opaque structure used to maintain the state for a "completion". + * Completions currently use a FIFO to queue threads that have to wait for + * the "completion" event. + * + * See also: complete(), wait_for_completion() (and friends _timeout, + * _interruptible, _interruptible_timeout, and _killable), init_completion(), + * reinit_completion(), and macros DECLARE_COMPLETION(), + * DECLARE_COMPLETION_ONSTACK(). + */ +struct completion { + unsigned int done; +#ifndef __UBOOT__ + wait_queue_head_t wait; +#endif /* __UBOOT__ */ +}; + +#define init_completion_map(x, m) __init_completion(x) +#define init_completion(x) __init_completion(x) +static inline void complete_acquire(struct completion *x) {} +static inline void complete_release(struct completion *x) {} + +#define COMPLETION_INITIALIZER(work) \ + { 0, __WAIT_QUEUE_HEAD_INITIALIZER((work).wait) } + +#define COMPLETION_INITIALIZER_ONSTACK_MAP(work, map) \ + (*({ init_completion_map(&(work), &(map)); &(work); })) + +#define COMPLETION_INITIALIZER_ONSTACK(work) \ + (*({ init_completion(&work); &work; })) + +/** + * DECLARE_COMPLETION - declare and initialize a completion structure + * @work: identifier for the completion structure + * + * This macro declares and initializes a completion structure. Generally used + * for static declarations. You should use the _ONSTACK variant for automatic + * variables. + */ +#define DECLARE_COMPLETION(work) \ + struct completion work = COMPLETION_INITIALIZER(work) + +/* + * Lockdep needs to run a non-constant initializer for on-stack + * completions - so we use the _ONSTACK() variant for those that + * are on the kernel stack: + */ +/** + * DECLARE_COMPLETION_ONSTACK - declare and initialize a completion structure + * @work: identifier for the completion structure + * + * This macro declares and initializes a completion structure on the kernel + * stack. + */ +#ifdef CONFIG_LOCKDEP +# define DECLARE_COMPLETION_ONSTACK(work) \ + struct completion work = COMPLETION_INITIALIZER_ONSTACK(work) +# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) \ + struct completion work = COMPLETION_INITIALIZER_ONSTACK_MAP(work, map) +#else +# define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work) +# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) DECLARE_COMPLETION(work) +#endif + +/** + * init_completion - Initialize a dynamically allocated completion + * @x: pointer to completion structure that is to be initialized + * + * This inline function will initialize a dynamically created completion + * structure. + */ +static inline void __init_completion(struct completion *x) +{ + x->done = 0; +#ifndef __UBOOT__ + init_waitqueue_head(&x->wait); +#endif /* __UBOOT__ */ +} + +/** + * reinit_completion - reinitialize a completion structure + * @x: pointer to completion structure that is to be reinitialized + * + * This inline function should be used to reinitialize a completion structure so it can + * be reused. This is especially important after complete_all() is used. + */ +static inline void reinit_completion(struct completion *x) +{ + x->done = 0; +} + +#ifndef __UBOOT__ +extern void wait_for_completion(struct completion *); +extern void wait_for_completion_io(struct completion *); +extern int wait_for_completion_interruptible(struct completion *x); +extern int wait_for_completion_killable(struct completion *x); +extern unsigned long wait_for_completion_timeout(struct completion *x, + unsigned long timeout); +extern unsigned long wait_for_completion_io_timeout(struct completion *x, + unsigned long timeout); +extern long wait_for_completion_interruptible_timeout( + struct completion *x, unsigned long timeout); +extern long wait_for_completion_killable_timeout( + struct completion *x, unsigned long timeout); +extern bool try_wait_for_completion(struct completion *x); +extern bool completion_done(struct completion *x); + +extern void complete(struct completion *); +extern void complete_all(struct completion *); + +#else /* __UBOOT __ */ + +#define wait_for_completion(x) do {} while (0) +#define wait_for_completion_io(x) do {} while (0) + +inline int wait_for_completion_interruptible(struct completion *x) +{ + return 1; +} +inline int wait_for_completion_killable(struct completion *x) +{ + return 1; +} +inline unsigned long wait_for_completion_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline unsigned long wait_for_completion_io_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline long wait_for_completion_interruptible_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline long wait_for_completion_killable_timeout(struct completion *x, + unsigned long timeout) +{ + return 1; +} +inline bool try_wait_for_completion(struct completion *x) +{ + return 1; +} +inline bool completion_done(struct completion *x) +{ + return 1; +} + +#define complete(x) do {} while (0) +#define complete_all(x) do {} while (0) +#endif /* __UBOOT__ */ + +#endif diff --git a/include/linux/io.h b/include/linux/io.h index 9badab49b0..79847886be 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -65,8 +65,8 @@ static inline void __iomem *ioremap(resource_size_t offset, static inline void iounmap(void __iomem *addr) { } +#endif #define devm_ioremap(dev, offset, size) ioremap(offset, size) -#endif #endif /* _LINUX_IO_H */ diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 9f5dc81aca..bd373b9617 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -15,6 +15,7 @@ #include <config.h> +#include <dm/device.h> #include <linux/compat.h> #include <linux/mtd/mtd.h> #include <linux/mtd/flashchip.h> @@ -498,6 +499,13 @@ struct nand_hw_control { struct nand_chip *active; }; +static inline void nand_hw_control_init(struct nand_hw_control *nfc) +{ + nfc->active = NULL; + spin_lock_init(&nfc->lock); + init_waitqueue_head(&nfc->wq); +} + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -961,6 +969,17 @@ struct nand_chip { void *priv; }; +static inline void nand_set_flash_node(struct nand_chip *chip, + ofnode node) +{ + chip->flash_node = ofnode_to_offset(node); +} + +static inline ofnode nand_get_flash_node(struct nand_chip *chip) +{ + return offset_to_ofnode(chip->flash_node); +} + static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) { return container_of(mtd, struct nand_chip, mtd); @@ -1280,4 +1299,34 @@ int nand_maximize_ecc(struct nand_chip *chip, /* Reset and initialize a NAND device */ int nand_reset(struct nand_chip *chip, int chipnr); + +/* NAND operation helpers */ +int nand_reset_op(struct nand_chip *chip); +int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, + unsigned int len); +int nand_status_op(struct nand_chip *chip, u8 *status); +int nand_exit_status_op(struct nand_chip *chip); +int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); +int nand_read_page_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, void *buf, unsigned int len); +int nand_change_read_column_op(struct nand_chip *chip, + unsigned int offset_in_page, void *buf, + unsigned int len, bool force_8bit); +int nand_read_oob_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, void *buf, unsigned int len); +int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, const void *buf, + unsigned int len); +int nand_prog_page_end_op(struct nand_chip *chip); +int nand_prog_page_op(struct nand_chip *chip, unsigned int page, + unsigned int offset_in_page, const void *buf, + unsigned int len); +int nand_change_write_column_op(struct nand_chip *chip, + unsigned int offset_in_page, const void *buf, + unsigned int len, bool force_8bit); +int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, + bool force_8bit); +int nand_write_data_op(struct nand_chip *chip, const void *buf, + unsigned int len, bool force_8bit); + #endif /* __LINUX_MTD_RAWNAND_H */ diff --git a/include/malloc.h b/include/malloc.h index b714fedf45..5efa6920b2 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -878,7 +878,6 @@ extern Void_t* sbrk(); #define memalign memalign_simple static inline void free(void *ptr) {} void *calloc(size_t nmemb, size_t size); -void *memalign_simple(size_t alignment, size_t bytes); void *realloc_simple(void *ptr, size_t size); void malloc_simple_info(void); #else @@ -914,6 +913,7 @@ int initf_malloc(void); /* Simple versions which can be used when space is tight */ void *malloc_simple(size_t size); +void *memalign_simple(size_t alignment, size_t bytes); #pragma GCC visibility push(hidden) # if __STD_C diff --git a/include/pci.h b/include/pci.h index 5fb212cab1..9668503f09 100644 --- a/include/pci.h +++ b/include/pci.h @@ -545,7 +545,11 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#define MAX_PCI_REGIONS 7 +#ifdef CONFIG_NR_DRAM_BANKS +#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7) +#else +#define MAX_PCI_REGIONS 7 +#endif #define INDIRECT_TYPE_NO_PCIE_LINK 1 diff --git a/include/regmap.h b/include/regmap.h index 8359c511d2..3cd7a66cea 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -274,7 +274,7 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, if (cond) \ break; \ if (IS_ENABLED(CONFIG_SANDBOX) && test_add_time) \ - sandbox_timer_add_offset(test_add_time); \ + timer_test_add_offset(test_add_time); \ if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \ __ret = regmap_read((map), (addr), &(val)); \ break; \ diff --git a/include/reset.h b/include/reset.h index 65aa7a4ce5..a1a9ad5603 100644 --- a/include/reset.h +++ b/include/reset.h @@ -43,6 +43,8 @@ struct udevice; * @data: An optional data field for scenarios where a single integer ID is not * sufficient. If used, it can be populated through an .of_xlate op and * processed during the various reset ops. + * @polarity: An optional polarity field for drivers that support + * different reset polarities. * * Should additional information to identify and configure any reset signal * for any provider be required in the future, the struct could be expanded to @@ -59,6 +61,7 @@ struct reset_ctl { */ unsigned long id; unsigned long data; + unsigned long polarity; }; /** diff --git a/include/time.h b/include/time.h index 825991e222..9fd0d73fb4 100644 --- a/include/time.h +++ b/include/time.h @@ -14,6 +14,14 @@ unsigned long get_timer(unsigned long base); unsigned long timer_get_us(void); /* + * timer_test_add_offset() + * + * Allow tests to add to the time reported through lib/time.c functions + * offset: number of milliseconds to advance the system time + */ +void timer_test_add_offset(unsigned long offset); + +/* * These inlines deal with timer wrapping correctly. You are * strongly encouraged to use them * 1. Because people otherwise forget diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 4068de045d..a6c12212a9 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -9,6 +9,7 @@ #define __DWC2_USB_GADGET #define PHY0_SLEEP (1 << 5) +#define DWC2_MAX_HW_ENDPOINTS 16 struct dwc2_plat_otg_data { void *priv; @@ -22,8 +23,14 @@ struct dwc2_plat_otg_data { unsigned int rx_fifo_sz; unsigned int np_tx_fifo_sz; unsigned int tx_fifo_sz; + unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS]; + unsigned char tx_fifo_sz_nb; + bool force_b_session_valid; + bool activate_stm_id_vb_detection; }; int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata); +int dwc2_udc_B_session_valid(struct udevice *dev); + #endif /* __DWC2_USB_GADGET */ |