diff options
Diffstat (limited to 'include')
81 files changed, 1406 insertions, 7894 deletions
diff --git a/include/.gitignore b/include/.gitignore deleted file mode 100644 index 8e41a9511d..0000000000 --- a/include/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/autoconf.mk* -/bmp_logo.h -/bmp_logo_data.h -/config.h diff --git a/include/ali512x.h b/include/ali512x.h deleted file mode 100644 index 6bb67009c1..0000000000 --- a/include/ali512x.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. - */ - -#ifndef __ASM_IC_ALI512X_H_ -#define __ASM_IC_ALI512X_H_ - -# define ALI_INDEX 0x3f0 -# define ALI_DATA 0x3f1 - -# define ALI_ENABLED 1 -# define ALI_DISABLED 0 - -# define ALI_UART1 0 -# define ALI_UART2 1 - -/* setup functions */ -void ali512x_init(void); -void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel); -void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel); -void ali512x_set_uart(int enabled, int index, u16 io, u8 irq); -void ali512x_set_rtc(int enabled, u16 io, u8 irq); -void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq); -void ali512x_set_cio(int enabled); - - -/* common I/O functions */ -void ali512x_cio_function(int pin, int special, int inv, int input); -void ali512x_cio_out(int pin, int value); -int ali512x_cio_in(int pin); - -/* misc features */ -void ali512x_set_uart2_irda(int enabled); - -#endif diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h deleted file mode 100644 index d24b82d18e..0000000000 --- a/include/andestech/andes_pcu.h +++ /dev/null @@ -1,354 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin <macpaul@andestech.com> - */ - -/* - * Andes Power Control Unit - */ -#ifndef __ANDES_PCU_H -#define __ANDES_PCU_H - -#ifndef __ASSEMBLY__ - -struct pcs { - unsigned int cr; /* PCSx Configuration (clock scaling) */ - unsigned int parm; /* PCSx Parameter*/ - unsigned int stat1; /* PCSx Status 1 */ - unsigned int stat2; /* PCSx Stusts 2 */ - unsigned int pdd; /* PCSx PDD */ -}; - -struct andes_pcu { - unsigned int rev; /* 0x00 - PCU Revision */ - unsigned int spinfo; /* 0x04 - Scratch Pad Info */ - unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ - unsigned int soc_id; /* 0x10 - SoC ID */ - unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ - unsigned int soc_apb; /* 0x18 - SoC APB configuration */ - unsigned int rsvd2; /* 0x1C */ - unsigned int dcsrcr0; /* 0x20 - Driving Capability - and Slew Rate Control 0 */ - unsigned int dcsrcr1; /* 0x24 - Driving Capability - and Slew Rate Control 1 */ - unsigned int dcsrcr2; /* 0x28 - Driving Capability - and Slew Rate Control 2 */ - unsigned int rsvd3; /* 0x2C */ - unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ - unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ - unsigned int dmaes; /* 0x38 - DMA Engine Selection */ - unsigned int rsvd4; /* 0x3C */ - unsigned int oscc; /* 0x40 - OSC Control */ - unsigned int pwmcd; /* 0x44 - PWM Clock divider */ - unsigned int socmisc; /* 0x48 - SoC Misc. */ - unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ - unsigned int bsmcr; /* 0x80 - BSM Controrl */ - unsigned int bsmst; /* 0x84 - BSM Status */ - unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ - unsigned int west; /* 0x8C - Wakeup Event Status */ - unsigned int rsttiming; /* 0x90 - Reset Timing */ - unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ - unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ - struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ - unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ - struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ - unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ - struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ - unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ - struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ - unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ - struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ - unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ - struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ - unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ - struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ - unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ - struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ - unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ - struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ - unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ - unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager - Scratch Pad Memory 0 */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * PCU Revision Register (ro) - */ -#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) -#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) - -/* - * Scratch Pad Info Register (ro) - */ -#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) -#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) - -/* - * SoC ID Register (ro) - */ -#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) -#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) -#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) - -/* - * SoC AHB Configuration Register (ro) - */ -#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) -#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) -#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) -#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) -#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) -#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) -#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) -#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) -#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) -#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) -#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) -#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) -#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) -#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) -#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) -#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) -#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) -#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) -#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) -#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) - -/* - * SoC APB Configuration Register (ro) - */ -#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) -#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) -#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) -#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) -#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) -#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) -#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) -#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) -#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) -#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) -#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) -#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) -#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) - -/* - * Driving Capability and Slew Rate Control Register 0 (rw) - */ -#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) -#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) -#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) -#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) -#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) - -/* - * Driving Capability and Slew Rate Control Register 1 (rw) - */ -#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) - -/* - * Driving Capability and Slew Rate Control Register 2 (rw) - */ -#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) -#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) -#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) -#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) -#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) -#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) -#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) -#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) - -/* - * Multi-function Port Setting Register 0 (rw) - */ -#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) -#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) -#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) -#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) -#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) -#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) -#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) - -/* - * Multi-function Port Setting Register 1 (rw) - */ -#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) -#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) -#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) -#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) -#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) -#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) -#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) -#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) -#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) -#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) -#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) -#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) -#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) -#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) -#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) -#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) - -/* - * DMA Engine Selection Register (rw) - */ -#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) -#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) -#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) -#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) -#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) -#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) -#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) -#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) - -/* - * OSC Control Register (rw) - */ -#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) -#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) -#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) -#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) -#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) -#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) - -/* - * PWM Clock Divider Register (rw) - */ -#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) - -/* - * SoC Misc. Register (rw) - */ -#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) -#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) -#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) -#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) -#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) -#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) -#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) -#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) -#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) -#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) -#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) -#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) -#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) -#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) -#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) -#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) -#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) -#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) -#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) -#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) -#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) -#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) -#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) -#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) -#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) -#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) -#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) -#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) -#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) -#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) - -/* - * BSM Control Register (rw) - */ -#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) -#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) -#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) -#define ANDES_PCU_BSMCR_IE(x) ((x) << 31) - -/* - * BSM Status Register - */ -#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) -#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) -#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) - -/* - * Wakeup Event Sensitivity Register (rw) - */ -#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) - -/* - * Wakeup Event Status Register (ro) - */ -#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) - -/* - * Reset Timing Register - */ -#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) -#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) -#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) -#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) - -/* - * PCU Interrupt Status Register - */ -#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) -#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) -#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) -#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) -#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) -#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) -#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) -#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) -#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) -#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) - -/* - * PCSx Configuration Register - */ -#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) -#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) -#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) -#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ - -/* - * PCSx Parameter Register (rw) - */ -#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) -#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) -#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) - -/* - * PCSx Status Register 1 - */ -#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) -#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) - -/* - * PCSx Status Register 2 - */ -#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) -#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) - -/* - * PCSx PDD Register - * This is reserved for PCS(1-7) - */ -#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) -#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) -#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) -#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) - -#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) -#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) -#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) -#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) -#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) -#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) -#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) -#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) -#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) - -#endif /* __ANDES_PCU_H */ diff --git a/include/asm-generic/types.h b/include/asm-generic/types.h deleted file mode 100644 index 7c076c56ce..0000000000 --- a/include/asm-generic/types.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_GENERIC_TYPES_H -#define _ASM_GENERIC_TYPES_H -/* - * int-ll64 is used everywhere now. - */ -#include <asm-generic/int-ll64.h> - -#endif /* _ASM_GENERIC_TYPES_H */ diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index 3d33a5a063..9e5d93ec30 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -1,24 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _GENERIC_UNALIGNED_H #define _GENERIC_UNALIGNED_H #include <asm/byteorder.h> -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -/* - * Select endianness - */ -#if defined(__LITTLE_ENDIAN) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#elif defined(__BIG_ENDIAN) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#else -#error invalid endian -#endif +#define __get_unaligned_t(type, ptr) ({ \ + const struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \ + __pptr->x; \ +}) + +#define __put_unaligned_t(type, val, ptr) do { \ + struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \ + __pptr->x = (val); \ +} while (0) + +#define get_unaligned(ptr) __get_unaligned_t(typeof(*(ptr)), (ptr)) +#define put_unaligned(val, ptr) __put_unaligned_t(typeof(*(ptr)), (val), (ptr)) + +static inline u16 get_unaligned_le16(const void *p) +{ + return le16_to_cpu(__get_unaligned_t(__le16, p)); +} + +static inline u32 get_unaligned_le32(const void *p) +{ + return le32_to_cpu(__get_unaligned_t(__le32, p)); +} + +static inline u64 get_unaligned_le64(const void *p) +{ + return le64_to_cpu(__get_unaligned_t(__le64, p)); +} + +static inline void put_unaligned_le16(u16 val, void *p) +{ + __put_unaligned_t(__le16, cpu_to_le16(val), p); +} + +static inline void put_unaligned_le32(u32 val, void *p) +{ + __put_unaligned_t(__le32, cpu_to_le32(val), p); +} + +static inline void put_unaligned_le64(u64 val, void *p) +{ + __put_unaligned_t(__le64, cpu_to_le64(val), p); +} + +static inline u16 get_unaligned_be16(const void *p) +{ + return be16_to_cpu(__get_unaligned_t(__be16, p)); +} + +static inline u32 get_unaligned_be32(const void *p) +{ + return be32_to_cpu(__get_unaligned_t(__be32, p)); +} + +static inline u64 get_unaligned_be64(const void *p) +{ + return be64_to_cpu(__get_unaligned_t(__be64, p)); +} + +static inline void put_unaligned_be16(u16 val, void *p) +{ + __put_unaligned_t(__be16, cpu_to_be16(val), p); +} + +static inline void put_unaligned_be32(u32 val, void *p) +{ + __put_unaligned_t(__be32, cpu_to_be32(val), p); +} + +static inline void put_unaligned_be64(u64 val, void *p) +{ + __put_unaligned_t(__be64, cpu_to_be64(val), p); +} /* Allow unaligned memory access */ void allow_unaligned(void); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 9d2a225e7e..2a136b96a6 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -35,11 +35,15 @@ #devtypel "_boot=" \ BOOTENV_SHARED_BLKDEV_BODY(devtypel) +#define BOOTENV_DEV_BLKDEV_NONE(devtypeu, devtypel, instance) + #define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "devnum=" #instance "; " \ "run " #devtypel "_boot\0" +#define BOOTENV_DEV_NAME_BLKDEV_NONE(devtypeu, devtypel, instance) + #define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -59,6 +63,10 @@ #define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc) #define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_SHARED_MMC +#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_SHARED_MMC #define BOOTENV_DEV_MMC \ @@ -190,6 +198,10 @@ #define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata) #define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_SHARED_SATA +#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_SHARED_SATA #define BOOTENV_DEV_SATA \ @@ -293,6 +305,11 @@ BOOTENV_SHARED_BLKDEV_BODY(usb) #define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_RUN_NET_USB_START +#define BOOTENV_SHARED_USB +#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_RUN_NET_USB_START #define BOOTENV_SHARED_USB @@ -395,6 +412,9 @@ "\0" #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ "dhcp " +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_DEV_DHCP BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_DHCP BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_DEV_DHCP \ BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP @@ -413,6 +433,9 @@ "fi\0" #define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \ "pxe " +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_DEV_PXE BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_PXE BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_DEV_PXE \ BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE diff --git a/include/configs/ae350.h b/include/configs/ae350.h index b566ecf296..23e4801379 100644 --- a/include/configs/ae350.h +++ b/include/configs/ae350.h @@ -83,11 +83,15 @@ #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00080000\0" \ - "pxefile_addr_r=0x01f00000\0" \ - "scriptaddr=0x01f00000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02800000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x00600000\0" \ + "kernel_comp_addr_r=0x04600000\0" \ + "kernel_comp_size=0x04000000\0" \ + "pxefile_addr_r=0x08600000\0" \ + "scriptaddr=0x08700000\0" \ + "fdt_addr_r=0x08800000\0" \ + "ramdisk_addr_r=0x08900000\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/eagle.h b/include/configs/eagle.h deleted file mode 100644 index c751f75a7d..0000000000 --- a/include/configs/eagle.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/eagle.h - * This file is Eagle board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - */ - -#ifndef __EAGLE_H -#define __EAGLE_H - -#include "rcar-gen3-common.h" - -/* Environment compatibility */ - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - -#endif /* __EAGLE_H */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 8cc4e0db03..6404b35911 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -11,6 +11,11 @@ /* RTC */ #define CFG_SYS_RTC_BUS_NUM 4 +#if defined(CONFIG_FSL_MC_ENET) +#define AQR113C_PHY_ADDR1 0x0 +#define AQR113C_PHY_ADDR2 0x08 +#endif + /* EMC2305 */ #define I2C_MUX_CH_EMC2305 0x09 #define I2C_EMC2305_ADDR 0x4D diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 9244601284..801cdae470 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -11,6 +11,9 @@ #if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A)) #define GICD_BASE 0xffc01000 #define GICC_BASE 0xffc02000 +#elif defined(CONFIG_MESON_A1) +#define GICD_BASE 0xff901000 +#define GICC_BASE 0xff902000 #else /* MESON GXL and GXBB */ #define GICD_BASE 0xc4301000 #define GICC_BASE 0xc4302000 diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 34856d3004..9bf01cac47 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -36,6 +36,4 @@ #define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) -/* For splashcreen */ - #endif /* __CONFIG_H */ diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 7db72a19ed..29a1197b5a 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -92,19 +92,6 @@ "run distro_bootcmd;" \ "fi;\0" -#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT -/* eMMC default partitions for fastboot command: oem format */ -#define STM32MP_PARTS_DEFAULT \ - "partitions=" \ - "name=ssbl,size=2M;" \ - "name=bootfs,size=64MB,bootable;" \ - "name=vendorfs,size=16M;" \ - "name=rootfs,size=746M;" \ - "name=userfs,size=-\0" -#else -#define STM32MP_PARTS_DEFAULT -#endif - #define STM32MP_EXTRA \ "env_check=if env info -p -d -q; then env save; fi\0" \ "boot_net_usb_start=true\0" @@ -138,7 +125,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 866cd7a719..b45982a35b 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -47,7 +47,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ ST_STM32MP1_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 8f44c6f66a..cd7359c2f8 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -40,19 +40,29 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEFAULT_DFU_ALT_INFO +#else #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ "mtd nor1=u-boot.bin raw 200000 100000;" \ "fip.bin raw 180000 78000;" \ "optee.bin raw 500000 100000\0" +#endif /* GUIDs for capsule updatable firmware images */ #define DEVELOPERBOX_UBOOT_IMAGE_GUID \ EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \ 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00) +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEVELOPERBOX_FIP_IMAGE_GUID \ + EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \ + 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08) +#else #define DEVELOPERBOX_FIP_IMAGE_GUID \ EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \ 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98) +#endif #define DEVELOPERBOX_OPTEE_IMAGE_GUID \ EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h deleted file mode 100644 index ac6d46f917..0000000000 --- a/include/configs/ti816x_evm.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti816x_evm.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - */ - -#ifndef __CONFIG_TI816X_EVM_H -#define __CONFIG_TI816X_EVM_H - -#include <configs/ti_armv7_omap.h> -#include <asm/arch/omap.h> - -#define CFG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/** - * Platform/Board specific defs - */ -#define CFG_SYS_TIMERBASE 0x4802E000 - -/* - * NS16550 Configuration - */ -#define CFG_SYS_NS16550_CLK (48000000) -#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ - -/* allow overwriting serial config and ethaddr */ - - -/* - * GPMC NAND block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#define CFG_SYS_NAND_BASE 0x8000000 - -/* NAND: SPL related configs */ - -/* NAND: device related configs */ -/* NAND: driver related configs */ -#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CFG_SYS_NAND_ECCSIZE 512 -#define CFG_SYS_NAND_ECCBYTES 14 - -/* SPL */ -/* Defines for SPL */ - -#endif diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h new file mode 100644 index 0000000000..58c2e88c0b --- /dev/null +++ b/include/configs/v3hsk.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/v3hsk.h + * This file is V3HSK board configuration. + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#ifndef __V3HSK_H +#define __V3HSK_H + +#include "rcar-gen3-common.h" + +/* Environment compatibility */ + +/* SH Ether */ +#define CFG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_PHY_ADDR 0x0 +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID +#define CFG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ + +#endif /* __V3HSK_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 011f0034c5..995427db63 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -60,6 +60,9 @@ "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ "script_size_f=0x80000\0" \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ #if defined(CONFIG_MMC_SDHCI_ZYNQ) # define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) diff --git a/include/dp83848.h b/include/dp83848.h deleted file mode 100644 index f1bc3d86f2..0000000000 --- a/include/dp83848.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * DP83848 ethernet Physical layer - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - */ - - -/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ - -#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ -#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ -#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ -#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ -#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ -#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ -#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ -#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ -#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ -#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ - -/*--Bit definitions: DP83848_CTL_REG */ -#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ -#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ -#define DP83848_SPEED_SELECT (1 << 13) -#define DP83848_AUTONEG (1 << 12) -#define DP83848_POWER_DOWN (1 << 11) -#define DP83848_ISOLATE (1 << 10) -#define DP83848_RESTART_AUTONEG (1 << 9) -#define DP83848_DUPLEX_MODE (1 << 8) -#define DP83848_COLLISION_TEST (1 << 7) - -/*--Bit definitions: DP83848_STAT_REG */ -#define DP83848_100BASE_T4 (1 << 15) -#define DP83848_100BASE_TX_FD (1 << 14) -#define DP83848_100BASE_TX_HD (1 << 13) -#define DP83848_10BASE_T_FD (1 << 12) -#define DP83848_10BASE_T_HD (1 << 11) -#define DP83848_MF_PREAMB_SUPPR (1 << 6) -#define DP83848_AUTONEG_COMP (1 << 5) -#define DP83848_RMT_FAULT (1 << 4) -#define DP83848_AUTONEG_ABILITY (1 << 3) -#define DP83848_LINK_STATUS (1 << 2) -#define DP83848_JABBER_DETECT (1 << 1) -#define DP83848_EXTEND_CAPAB (1 << 0) - -/*--definitions: DP83848_PHYID1 */ -#define DP83848_PHYID1_OUI 0x2000 -#define DP83848_PHYID2_OUI 0x5c90 - -/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ -#define DP83848_NP (1 << 15) -#define DP83848_ACK (1 << 14) -#define DP83848_RF (1 << 13) -#define DP83848_PAUSE (1 << 10) -#define DP83848_T4 (1 << 9) -#define DP83848_TX_FDX (1 << 8) -#define DP83848_TX_HDX (1 << 7) -#define DP83848_10_FDX (1 << 6) -#define DP83848_10_HDX (1 << 5) -#define DP83848_AN_IEEE_802_3 0x0001 - -/*--Bit definitions: DP83848_ANER */ -#define DP83848_PDF (1 << 4) -#define DP83848_LP_NP_ABLE (1 << 3) -#define DP83848_NP_ABLE (1 << 2) -#define DP83848_PAGE_RX (1 << 1) -#define DP83848_LP_AN_ABLE (1 << 0) - -/*--Bit definitions: DP83848_PHY_STAT */ -#define DP83848_RX_ERR_LATCH (1 << 13) -#define DP83848_POLARITY_STAT (1 << 12) -#define DP83848_FALSE_CAR_SENSE (1 << 11) -#define DP83848_SIG_DETECT (1 << 10) -#define DP83848_DESCRAM_LOCK (1 << 9) -#define DP83848_PAGE_RCV (1 << 8) -#define DP83848_PHY_RMT_FAULT (1 << 6) -#define DP83848_JABBER (1 << 5) -#define DP83848_AUTONEG_COMPLETE (1 << 4) -#define DP83848_LOOPBACK_STAT (1 << 3) -#define DP83848_DUPLEX (1 << 2) -#define DP83848_SPEED (1 << 1) -#define DP83848_LINK (1 << 0) diff --git a/include/ds1722.h b/include/ds1722.h deleted file mode 100644 index e115696cea..0000000000 --- a/include/ds1722.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _DS1722_H_ -#define _DS1722_H_ - -#define DS1722_RESOLUTION_8BIT 0x0 -#define DS1722_RESOLUTION_9BIT 0x1 -#define DS1722_RESOLUTION_10BIT 0x2 -#define DS1722_RESOLUTION_11BIT 0x3 -#define DS1722_RESOLUTION_12BIT 0x4 - -int ds1722_probe(int dev); - -#endif /* _DS1722_H_ */ diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h index c7ed0a8db7..79775a5134 100644 --- a/include/dt-bindings/clock/microchip-mpfs-clock.h +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h @@ -1,7 +1,7 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2020 Microchip Technology Inc. - * Padmarao Begari <padmarao.begari@microchip.com> + * Daire McNamara,<daire.mcnamara@microchip.com> + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ @@ -45,4 +45,27 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +/* Clock Conditioning Circuitry Clock IDs */ + +#define CLK_CCC_PLL0 0 +#define CLK_CCC_PLL1 1 +#define CLK_CCC_DLL0 2 +#define CLK_CCC_DLL1 3 + +#define CLK_CCC_PLL0_OUT0 4 +#define CLK_CCC_PLL0_OUT1 5 +#define CLK_CCC_PLL0_OUT2 6 +#define CLK_CCC_PLL0_OUT3 7 + +#define CLK_CCC_PLL1_OUT0 8 +#define CLK_CCC_PLL1_OUT1 9 +#define CLK_CCC_PLL1_OUT2 10 +#define CLK_CCC_PLL1_OUT3 11 + +#define CLK_CCC_DLL0_OUT0 12 +#define CLK_CCC_DLL0_OUT1 13 + +#define CLK_CCC_DLL1_OUT0 14 +#define CLK_CCC_DLL1_OUT1 15 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h index 799dee5b80..da4cb75674 100644 --- a/include/dt-bindings/clock/stm32mp13-clks.h +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. */ diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h new file mode 100644 index 0000000000..40e57a5ff1 --- /dev/null +++ b/include/dt-bindings/gpio/meson-a1-gpio.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_A1_GPIO_H +#define _DT_BINDINGS_MESON_A1_GPIO_H + +#define GPIOP_0 0 +#define GPIOP_1 1 +#define GPIOP_2 2 +#define GPIOP_3 3 +#define GPIOP_4 4 +#define GPIOP_5 5 +#define GPIOP_6 6 +#define GPIOP_7 7 +#define GPIOP_8 8 +#define GPIOP_9 9 +#define GPIOP_10 10 +#define GPIOP_11 11 +#define GPIOP_12 12 +#define GPIOB_0 13 +#define GPIOB_1 14 +#define GPIOB_2 15 +#define GPIOB_3 16 +#define GPIOB_4 17 +#define GPIOB_5 18 +#define GPIOB_6 19 +#define GPIOX_0 20 +#define GPIOX_1 21 +#define GPIOX_2 22 +#define GPIOX_3 23 +#define GPIOX_4 24 +#define GPIOX_5 25 +#define GPIOX_6 26 +#define GPIOX_7 27 +#define GPIOX_8 28 +#define GPIOX_9 29 +#define GPIOX_10 30 +#define GPIOX_11 31 +#define GPIOX_12 32 +#define GPIOX_13 33 +#define GPIOX_14 34 +#define GPIOX_15 35 +#define GPIOX_16 36 +#define GPIOF_0 37 +#define GPIOF_1 38 +#define GPIOF_2 39 +#define GPIOF_3 40 +#define GPIOF_4 41 +#define GPIOF_5 42 +#define GPIOF_6 43 +#define GPIOF_7 44 +#define GPIOF_8 45 +#define GPIOF_9 46 +#define GPIOF_10 47 +#define GPIOF_11 48 +#define GPIOF_12 49 +#define GPIOA_0 50 +#define GPIOA_1 51 +#define GPIOA_2 52 +#define GPIOA_3 53 +#define GPIOA_4 54 +#define GPIOA_5 55 +#define GPIOA_6 56 +#define GPIOA_7 57 +#define GPIOA_8 58 +#define GPIOA_9 59 +#define GPIOA_10 60 +#define GPIOA_11 61 + +#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h deleted file mode 100644 index eba1bac7df..0000000000 --- a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H - -#define PLIC_INT_INVALID 0 -#define PLIC_INT_L2_METADATA_CORR 1 -#define PLIC_INT_L2_METADATA_UNCORR 2 -#define PLIC_INT_L2_DATA_CORR 3 -#define PLIC_INT_L2_DATA_UNCORR 4 -#define PLIC_INT_DMA_CH0_DONE 5 -#define PLIC_INT_DMA_CH0_ERR 6 -#define PLIC_INT_DMA_CH1_DONE 7 -#define PLIC_INT_DMA_CH1_ERR 8 -#define PLIC_INT_DMA_CH2_DONE 9 -#define PLIC_INT_DMA_CH2_ERR 10 -#define PLIC_INT_DMA_CH3_DONE 11 -#define PLIC_INT_DMA_CH3_ERR 12 - -#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13 -#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14 -#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15 -#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16 -#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17 -#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18 -#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19 -#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20 -#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21 -#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22 -#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23 -#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24 -#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25 -#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26 -#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27 -#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28 -#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29 -#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30 -#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31 -#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32 -#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33 -#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34 -#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35 -#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36 -#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37 -#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38 -#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39 -#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40 -#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41 -#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42 -#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43 -#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44 -#define PLIC_INT_GPIO1_BIT18 45 -#define PLIC_INT_GPIO1_BIT19 46 -#define PLIC_INT_GPIO1_BIT20 47 -#define PLIC_INT_GPIO1_BIT21 48 -#define PLIC_INT_GPIO1_BIT22 49 -#define PLIC_INT_GPIO1_BIT23 50 -#define PLIC_INT_GPIO0_NON_DIRECT 51 -#define PLIC_INT_GPIO1_NON_DIRECT 52 -#define PLIC_INT_GPIO2_NON_DIRECT 53 -#define PLIC_INT_SPI0 54 -#define PLIC_INT_SPI1 55 -#define PLIC_INT_CAN0 56 -#define PLIC_INT_CAN1 57 -#define PLIC_INT_I2C0_MAIN 58 -#define PLIC_INT_I2C0_ALERT 59 -#define PLIC_INT_I2C0_SUS 60 -#define PLIC_INT_I2C1_MAIN 61 -#define PLIC_INT_I2C1_ALERT 62 -#define PLIC_INT_I2C1_SUS 63 -#define PLIC_INT_MAC0_INT 64 -#define PLIC_INT_MAC0_QUEUE1 65 -#define PLIC_INT_MAC0_QUEUE2 66 -#define PLIC_INT_MAC0_QUEUE3 67 -#define PLIC_INT_MAC0_EMAC 68 -#define PLIC_INT_MAC0_MMSL 69 -#define PLIC_INT_MAC1_INT 70 -#define PLIC_INT_MAC1_QUEUE1 71 -#define PLIC_INT_MAC1_QUEUE2 72 -#define PLIC_INT_MAC1_QUEUE3 73 -#define PLIC_INT_MAC1_EMAC 74 -#define PLIC_INT_MAC1_MMSL 75 -#define PLIC_INT_DDRC_TRAIN 76 -#define PLIC_INT_SCB_INTERRUPT 77 -#define PLIC_INT_ECC_ERROR 78 -#define PLIC_INT_ECC_CORRECT 79 -#define PLIC_INT_RTC_WAKEUP 80 -#define PLIC_INT_RTC_MATCH 81 -#define PLIC_INT_TIMER1 82 -#define PLIC_INT_TIMER2 83 -#define PLIC_INT_ENVM 84 -#define PLIC_INT_QSPI 85 -#define PLIC_INT_USB_DMA 86 -#define PLIC_INT_USB_MC 87 -#define PLIC_INT_MMC_MAIN 88 -#define PLIC_INT_MMC_WAKEUP 89 -#define PLIC_INT_MMUART0 90 -#define PLIC_INT_MMUART1 91 -#define PLIC_INT_MMUART2 92 -#define PLIC_INT_MMUART3 93 -#define PLIC_INT_MMUART4 94 -#define PLIC_INT_G5C_DEVRST 95 -#define PLIC_INT_G5C_MESSAGE 96 -#define PLIC_INT_USOC_VC_INTERRUPT 97 -#define PLIC_INT_USOC_SMB_INTERRUPT 98 -#define PLIC_INT_E51_0_MAINTENACE 99 -#define PLIC_INT_WDOG0_MRVP 100 -#define PLIC_INT_WDOG1_MRVP 101 -#define PLIC_INT_WDOG2_MRVP 102 -#define PLIC_INT_WDOG3_MRVP 103 -#define PLIC_INT_WDOG4_MRVP 104 -#define PLIC_INT_WDOG0_TOUT 105 -#define PLIC_INT_WDOG1_TOUT 106 -#define PLIC_INT_WDOG2_TOUT 107 -#define PLIC_INT_WDOG3_TOUT 108 -#define PLIC_INT_WDOG4_TOUT 109 -#define PLIC_INT_G5C_MSS_SPI 110 -#define PLIC_INT_VOLT_TEMP_ALARM 111 -#define PLIC_INT_ATHENA_COMPLETE 112 -#define PLIC_INT_ATHENA_ALARM 113 -#define PLIC_INT_ATHENA_BUS_ERROR 114 -#define PLIC_INT_USOC_AXIC_US 115 -#define PLIC_INT_USOC_AXIC_DS 116 -#define PLIC_INT_SPARE 117 -#define PLIC_INT_FABRIC_F2H_0 118 -#define PLIC_INT_FABRIC_F2H_1 119 -#define PLIC_INT_FABRIC_F2H_2 120 -#define PLIC_INT_FABRIC_F2H_3 121 -#define PLIC_INT_FABRIC_F2H_4 122 -#define PLIC_INT_FABRIC_F2H_5 123 -#define PLIC_INT_FABRIC_F2H_6 124 -#define PLIC_INT_FABRIC_F2H_7 125 -#define PLIC_INT_FABRIC_F2H_8 126 -#define PLIC_INT_FABRIC_F2H_9 127 -#define PLIC_INT_FABRIC_F2H_10 128 -#define PLIC_INT_FABRIC_F2H_11 129 -#define PLIC_INT_FABRIC_F2H_12 130 -#define PLIC_INT_FABRIC_F2H_13 131 -#define PLIC_INT_FABRIC_F2H_14 132 -#define PLIC_INT_FABRIC_F2H_15 133 -#define PLIC_INT_FABRIC_F2H_16 134 -#define PLIC_INT_FABRIC_F2H_17 135 -#define PLIC_INT_FABRIC_F2H_18 136 -#define PLIC_INT_FABRIC_F2H_19 137 -#define PLIC_INT_FABRIC_F2H_20 138 -#define PLIC_INT_FABRIC_F2H_21 139 -#define PLIC_INT_FABRIC_F2H_22 140 -#define PLIC_INT_FABRIC_F2H_23 141 -#define PLIC_INT_FABRIC_F2H_24 142 -#define PLIC_INT_FABRIC_F2H_25 143 -#define PLIC_INT_FABRIC_F2H_26 144 -#define PLIC_INT_FABRIC_F2H_27 145 -#define PLIC_INT_FABRIC_F2H_28 146 -#define PLIC_INT_FABRIC_F2H_29 147 -#define PLIC_INT_FABRIC_F2H_30 148 -#define PLIC_INT_FABRIC_F2H_31 149 -#define PLIC_INT_FABRIC_F2H_32 150 -#define PLIC_INT_FABRIC_F2H_33 151 -#define PLIC_INT_FABRIC_F2H_34 152 -#define PLIC_INT_FABRIC_F2H_35 153 -#define PLIC_INT_FABRIC_F2H_36 154 -#define PLIC_INT_FABRIC_F2H_37 155 -#define PLIC_INT_FABRIC_F2H_38 156 -#define PLIC_INT_FABRIC_F2H_39 157 -#define PLIC_INT_FABRIC_F2H_40 158 -#define PLIC_INT_FABRIC_F2H_41 159 -#define PLIC_INT_FABRIC_F2H_42 160 -#define PLIC_INT_FABRIC_F2H_43 161 -#define PLIC_INT_FABRIC_F2H_44 162 -#define PLIC_INT_FABRIC_F2H_45 163 -#define PLIC_INT_FABRIC_F2H_46 164 -#define PLIC_INT_FABRIC_F2H_47 165 -#define PLIC_INT_FABRIC_F2H_48 166 -#define PLIC_INT_FABRIC_F2H_49 167 -#define PLIC_INT_FABRIC_F2H_50 168 -#define PLIC_INT_FABRIC_F2H_51 169 -#define PLIC_INT_FABRIC_F2H_52 170 -#define PLIC_INT_FABRIC_F2H_53 171 -#define PLIC_INT_FABRIC_F2H_54 172 -#define PLIC_INT_FABRIC_F2H_55 173 -#define PLIC_INT_FABRIC_F2H_56 174 -#define PLIC_INT_FABRIC_F2H_57 175 -#define PLIC_INT_FABRIC_F2H_58 176 -#define PLIC_INT_FABRIC_F2H_59 177 -#define PLIC_INT_FABRIC_F2H_60 178 -#define PLIC_INT_FABRIC_F2H_61 179 -#define PLIC_INT_FABRIC_F2H_62 180 -#define PLIC_INT_FABRIC_F2H_63 181 -#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182 -#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183 -#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184 -#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185 -#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */ diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h deleted file mode 100644 index c4331b8521..0000000000 --- a/include/dt-bindings/interrupt-controller/riscv-hart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H - -#define HART_INT_U_SOFT 0 -#define HART_INT_S_SOFT 1 -#define HART_INT_M_SOFT 3 -#define HART_INT_U_TIMER 4 -#define HART_INT_S_TIMER 5 -#define HART_INT_M_TIMER 7 -#define HART_INT_U_EXT 8 -#define HART_INT_S_EXT 9 -#define HART_INT_M_EXT 11 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h new file mode 100644 index 0000000000..68ac4e05e3 --- /dev/null +++ b/include/dt-bindings/media/video-interfaces.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2022 Laurent Pinchart <laurent.pinchart@ideasonboard.com> + */ + +#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ +#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ + +#define MEDIA_BUS_TYPE_CSI2_CPHY 1 +#define MEDIA_BUS_TYPE_CSI1 2 +#define MEDIA_BUS_TYPE_CCP2 3 +#define MEDIA_BUS_TYPE_CSI2_DPHY 4 +#define MEDIA_BUS_TYPE_PARALLEL 5 +#define MEDIA_BUS_TYPE_BT656 6 + +#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index 84795ec27a..d2478d9ae3 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -28,7 +28,7 @@ #define BCM_NS3_MEM_SHARE_START 0x8d000000 #define BCM_NS3_MEM_SHARE_LEN 0x020fffff -/* ATF/U-boot/Linux error logs */ +/* ATF/U-Boot/Linux error logs */ #define BCM_NS3_MEM_ELOG_START 0x8f113000 #define BCM_NS3_MEM_ELOG_LEN 0x00100000 diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h new file mode 100644 index 0000000000..8e39dfc0b6 --- /dev/null +++ b/include/dt-bindings/power/meson-a1-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2023 SberDevices, Inc. + * Author: Alexey Romanov <avromanov@sberdevices.ru> + */ + +#ifndef _DT_BINDINGS_MESON_A1_POWER_H +#define _DT_BINDINGS_MESON_A1_POWER_H + +#define PWRC_DSPA_ID 8 +#define PWRC_DSPB_ID 9 +#define PWRC_UART_ID 10 +#define PWRC_DMC_ID 11 +#define PWRC_I2C_ID 12 +#define PWRC_PSRAM_ID 13 +#define PWRC_ACODEC_ID 14 +#define PWRC_AUDIO_ID 15 +#define PWRC_OTP_ID 16 +#define PWRC_DMA_ID 17 +#define PWRC_SD_EMMC_ID 18 +#define PWRC_RAMA_ID 19 +#define PWRC_RAMB_ID 20 +#define PWRC_IR_ID 21 +#define PWRC_SPICC_ID 22 +#define PWRC_SPIFC_ID 23 +#define PWRC_USB_ID 24 +#define PWRC_NIC_ID 25 +#define PWRC_PDMIN_ID 26 +#define PWRC_RSA_ID 27 +#define PWRC_MAX_ID 28 + +#endif diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h index 18ccb05db6..1b83a01de8 100644 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 38d7f66bab..11e08a804f 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -1078,15 +1078,16 @@ struct efi_fw_image { * platforms which enable capsule updates * * @dfu_string: String used to populate dfu_alt_info + * @num_images: The number of images array entries * @images: Pointer to an array of updatable images */ struct efi_capsule_update_info { const char *dfu_string; + int num_images; struct efi_fw_image *images; }; extern struct efi_capsule_update_info update_info; -extern u8 num_image_type_guids; /** * Install the ESRT system table. diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h deleted file mode 100644 index 484bd36334..0000000000 --- a/include/exynos_lcd.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * exynos_lcd.h - Exynos LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef _EXYNOS_LCD_H_ -#define _EXYNOS_LCD_H_ - -enum { - FIMD_RGB_INTERFACE = 1, - FIMD_CPU_INTERFACE = 2, -}; - -enum exynos_fb_rgb_mode_t { - MODE_RGB_P = 0, - MODE_BGR_P = 1, - MODE_RGB_S = 2, - MODE_BGR_S = 3, -}; - -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_freq; /* Frequency */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel */ - - /* Horizontal control register. Timing from data sheet */ - u_char vl_hspw; /* Horz sync pulse width */ - u_char vl_hfpd; /* Wait before of line */ - u_char vl_hbpd; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vspw; /* Vertical sync pulse width */ - u_char vl_vfpd; /* Wait before of frame */ - u_char vl_vbpd; /* Wait end of frame */ - u_char vl_cmd_allow_len; /* Wait end of frame */ - - unsigned int win_id; - unsigned int init_delay; - unsigned int power_on_delay; - unsigned int reset_delay; - unsigned int interface_mode; - unsigned int mipi_enabled; - unsigned int dp_enabled; - unsigned int cs_setup; - unsigned int wr_setup; - unsigned int wr_act; - unsigned int wr_hold; - unsigned int logo_on; - unsigned int logo_width; - unsigned int logo_height; - int logo_x_offset; - int logo_y_offset; - unsigned long logo_addr; - unsigned int rgb_mode; - unsigned int resolution; - - /* parent clock name(MPLL, EPLL or VPLL) */ - unsigned int pclk_name; - /* ratio value for source clock from parent clock. */ - unsigned int sclk_div; - - unsigned int dual_lcd_enabled; - struct exynos_fb *reg; - struct exynos_platform_mipi_dsim *dsim_platform_data_dt; -} vidinfo_t; - -#endif diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h deleted file mode 100644 index e628156c15..0000000000 --- a/include/faraday/ftahbc020s.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - */ - -/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ -#ifndef __FTAHBC020S_H -#define __FTAHBC202S_H - -/* Registers Offsets */ - -/* - * AHB Slave BSR, offset: n * 4, n=0~31 - */ -#ifndef __ASSEMBLY__ -struct ftahbc02s { - unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ - unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ - unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ - unsigned int cr; /* 0x88 - Ctrl Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register - */ -#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) -#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) -/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ -#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ - -/* - * FTAHBC020S_PCR - Priority Control Register - */ -#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ - -/* - * FTAHBC020S_CR - Interrupt Control Register - */ -#define FTAHBC020S_CR_INTSTS (1 << 24) -#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) -#define FTAHBC020S_CR_INTSMASK (1 << 16) -#define FTAHBC020S_CR_REMAP (1 << 0) - -#endif /* __FTAHBC020S_H */ diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h deleted file mode 100644 index 8801bd1350..0000000000 --- a/include/faraday/ftpci100.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation - * - * Copyright (C) 2010 Andes Technology Corporation - * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com> - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - */ - -#ifndef __FTPCI100_H -#define __FTPCI100_H - -/* AHB Control Registers */ -#include <linux/bitops.h> -struct ftpci100_ahbc { - unsigned int iosize; /* 0x00 - I/O Space Size Signal */ - unsigned int prot; /* 0x04 - AHB Protection */ - unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ - unsigned int conf; /* 0x28 - PCI Configuration */ - unsigned int data; /* 0x2c - PCI Configuration DATA */ -}; - -/* - * FTPCI100_IOSIZE_REG's constant definitions - */ -#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ - -/* - * PCI Configuration Register - */ -#define PCI_INT_MASK 0x4c -#define PCI_MEM_BASE_SIZE1 0x50 -#define PCI_MEM_BASE_SIZE2 0x54 -#define PCI_MEM_BASE_SIZE3 0x58 - -/* - * PCI_INT_MASK's bit definitions - */ -#define PCI_INTA_ENABLE (1 << 22) -#define PCI_INTB_ENABLE (1 << 23) -#define PCI_INTC_ENABLE (1 << 24) -#define PCI_INTD_ENABLE (1 << 25) - -/* - * PCI_MEM_BASE_SIZE1's constant definitions - */ -#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ - -#define FTPCI100_MAX_FUNCTIONS 20 -#define PCI_IRQ_LINES 4 - -#define MAX_BUS_NUM 256 -#define MAX_DEV_NUM 32 -#define MAX_FUN_NUM 8 - -#define PCI_MAX_BAR_PER_FUNC 6 - -/* - * PCI_MEM_SIZE - */ -#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) - -/* This definition is used by pci_ftpci_init() */ -#define FTPCI100_BRIDGE_VENDORID 0x159b -#define FTPCI100_BRIDGE_DEVICEID 0x4321 - -void pci_ftpci_init(void); - -struct pcibar { - unsigned int size; - unsigned int addr; -}; - -struct pci_config { - unsigned int bus; - unsigned int dev; /* device */ - unsigned int func; - unsigned int pin; - unsigned short v_id; /* vendor id */ - unsigned short d_id; /* device id */ - struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; -}; - -#endif diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h deleted file mode 100644 index d74da16ef2..0000000000 --- a/include/faraday/ftsdmc020.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h deleted file mode 100644 index e0e5eb339e..0000000000 --- a/include/faraday/ftsdmc021.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin <macpaul@andestech.com> - */ - -/* - * FTSDMC021 - SDRAM Controller - */ -#ifndef __FTSDMC021_H -#define __FTSDMC021_H - -#ifndef __ASSEMBLY__ -#include <linux/bitops.h> -struct ftsdmc021 { - unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */ - unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */ - unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */ - unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */ - unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */ - unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */ - unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */ - unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */ - unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */ - unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */ - unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */ - unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */ - unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */ - unsigned int frr; /* 0x34 - Flush Request Register */ - unsigned int ebisr; /* 0x38 - EBI Support Register */ - unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */ - unsigned int crr; /* 0x100 - Controller Revision Reg */ - unsigned int cfr; /* 0x104 - Controller Feature Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Timing Parameter 1 Register - */ -#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ -#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ -#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ -#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ -#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ -#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parameter 2 Register - */ -#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ -/* b(16:19) - Initial Refresh Times */ -#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) -/* b(20:23) - Initial Pre-Charge Times */ -#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * SDRAM Configuration Register 1 - */ -#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ -#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */ -#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ -#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ -/* b(16) MA2T: Double Memory Address Cycle Enable */ -#define FTSDMC021_CR1_MA2T(x) (1 << 16) -/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ -#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) - -/* - * Configuration Register 2 - */ -#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ -#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ -#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ -#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ -#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ -#define FTSDMC021_CR2_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC021_BANK_ENABLE (1 << 12) - -/* 12-bit base address of external bank. - * Default value is 0x800. - * The 12-bit equals to the haddr[31:20] of AHB address bus. */ -#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) - -/* - * Read Arbitration Grant Window Register - */ -#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) -#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) -#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) -#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) -#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) -#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) -#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) -#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) - -/* - * Flush Request Register - */ -#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) -#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ - -/* - * External Bus Interface Support Register (EBISR) - */ -#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ -#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ -#define FTSDMC021_EBISR_POPREC (1 << 13) -#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ - -/* - * Controller Revision Register (CRR, Read Only) - */ -#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) -#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) -#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) - -/* - * Controller Feature Register (CFR, Read Only) - */ -#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) -#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) -#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) -#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) -#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) -#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) -#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) -#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) -#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) -#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) -#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) - -#endif /* __FTSDMC021_H */ diff --git a/include/fdt_support.h b/include/fdt_support.h index 5638bd4f16..2cd8366898 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -7,7 +7,8 @@ #ifndef __FDT_SUPPORT_H #define __FDT_SUPPORT_H -#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC) +#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \ + !defined(USE_HOSTCC) #include <asm/u-boot.h> #include <linux/libfdt.h> @@ -255,6 +256,14 @@ static inline void fdt_fixup_mtdparts(void *fdt, } #endif +/** + * copy the fixed-partition nodes from U-Boot device tree to external blob + * + * @param blob FDT blob to update + * Return: 0 if ok, or non-zero on error + */ +int fdt_copy_fixed_partitions(void *blob); + void fdt_del_node_and_alias(void *blob, const char *alias); /** diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 2278ac952e..3f3e6c4070 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Freescale Layerscape MC I/O wrapper + * Data Path Buffer Pool API + * Contains initialization APIs and runtime control APIs for DPBP * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ -/*! - * @file fsl_dpbp.h - * @brief Data Path Buffer Pool API + * Copyright 2017-2023 NXP */ + #ifndef __FSL_DPBP_H #define __FSL_DPBP_H @@ -27,160 +26,50 @@ #define DPBP_CMDID_DISABLE 0x0031 #define DPBP_CMDID_GET_ATTR 0x0041 #define DPBP_CMDID_RESET 0x0051 -#define DPBP_CMDID_IS_ENABLED 0x0061 -/* cmd, param, offset, width, type, arg_name */ -#define DPBP_CMD_OPEN(cmd, dpbp_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id) +#pragma pack(push, 1) + +struct dpbp_cmd_open { + __le32 dpbp_id; +}; -/* cmd, param, offset, width, type, arg_name */ -#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \ - MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ -} while (0) +struct dpbp_cmd_destroy { + __le32 object_id; +}; -/* Data Path Buffer Pool API - * Contains initialization APIs and runtime control APIs for DPBP - */ +struct dpbp_rsp_get_attributes { + __le16 pad; + __le16 bpid; + __le32 id; +}; + +#pragma pack(pop) struct fsl_mc_io; -/** - * dpbp_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpbp_id: DPBP unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpbp_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpbp_id, - uint16_t *token); +int dpbp_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpbp_id, u16 *token); -/** - * dpbp_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpbp_cfg - Structure representing DPBP configuration * @options: place holder */ struct dpbp_cfg { - uint32_t options; + u32 options; }; -/** - * dpbp_create() - Create the DPBP object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @token: Returned token; use in subsequent API calls - * - * Create the DPBP object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpbp_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpbp_cfg *cfg, - uint32_t *obj_id); +int dpbp_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpbp_cfg *cfg, u32 *obj_id); -/** - * dpbp_destroy() - Destroy the DPBP object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; error code otherwise. - */ -int dpbp_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpbp_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 obj_id); -/** - * dpbp_enable() - Enable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpbp_disable() - Disable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); - -/** - * dpbp_is_enabled() - Check if the DPBP is enabled. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * @en: Returns '1' if object is enabled; '0' otherwise - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_is_enabled(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *en); - -/** - * dpbp_reset() - Reset the DPBP, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpbp_attr - Structure representing DPBP attributes @@ -190,40 +79,14 @@ int dpbp_reset(struct fsl_mc_io *mc_io, * acquire/release operations on buffers */ struct dpbp_attr { - uint32_t id; - uint16_t bpid; + u32 id; + u16 bpid; }; -/** - * dpbp_get_attributes - Retrieve DPBP attributes. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpbp_attr *attr); - -/** - * dpbp_get_api_version - Retrieve DPBP Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPBP major version - * @minor_ver: DPBP minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpbp_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpbp_attr *attr); -/** @} */ +int dpbp_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* __FSL_DPBP_H */ diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 7788e1962e..375590fd97 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPIO_H @@ -21,31 +21,53 @@ #define DPIO_CMDID_ENABLE 0x0021 #define DPIO_CMDID_DISABLE 0x0031 #define DPIO_CMDID_GET_ATTR 0x0041 -#define DPIO_CMDID_RESET 0x0051 - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_CMD_OPEN(cmd, dpio_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_CMD_CREATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \ - cfg->channel_mode);\ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_RSP_GET_ATTR(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ - MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\ - MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ - MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ -} while (0) + +/* Macros for accessing command fields smaller than 1byte */ +#define DPIO_MASK(field) \ + GENMASK(DPIO_##field##_SHIFT + DPIO_##field##_SIZE - 1, \ + DPIO_##field##_SHIFT) +#define dpio_set_field(var, field, val) \ + ((var) |= (((val) << DPIO_##field##_SHIFT) & DPIO_MASK(field))) +#define dpio_get_field(var, field) \ + (((var) & DPIO_MASK(field)) >> DPIO_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpio_cmd_open { + __le32 dpio_id; +}; + +#define DPIO_CHANNEL_MODE_SHIFT 0 +#define DPIO_CHANNEL_MODE_SIZE 2 + +struct dpio_cmd_create { + __le16 pad1; + /* from LSB: channel_mode:2 */ + u8 channel_mode; + u8 pad2; + u8 num_priorities; +}; + +struct dpio_cmd_destroy { + __le32 dpio_id; +}; + +#define DPIO_ATTR_CHANNEL_MODE_SHIFT 0 +#define DPIO_ATTR_CHANNEL_MODE_SIZE 4 + +struct dpio_rsp_get_attr { + __le32 id; + __le16 qbman_portal_id; + u8 num_priorities; + /* from LSB: channel_mode:4 */ + u8 channel_mode; + __le64 qbman_portal_ce_offset; + __le64 qbman_portal_ci_offset; + __le32 qbman_version; + __le32 pad; + __le32 clk; +}; + +#pragma pack(pop) /* Data Path I/O Portal API * Contains initialization APIs and runtime control APIs for DPIO @@ -53,44 +75,15 @@ do { \ struct fsl_mc_io; -/** - * dpio_open() - Open a control session for the specified object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpio_id: DPIO unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpio_create() function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint32_t dpio_id, - uint16_t *token); +int dpio_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpio_id, + u16 *token); -/** - * dpio_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * enum dpio_channel_mode - DPIO notification channel mode - * @DPIO_NO_CHANNEL: No support for notification channel - * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a + * @DPIO_NO_CHANNEL: No support for notification channel + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a * dedicated channel in the DPIO; user should point the queue's * destination in the relevant interface to this DPIO */ @@ -101,143 +94,52 @@ enum dpio_channel_mode { /** * struct dpio_cfg - Structure representing DPIO configuration - * @channel_mode: Notification channel mode - * @num_priorities: Number of priorities for the notification channel (1-8); + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' */ struct dpio_cfg { - enum dpio_channel_mode channel_mode; - uint8_t num_priorities; + enum dpio_channel_mode channel_mode; + u8 num_priorities; }; -/** - * dpio_create() - Create the DPIO object. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPIO object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpio_open() function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpio_cfg *cfg, - uint32_t *obj_id); - -/** - * dpio_destroy() - Destroy the DPIO object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: Object ID of DPIO - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpio_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpio_cfg *cfg, u32 *obj_id); -/** - * dpio_enable() - Enable the DPIO, allow I/O portal operations. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); -/** - * dpio_disable() - Disable the DPIO, stop any I/O portal operation. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpio_reset() - Reset the DPIO, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpio_attr - Structure representing DPIO attributes - * @id: DPIO object ID - * @version: DPIO version - * @qbman_portal_ce_offset: offset of the software portal cache-enabled area - * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area - * @qbman_portal_id: Software portal ID - * @channel_mode: Notification channel mode - * @num_priorities: Number of priorities for the notification channel (1-8); - * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' - * @qbman_version: QBMAN version + * @id: DPIO object ID + * @qbman_portal_ce_offset: Offset of the software portal cache-enabled area + * @qbman_portal_ci_offset: Offset of the software portal + * cache-inhibited area + * @qbman_portal_id: Software portal ID + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification + * channel (1-8); relevant only if + * 'channel_mode = DPIO_LOCAL_CHANNEL' + * @qbman_version: QBMAN version */ struct dpio_attr { - uint32_t id; - uint64_t qbman_portal_ce_offset; - uint64_t qbman_portal_ci_offset; - uint16_t qbman_portal_id; + int id; + u64 qbman_portal_ce_offset; + u64 qbman_portal_ci_offset; + u16 qbman_portal_id; enum dpio_channel_mode channel_mode; - uint8_t num_priorities; - uint32_t qbman_version; + u8 num_priorities; + u32 qbman_version; + u32 clk; }; -/** - * dpio_get_attributes() - Retrieve DPIO attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpio_attr *attr); - -/** - * dpio_get_api_version - Retrieve DPIO Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPIO major version - * @minor_ver: DPIO minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpio_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpio_attr *attr); +int dpio_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPIO_H */ diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 1cea123a31..a8e9e4684a 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -21,74 +21,59 @@ #define DPMAC_CMDID_DESTROY 0x98c1 #define DPMAC_CMDID_GET_API_VERSION 0xa0c1 -#define DPMAC_CMDID_GET_ATTR 0x0041 #define DPMAC_CMDID_RESET 0x0051 -#define DPMAC_CMDID_MDIO_READ 0x0c01 -#define DPMAC_CMDID_MDIO_WRITE 0x0c11 -#define DPMAC_CMDID_GET_LINK_CFG 0x0c21 #define DPMAC_CMDID_SET_LINK_STATE 0x0c31 #define DPMAC_CMDID_GET_COUNTER 0x0c41 -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_CREATE(cmd, cfg) \ - MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->mac_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_OPEN(cmd, dpmac_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ - MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ - MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ - MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ - MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_MDIO_READ(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_MDIO_READ(cmd, data) \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ - MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ - MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_GET_COUNTER(cmd, type) \ - MC_CMD_OP(cmd, 1, 0, 64, enum dpmac_counter, type) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_COUNTER(cmd, counter) \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) +/* Macros for accessing command fields smaller than 1byte */ +#define DPMAC_MASK(field) \ + GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \ + DPMAC_##field##_SHIFT) +#define dpmac_set_field(var, field, val) \ + ((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field))) +#define dpmac_get_field(var, field) \ + (((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpmac_cmd_open { + __le32 dpmac_id; +}; + +struct dpmac_cmd_create { + __le32 mac_id; +}; + +struct dpmac_cmd_destroy { + __le32 dpmac_id; +}; + +#define DPMAC_STATE_SIZE 1 +#define DPMAC_STATE_SHIFT 0 +#define DPMAC_STATE_VALID_SIZE 1 +#define DPMAC_STATE_VALID_SHIFT 1 + +struct dpmac_cmd_set_link_state { + __le64 options; + __le32 rate; + __le32 pad; + /* only least significant bit is valid */ + u8 up; + u8 pad0[7]; + __le64 supported; + __le64 advertising; +}; + +struct dpmac_cmd_get_counter { + u8 type; +}; + +struct dpmac_rsp_get_counter { + __le64 pad; + __le64 counter; +}; + +#pragma pack(pop) /* Data Path MAC API * Contains initialization APIs and runtime control APIs for DPMAC @@ -96,42 +81,27 @@ do { \ struct fsl_mc_io; -/** - * dpmac_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpmac_id: DPMAC unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpmac_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpmac_id, - uint16_t *token); +int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token); + +int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** - * dpmac_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. + * struct dpmac_cfg - Structure representing DPMAC configuration + * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, + * the MAC IDs are continuous. + * For example: 2 WRIOPs, 16 MACs in each: + * MAC IDs for the 1st WRIOP: 1-16, + * MAC IDs for the 2nd WRIOP: 17-32. */ -int dpmac_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +struct dpmac_cfg { + int mac_id; +}; + +int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpmac_cfg *cfg, u32 *obj_id); + +int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); /** * enum dpmac_link_type - DPMAC link type @@ -171,60 +141,6 @@ enum dpmac_eth_if { DPMAC_ETH_IF_XFI }; -/** - * struct dpmac_cfg - Structure representing DPMAC configuration - * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, - * the MAC IDs are continuous. - * For example: 2 WRIOPs, 16 MACs in each: - * MAC IDs for the 1st WRIOP: 1-16, - * MAC IDs for the 2nd WRIOP: 17-32. - */ -struct dpmac_cfg { - int mac_id; -}; - -/** - * dpmac_create() - Create the DPMAC object. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPMAC object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpmac_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpmac_cfg *cfg, - uint32_t *obj_id); - -/** - * dpmac_destroy() - Destroy the DPMAC object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: DPMAC object id - * - * Return: '0' on Success; error code otherwise. - */ -int dpmac_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); - /* DPMAC IRQ Index and Events */ /* IRQ index */ @@ -248,65 +164,9 @@ struct dpmac_attr { int phy_id; enum dpmac_link_type link_type; enum dpmac_eth_if eth_if; - uint32_t max_rate; + u32 max_rate; }; -/** - * dpmac_get_attributes - Retrieve DPMAC attributes. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_attr *attr); - -/** - * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters - * @phy_addr: MDIO device address - * @reg: Address of the register within the Clause 45 PHY device from which data - * is to be read - * @data: Data read/write from/to MDIO - */ -struct dpmac_mdio_cfg { - uint8_t phy_addr; - uint8_t reg; - uint16_t data; -}; - -/** - * dpmac_mdio_read() - Perform MDIO read transaction - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Structure with MDIO transaction parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_mdio_read(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg); - -/** - * dpmac_mdio_write() - Perform MDIO write transaction - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Structure with MDIO transaction parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_mdio_write(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg); - /* DPMAC link configuration/state options */ /* Enable auto-negotiation */ @@ -319,55 +179,25 @@ int dpmac_mdio_write(struct fsl_mc_io *mc_io, #define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL /** - * struct dpmac_link_cfg - Structure representing DPMAC link configuration - * @rate: Link's rate - in Mbps - * @options: Enable/Disable DPMAC link cfg features (bitmap) - */ -struct dpmac_link_cfg { - uint32_t rate; - uint64_t options; -}; - -/** - * dpmac_get_link_cfg() - Get Ethernet link configuration - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Returned structure with the link configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_cfg *cfg); - -/** * struct dpmac_link_state - DPMAC link configuration request * @rate: Rate in Mbps * @options: Enable/Disable DPMAC link cfg features (bitmap) * @up: Link state + * @state_valid: Ignore/Update the state of the link + * @supported: Speeds capability of the phy (bitmap) + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpmac_link_state { - uint32_t rate; - uint64_t options; - int up; + u32 rate; + u64 options; + int up; + int state_valid; + u64 supported; + u64 advertising; }; -/** - * dpmac_set_link_state() - Set the Ethernet link status - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @link_state: Link state configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_set_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_state *link_state); - +int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpmac_link_state *link_state); /** * enum dpni_counter - DPNI counter types * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad. @@ -412,6 +242,8 @@ int dpmac_set_link_state(struct fsl_mc_io *mc_io, * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including * pause frames. + * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including + * pause frames. */ enum dpmac_counter { DPMAC_CNT_ING_FRAME_64, @@ -440,37 +272,14 @@ enum dpmac_counter { DPMAC_CNT_EGR_BCAST_FRAME, DPMAC_CNT_EGR_UCAST_FRAME, DPMAC_CNT_EGR_ERR_FRAME, - DPMAC_CNT_ING_GOOD_FRAME + DPMAC_CNT_ING_GOOD_FRAME, + DPMAC_CNT_EGR_GOOD_FRAME, }; -/** - * dpmac_get_counter() - Read a specific DPMAC counter - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @type: The requested counter - * @counter: Returned counter value - * - * Return: The requested counter; '0' otherwise. - */ -int dpmac_get_counter(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpmac_counter type, - uint64_t *counter); -/** - * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPMAC major version - * @minor_ver: DPMAC minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_api_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t *major_ver, - uint16_t *minor_ver); +int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpmac_counter type, u64 *counter); + +int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* __FSL_DPMAC_H */ diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h index 2148601e8a..5dfc9ecc42 100644 --- a/include/fsl-mc/fsl_dpmng.h +++ b/include/fsl-mc/fsl_dpmng.h @@ -30,17 +30,6 @@ struct mc_version { uint32_t revision; }; -/** - * mc_get_version() - Retrieves the Management Complex firmware - * version information - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @mc_ver_info: Returned version information structure - * - * Return: '0' on Success; Error code otherwise. - */ -int mc_get_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - struct mc_version *mc_ver_info); +int mc_get_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, struct mc_version *mc_ver_info); #endif /* __FSL_DPMNG_H */ diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index e5e7338192..9bc475475d 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPNI_H #define _FSL_DPNI_H @@ -24,303 +24,243 @@ #define DPNI_CMDID_SET_POOLS 0x2002 #define DPNI_CMDID_SET_BUFFER_LAYOUT 0x2651 -#define DPNI_CMDID_GET_BUFFER_LAYOUT 0x2641 -#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B1 #define DPNI_CMDID_GET_QDID 0x2101 #define DPNI_CMDID_GET_TX_DATA_OFFSET 0x2121 #define DPNI_CMDID_GET_LINK_STATE 0x2151 #define DPNI_CMDID_SET_LINK_CFG 0x21A1 -#define DPNI_CMDID_SET_PRIM_MAC 0x2241 -#define DPNI_CMDID_GET_PRIM_MAC 0x2251 #define DPNI_CMDID_ADD_MAC_ADDR 0x2261 -#define DPNI_CMDID_REMOVE_MAC_ADDR 0x2271 #define DPNI_CMDID_GET_STATISTICS 0x25D1 -#define DPNI_CMDID_RESET_STATISTICS 0x25E1 #define DPNI_CMDID_GET_QUEUE 0x25F1 #define DPNI_CMDID_SET_QUEUE 0x2601 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE 0x2661 -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_OPEN(cmd, dpni_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_PREP_CFG(param, cfg) \ -do { \ - MC_PREP_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ - MC_PREP_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ - MC_PREP_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ - MC_PREP_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ - MC_PREP_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ - MC_PREP_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ - MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_EXT_CFG(param, cfg) \ -do { \ - MC_EXT_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ - MC_EXT_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ - MC_EXT_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ - MC_EXT_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ - MC_EXT_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ - MC_EXT_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ - MC_EXT_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_CREATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->adv.options); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->adv.num_queues); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->adv.num_tcs); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->adv.mac_entries); \ - MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->adv.vlan_entries); \ - MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->adv.qos_entries); \ - MC_CMD_OP(cmd, 1, 32, 16, uint8_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_POOLS(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ - MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ - MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ - MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ - MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ - MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ - MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ - MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ - MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ - MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ - MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ - MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ - MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\ - MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \ - MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\ - MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \ - MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\ - MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \ - MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\ - MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \ - MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\ - MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \ - MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\ - MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \ - MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_ATTR(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->options);\ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_num_queues); \ - MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_num_tcs); \ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->max_mac_entries); \ - MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->max_vlan_entries); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->max_qos_entries); \ - MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fs_entries); \ - MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_qos_key_size); \ - MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_fs_key_size); \ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->wriop_version); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ - MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ - MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, queue); \ - MC_CMD_OP(cmd, 1, 0, 16, uint16_t, layout->private_data_size); \ - MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \ - MC_CMD_OP(cmd, 0, 48, 1, int, layout->pass_timestamp); \ - MC_CMD_OP(cmd, 0, 49, 1, int, layout->pass_parser_result); \ - MC_CMD_OP(cmd, 0, 50, 1, int, layout->pass_frame_status); \ - MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \ - MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_QDID(cmd, qdid) \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ - MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_LINK_STATE(cmd, state) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ -} while (0) - -#define DPNI_RSP_GET_QUEUE(cmd, queue) \ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_RSP_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ - MC_RSP_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ - MC_RSP_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ - MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ - MC_RSP_OP(cmd, 4, 0, 32, uint32_t, (queue)->fqid); \ - MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \ -} while (0) - -#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, (queue)->options); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_CMD_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ - MC_CMD_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ - MC_CMD_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_CMD_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ - MC_CMD_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_GET_STATISTICS(cmd, page) \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_STATISTICS(cmd, stat) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \ - MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \ - MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \ - MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \ - MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \ -} while (0) - -enum net_prot { - NET_PROT_NONE = 0, - NET_PROT_PAYLOAD, - NET_PROT_ETH, - NET_PROT_VLAN, - NET_PROT_IPV4, - NET_PROT_IPV6, - NET_PROT_IP, - NET_PROT_TCP, - NET_PROT_UDP, - NET_PROT_UDP_LITE, - NET_PROT_IPHC, - NET_PROT_SCTP, - NET_PROT_SCTP_CHUNK_DATA, - NET_PROT_PPPOE, - NET_PROT_PPP, - NET_PROT_PPPMUX, - NET_PROT_PPPMUX_SUBFRM, - NET_PROT_L2TPV2, - NET_PROT_L2TPV3_CTRL, - NET_PROT_L2TPV3_SESS, - NET_PROT_LLC, - NET_PROT_LLC_SNAP, - NET_PROT_NLPID, - NET_PROT_SNAP, - NET_PROT_MPLS, - NET_PROT_IPSEC_AH, - NET_PROT_IPSEC_ESP, - NET_PROT_UDP_ENC_ESP, /* RFC 3948 */ - NET_PROT_MACSEC, - NET_PROT_GRE, - NET_PROT_MINENCAP, - NET_PROT_DCCP, - NET_PROT_ICMP, - NET_PROT_IGMP, - NET_PROT_ARP, - NET_PROT_CAPWAP_DATA, - NET_PROT_CAPWAP_CTRL, - NET_PROT_RFC2684, - NET_PROT_ICMPV6, - NET_PROT_FCOE, - NET_PROT_FIP, - NET_PROT_ISCSI, - NET_PROT_GTP, - NET_PROT_USER_DEFINED_L2, - NET_PROT_USER_DEFINED_L3, - NET_PROT_USER_DEFINED_L4, - NET_PROT_USER_DEFINED_L5, - NET_PROT_USER_DEFINED_SHIM1, - NET_PROT_USER_DEFINED_SHIM2, - - NET_PROT_DUMMY_LAST +/* Macros for accessing command fields smaller than 1byte */ +#define DPNI_MASK(field) \ + GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \ + DPNI_##field##_SHIFT) +#define dpni_set_field(var, field, val) \ + ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field))) +#define dpni_get_field(var, field) \ + (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpni_cmd_open { + __le32 dpni_id; }; +struct dpni_cmd_create { + __le32 options; + u8 num_queues; + u8 num_tcs; + u8 mac_filter_entries; + u8 num_channels; + u8 vlan_filter_entries; + u8 pad2; + u8 qos_entries; + u8 pad3; + __le16 fs_entries; + u8 num_rx_tcs; + u8 pad4; + u8 num_cgs; + __le16 num_opr; + u8 dist_key_size; +}; + +struct dpni_cmd_destroy { + __le32 dpni_id; +}; + +#define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) + +struct dpni_cmd_pool { + __le16 dpbp_id; + u8 priority_mask; + u8 pad; +}; + +struct dpni_cmd_set_pools { + u8 num_dpbp; + u8 backup_pool_mask; + u8 pad; + u8 pool_options; + struct dpni_cmd_pool pool[8]; + __le16 buffer_size[8]; +}; + +struct dpni_rsp_get_attr { + /* response word 0 */ + __le32 options; + u8 num_queues; + u8 num_rx_tcs; + u8 mac_filter_entries; + u8 num_tx_tcs; + /* response word 1 */ + u8 vlan_filter_entries; + u8 num_channels; + u8 qos_entries; + u8 pad2; + __le16 fs_entries; + __le16 num_opr; + /* response word 2 */ + u8 qos_key_size; + u8 fs_key_size; + __le16 wriop_version; + u8 num_cgs; +}; + +/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation + * buffer layouts, but they all share the same parameters. + * If one of the functions changes, below structure needs to be split. + */ + +#define DPNI_PASS_TS_SHIFT 0 +#define DPNI_PASS_TS_SIZE 1 +#define DPNI_PASS_PR_SHIFT 1 +#define DPNI_PASS_PR_SIZE 1 +#define DPNI_PASS_FS_SHIFT 2 +#define DPNI_PASS_FS_SIZE 1 +#define DPNI_PASS_SWO_SHIFT 3 +#define DPNI_PASS_SWO_SIZE 1 + +struct dpni_cmd_set_buffer_layout { + /* cmd word 0 */ + u8 qtype; + u8 pad0[3]; + __le16 options; + /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ + u8 flags; + u8 pad1; + /* cmd word 1 */ + __le16 private_data_size; + __le16 data_align; + __le16 head_room; + __le16 tail_room; +}; + +struct dpni_cmd_get_qdid { + u8 qtype; +}; + +struct dpni_rsp_get_qdid { + __le16 qdid; +}; + +struct dpni_rsp_get_tx_data_offset { + __le16 data_offset; +}; + +struct dpni_cmd_set_link_cfg { + __le64 pad0; + __le32 rate; + __le32 pad1; + __le64 options; + __le64 advertising; +}; + +#define DPNI_LINK_STATE_SHIFT 0 +#define DPNI_LINK_STATE_SIZE 1 +#define DPNI_STATE_VALID_SHIFT 1 +#define DPNI_STATE_VALID_SIZE 1 + +struct dpni_rsp_get_link_state { + __le32 pad0; + /* from LSB: up:1 */ + u8 flags; + u8 pad1[3]; + __le32 rate; + __le32 pad2; + __le64 options; + __le64 supported; + __le64 advertising; +}; + +struct dpni_cmd_add_mac_addr { + u8 flags; + u8 pad; + u8 mac_addr[6]; + u8 tc_id; + u8 fq_id; +}; + +struct dpni_cmd_get_queue { + u8 qtype; + u8 tc; + u8 index; + u8 channel_id; +}; + +#define DPNI_DEST_TYPE_SHIFT 0 +#define DPNI_DEST_TYPE_SIZE 4 +#define DPNI_CGID_VALID_SHIFT 5 +#define DPNI_CGID_VALID_SIZE 1 +#define DPNI_STASH_CTRL_SHIFT 6 +#define DPNI_STASH_CTRL_SIZE 1 +#define DPNI_HOLD_ACTIVE_SHIFT 7 +#define DPNI_HOLD_ACTIVE_SIZE 1 + +struct dpni_rsp_get_queue { + /* response word 0 */ + __le64 pad0; + /* response word 1 */ + __le32 dest_id; + __le16 pad1; + u8 dest_prio; + /* From LSB: dest_type:4, pad:1, cgid_valid:1, flc_stash_ctrl:1, hold_active:1 */ + u8 flags; + /* response word 2 */ + __le64 flc; + /* response word 3 */ + __le64 user_context; + /* response word 4 */ + __le32 fqid; + __le16 qdbin; + __le16 pad2; + /* response word 5*/ + u8 cgid; +}; + +struct dpni_cmd_set_queue { + /* cmd word 0 */ + u8 qtype; + u8 tc; + u8 index; + u8 options; + __le32 pad0; + /* cmd word 1 */ + __le32 dest_id; + __le16 pad1; + u8 dest_prio; + u8 flags; + /* cmd word 2 */ + __le64 flc; + /* cmd word 3 */ + __le64 user_context; + /* cmd word 4 */ + u8 cgid; + u8 channel_id; +}; + +struct dpni_tx_confirmation_mode { + u8 ceetm_ch_idx; + u8 pad1; + __le16 pad2; + u8 confirmation_mode; +}; + +struct dpni_cmd_get_statistics { + u8 page_number; + __le16 param; +}; + +struct dpni_rsp_get_statistics { + __le64 counter[7]; +}; + +#pragma pack(pop) + /** * Data Path Network Interface API * Contains initialization APIs and runtime control APIs for DPNI @@ -336,50 +276,17 @@ struct fsl_mc_io; #define DPNI_MAX_DPBP 8 /* All traffic classes considered; see dpni_set_rx_flow() */ -#define DPNI_ALL_TCS (uint8_t)(-1) +#define DPNI_ALL_TCS (u8)(-1) /* All flows within traffic class considered; see dpni_set_rx_flow() */ -#define DPNI_ALL_TC_FLOWS (uint16_t)(-1) +#define DPNI_ALL_TC_FLOWS (u16)(-1) /* Generate new flow ID; see dpni_set_tx_flow() */ -#define DPNI_NEW_FLOW_ID (uint16_t)(-1) +#define DPNI_NEW_FLOW_ID (u16)(-1) /* use for common tx-conf queue; see dpni_set_tx_conf_<x>() */ -#define DPNI_COMMON_TX_CONF (uint16_t)(-1) +#define DPNI_COMMON_TX_CONF (u16)(-1) -/** - * dpni_open() - Open a control session for the specified object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpni_id: DPNI unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpni_create() function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpni_id, - uint16_t *token); +int dpni_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpni_id, u16 *token); -/** - * dpni_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /* DPNI configuration options */ @@ -442,57 +349,84 @@ enum dpni_queue_type { DPNI_QUEUE_RX_ERR, }; -struct dpni_cfg { - uint8_t mac_addr[6]; - struct { - uint32_t options; - uint16_t fs_entries; - uint8_t num_queues; - uint8_t num_tcs; - uint8_t mac_entries; - uint8_t vlan_entries; - uint8_t qos_entries; - } adv; -}; - /** - * struct dpni_extended_cfg - Structure representing extended DPNI configuration - * @tc_cfg: TCs configuration - * @ipr_cfg: IP reassembly configuration + * struct dpni_cfg - Structure representing DPNI configuration + * @options: Any combination of the following options: + * DPNI_OPT_TX_FRM_RELEASE + * DPNI_OPT_NO_MAC_FILTER + * DPNI_OPT_HAS_POLICING + * DPNI_OPT_SHARED_CONGESTION + * DPNI_OPT_HAS_KEY_MASKING + * DPNI_OPT_NO_FS + * DPNI_OPT_SINGLE_SENDER + * DPNI_OPT_STASHING_DIS + * @fs_entries: Number of entries in the flow steering table. + * This table is used to select the ingress queue for + * ingress traffic, targeting a GPP core or another. + * In addition it can be used to discard traffic that + * matches the set rule. It is either an exact match table + * or a TCAM table, depending on DPNI_OPT_ HAS_KEY_MASKING + * bit in OPTIONS field. This field is ignored if + * DPNI_OPT_NO_FS bit is set in OPTIONS field. Otherwise, + * value 0 defaults to 64. Maximum supported value is 1024. + * Note that the total number of entries is limited on the + * SoC to as low as 512 entries if TCAM is used. + * @vlan_filter_entries: Number of entries in the VLAN address filtering + * table. This is an exact match table used to filter + * ingress traffic based on VLAN IDs. Value 0 disables VLAN + * filtering. Maximum supported value is 16. + * @mac_filter_entries: Number of entries in the MAC address filtering + * table. This is an exact match table and allows both + * unicast and multicast entries. The primary MAC address + * of the network interface is not part of this table, + * this contains only entries in addition to it. This + * field is ignored if DPNI_OPT_ NO_MAC_FILTER is set in + * OPTIONS field. Otherwise, value 0 defaults to 80. + * Maximum supported value is 80. + * @num_queues: Number of Tx and Rx queues used for traffic + * distribution. This is orthogonal to QoS and is only + * used to distribute traffic to multiple GPP cores. + * This configuration affects the number of Tx queues + * (logical FQs, all associated with a single CEETM queue), + * Rx queues and Tx confirmation queues, if applicable. + * Value 0 defaults to one queue. Maximum supported value + * is 8. + * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI. + * TCs can have different priority levels for the purpose + * of Tx scheduling (see DPNI_SET_TX_PRIORITIES), different + * BPs (DPNI_ SET_POOLS), policers. There are dedicated QM + * queues for traffic classes (including class queues on + * Tx). Value 0 defaults to one TC. Maximum supported value + * is 16. There are maximum 16 TCs for Tx and 8 TCs for Rx. + * When num_tcs>8 Tx will use this value but Rx will have + * only 8 traffic classes. + * @num_rx_tcs: if set to other value than zero represents number + * of TCs used for Rx. Maximum value is 8. If set to zero the + * number of Rx TCs will be initialized with the value provided + * in num_tcs parameter. + * @qos_entries: Number of entries in the QoS classification table. This + * table is used to select the TC for ingress traffic. It + * is either an exact match or a TCAM table, depending on + * DPNI_OPT_ HAS_KEY_MASKING bit in OPTIONS field. This + * field is ignored if the DPNI has a single TC. Otherwise, + * a value of 0 defaults to 64. Maximum supported value + * is 64. + * @num_channels: Number of egress channels used by this dpni object. If + * set to zero the dpni object will use a single CEETM channel. */ -struct dpni_extended_cfg { - /** - * struct tc_cfg - TC configuration - * @max_dist: Maximum distribution size for Rx traffic class; - * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, - * 112,128,192,224,256,384,448,512,768,896,1024; - * value '0' will be treated as '1'. - * other unsupported values will be round down to the nearest - * supported value. - * @max_fs_entries: Maximum FS entries for Rx traffic class; - * '0' means no support for this TC; - */ - struct { - uint16_t max_dist; - uint16_t max_fs_entries; - } tc_cfg[DPNI_MAX_TC]; - /** - * struct ipr_cfg - Structure representing IP reassembly configuration - * @max_reass_frm_size: Maximum size of the reassembled frame - * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments - * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments - * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly - * process - * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly - * process - */ - struct { - uint16_t max_reass_frm_size; - uint16_t min_frag_size_ipv4; - uint16_t min_frag_size_ipv6; - uint16_t max_open_frames_ipv4; - uint16_t max_open_frames_ipv6; - } ipr_cfg; +struct dpni_cfg { + u32 options; + u16 fs_entries; + u8 vlan_filter_entries; + u8 mac_filter_entries; + u8 num_queues; + u8 num_tcs; + u8 num_rx_tcs; + u8 qos_entries; + u8 num_cgs; + u16 num_opr; + u8 dist_key_size; + u8 num_channels; }; /** @@ -503,249 +437,108 @@ struct dpni_extended_cfg { * This function has to be called before dpni_create() */ int dpni_prepare_cfg(const struct dpni_cfg *cfg, - uint8_t *cfg_buf); -/** - * dpni_create() - Create the DPNI object - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPNI object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpni_open() function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpni_cfg *cfg, - uint32_t *obj_id); + u8 *cfg_buf); -/** - * dpni_destroy() - Destroy the DPNI object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Return: '0' on Success; error code otherwise. - */ -int dpni_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpni_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpni_cfg *cfg, u32 *obj_id); + +int dpni_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); /** * struct dpni_pools_cfg - Structure representing buffer pools configuration - * @num_dpbp: Number of DPBPs - * @pools: Array of buffer pools parameters; The number of valid entries - * must match 'num_dpbp' value + * @num_dpbp: Number of DPBPs + * @pool_options: Buffer assignment options + * This field is a combination of DPNI_POOL_ASSOC_flags + * @pools: Array of buffer pools parameters; The number of valid entries + * must match 'num_dpbp' value + * @pools.dpbp_id: DPBP object ID + * @pools.priority: Priority mask that indicates TC's used with this buffer. + * I set to 0x00 MC will assume value 0xff. + * @pools.buffer_size: Buffer size + * @pools.backup_pool: Backup pool */ + +#define DPNI_POOL_ASSOC_QPRI 0 +#define DPNI_POOL_ASSOC_QDBIN 1 + struct dpni_pools_cfg { - uint8_t num_dpbp; - /** - * struct pools - Buffer pools parameters - * @dpbp_id: DPBP object ID - * @buffer_size: Buffer size - * @backup_pool: Backup pool - */ + u8 num_dpbp; + u8 pool_options; struct { int dpbp_id; - uint16_t buffer_size; + u8 priority_mask; + u16 buffer_size; int backup_pool; } pools[DPNI_MAX_DPBP]; }; -/** - * dpni_set_pools() - Set buffer pools configuration - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Buffer pools configuration - * - * mandatory for DPNI operation - * warning:Allowed only when DPNI is disabled - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_pools(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_pools_cfg *cfg); +int dpni_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dpni_pools_cfg *cfg); -/** - * dpni_enable() - Enable the DPNI, allow sending and receiving frames. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpni_disable() - Disable the DPNI, stop sending and receiving frames. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); - -/** - * dpni_reset() - Reset the DPNI, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpni_attr - Structure representing DPNI attributes - * @options: Mask of available options; reflects the value as was given in - * object's creation - * @max_num_queues: Number of queues available (for both Tx and Rx) - * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx) - * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx) - * @max_unicast_filters: Maximum number of unicast filters - * @max_multicast_filters: Maximum number of multicast filters - * @max_vlan_entries: Maximum number of VLAN filters - * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table - * @max_fs_entries: declares the maximum entries in flow steering table - * @max_qos_key_size: Maximum key size for the QoS look-up - * @max_fs_key_size: Maximum key size for the flow steering - * @wriop_version: Indicates revision of WRIOP hardware block + * @options: Any combination of the following options: + * DPNI_OPT_TX_FRM_RELEASE + * DPNI_OPT_NO_MAC_FILTER + * DPNI_OPT_HAS_POLICING + * DPNI_OPT_SHARED_CONGESTION + * DPNI_OPT_HAS_KEY_MASKING + * DPNI_OPT_NO_FS + * DPNI_OPT_STASHING_DIS + * @num_queues: Number of Tx and Rx queues used for traffic distribution. + * @num_rx_tcs: Number of RX traffic classes (TCs), reserved for the DPNI. + * @num_tx_tcs: Number of TX traffic classes (TCs), reserved for the DPNI. + * @mac_filter_entries: Number of entries in the MAC address filtering + * table. + * @vlan_filter_entries: Number of entries in the VLAN address filtering + * table. + * @qos_entries: Number of entries in the QoS classification table. + * @fs_entries: Number of entries in the flow steering table. + * @qos_key_size: Size, in bytes, of the QoS look-up key. Defining a key larger + * than this when adding QoS entries will result + * in an error. + * @fs_key_size: Size, in bytes, of the flow steering look-up key. Defining a + * key larger than this when composing the hash + FS key + * will result in an error. + * @wriop_version: Version of WRIOP HW block. + * The 3 version values are stored on 6, 5, 5 bits + * respectively. + * Values returned: + * - 0x400 - WRIOP version 1.0.0, used on LS2080 and + * variants, + * - 0x421 - WRIOP version 1.1.1, used on LS2088 and + * variants, + * - 0x422 - WRIOP version 1.1.2, used on LS1088 and + * variants. + * - 0xC00 - WRIOP version 3.0.0, used on LX2160 and + * variants. */ struct dpni_attr { - uint32_t id; - uint32_t options; - uint8_t max_num_queues; - uint8_t max_num_tcs; - uint8_t max_mac_entries; - uint8_t max_vlan_entries; - uint8_t max_qos_entries; - uint16_t max_fs_entries; - uint8_t max_qos_key_size; - uint8_t max_fs_key_size; - uint16_t wriop_version; -}; - -/** - * dpni_get_attributes() - Retrieve DPNI attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @attr: Object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_attr *attr); - -/** - * dpni_extract_cfg() - extract the parameters - * @cfg: cfg structure - * @cfg_buf: 256 bytes of DMA-able memory - * - * This function has to be called after dpni_get_attributes() - */ -int dpni_extract_cfg(struct dpni_cfg *cfg, - const uint8_t *cfg_buf); - -/** - * DPNI errors - */ - -/** - * Extract out of frame header error - */ -#define DPNI_ERROR_EOFHE 0x00020000 -/** - * Frame length error - */ -#define DPNI_ERROR_FLE 0x00002000 -/** - * Frame physical error - */ -#define DPNI_ERROR_FPE 0x00001000 -/** - * Parsing header error - */ -#define DPNI_ERROR_PHE 0x00000020 -/** - * Parser L3 checksum error - */ -#define DPNI_ERROR_L3CE 0x00000004 -/** - * Parser L3 checksum error - */ -#define DPNI_ERROR_L4CE 0x00000001 - -/** - * enum dpni_error_action - Defines DPNI behavior for errors - * @DPNI_ERROR_ACTION_DISCARD: Discard the frame - * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow - * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue - */ -enum dpni_error_action { - DPNI_ERROR_ACTION_DISCARD = 0, - DPNI_ERROR_ACTION_CONTINUE = 1, - DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 + u32 options; + u8 num_queues; + u8 num_rx_tcs; + u8 num_tx_tcs; + u8 mac_filter_entries; + u8 vlan_filter_entries; + u8 qos_entries; + u16 fs_entries; + u16 num_opr; + u8 qos_key_size; + u8 fs_key_size; + u16 wriop_version; + u8 num_cgs; + u8 num_channels; }; -/** - * struct dpni_error_cfg - Structure representing DPNI errors treatment - * @errors: Errors mask; use 'DPNI_ERROR__<X> - * @error_action: The desired action for the errors mask - * @set_frame_annotation: Set to '1' to mark the errors in frame annotation - * status (FAS); relevant only for the non-discard action - */ -struct dpni_error_cfg { - uint32_t errors; - enum dpni_error_action error_action; - int set_frame_annotation; -}; - -/** - * dpni_set_errors_behavior() - Set errors behavior - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Errors configuration - * - * this function may be called numerous times with different - * error masks - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_error_cfg *cfg); +int dpni_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpni_attr *attr); /* DPNI buffer layout modification options */ @@ -763,93 +556,45 @@ int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, #define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020 /*!< Select to modify the data-tail-room setting */ #define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040 +/* Select to modify the sw-opaque value setting */ +#define DPNI_BUF_LAYOUT_OPT_SW_OPAQUE 0x00000080 +/* Select to disable Scatter Gather and use single buffer */ +#define DPNI_BUF_LAYOUT_OPT_NO_SG 0x00000100 /** * struct dpni_buffer_layout - Structure representing DPNI buffer layout - * @options: Flags representing the suggested modifications to the buffer - * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags - * @pass_timestamp: Pass timestamp value - * @pass_parser_result: Pass parser results - * @pass_frame_status: Pass frame status - * @private_data_size: Size kept for private data (in bytes) - * @data_align: Data alignment - * @data_head_room: Data head room - * @data_tail_room: Data tail room + * @options: Flags representing the suggested modifications to the + * buffer layout; + * Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags + * @pass_timestamp: Pass timestamp value + * @pass_parser_result: Pass parser results + * @pass_frame_status: Pass frame status + * @private_data_size: Size kept for private data (in bytes) + * @data_align: Data alignment + * @data_head_room: Data head room + * @data_tail_room: Data tail room */ struct dpni_buffer_layout { - uint16_t options; + u32 options; int pass_timestamp; int pass_parser_result; int pass_frame_status; - uint16_t private_data_size; - uint16_t data_align; - uint16_t data_head_room; - uint16_t data_tail_room; + int pass_sw_opaque; + u16 private_data_size; + u16 data_align; + u16 data_head_room; + u16 data_tail_room; }; -/** - * dpni_get_buffer_layout() - Retrieve buffer layout attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Returns buffer layout attributes - * @type: DPNI queue type - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type); - -/** - * dpni_set_buffer_layout() - Set buffer layout configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Buffer layout configuration - * @type: DPNI queue type - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Allowed only when DPNI is disabled - */ -int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type); +int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, + const struct dpni_buffer_layout *layout); -/** - * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used - * for enqueue operations - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @qdid: Returned virtual QDID value that should be used as an argument - * in all enqueue operations - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_qdid(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *qdid); +int dpni_get_qdid(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 *qdid); -/** - * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @data_offset: Tx data offset (from start of buffer) - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *data_offset); +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u16 *data_offset); /* Enable auto-negotiation */ #define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL @@ -864,107 +609,44 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, * struct - Structure representing DPNI link configuration * @rate: Rate * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpni_link_cfg { - uint32_t rate; - uint64_t options; + u32 rate; + u64 options; + u64 advertising; }; -/** - * dpni_set_link_cfg() - set the link configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Link configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_link_cfg *cfg); +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dpni_link_cfg *cfg); /** * struct dpni_link_state - Structure representing DPNI link state - * @rate: Rate - * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values - * @up: Link state; '0' for down, '1' for up + * @rate: Rate + * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values + * @up: Link state; '0' for down, '1' for up + * @state_valid: Ignore/Update the state of the link + * @supported: Speeds capability of the phy (bitmap) + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpni_link_state { - uint32_t rate; - uint64_t options; + u32 rate; + u64 options; int up; + int state_valid; + u64 supported; + u64 advertising; }; -/** - * dpni_get_link_state() - Return the link state (either up or down) - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @state: Returned link state; - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_link_state *state); +int dpni_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpni_link_state *state); -/** - * dpni_set_primary_mac_addr() - Set the primary MAC address - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to set as primary address - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); - -/** - * dpni_get_primary_mac_addr() - Get the primary MAC address - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: Returned MAC address - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t mac_addr[6]); +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const u8 mac_addr[6], u8 flags, + u8 tc_id, u8 flow_id); -/** - * dpni_add_mac_addr() - Add MAC address filter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to add - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_add_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); - -/** - * dpni_remove_mac_addr() - Remove MAC address filter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to remove - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); +int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); /** * enum dpni_dest - DPNI destination types @@ -985,137 +667,6 @@ enum dpni_dest { DPNI_DEST_DPCON = 2 }; -/** - * struct dpni_dest_cfg - Structure representing DPNI destination parameters - * @dest_type: Destination type - * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type - * @priority: Priority selection within the DPIO or DPCON channel; valid values - * are 0-1 or 0-7, depending on the number of priorities in that - * channel; not relevant for 'DPNI_DEST_NONE' option - */ -struct dpni_dest_cfg { - enum dpni_dest dest_type; - int dest_id; - uint8_t priority; -}; - -/** - * enum dpni_flc_type - DPNI FLC types - * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value - * @DPNI_FLC_STASH: select the FLC to be used for stash control - */ -enum dpni_flc_type { - DPNI_FLC_USER_DEFINED = 0, - DPNI_FLC_STASH = 1, -}; - -/** - * enum dpni_stash_size - DPNI FLC stashing size - * @DPNI_STASH_SIZE_0B: no stash - * @DPNI_STASH_SIZE_64B: stashes 64 bytes - * @DPNI_STASH_SIZE_128B: stashes 128 bytes - * @DPNI_STASH_SIZE_192B: stashes 192 bytes - */ -enum dpni_stash_size { - DPNI_STASH_SIZE_0B = 0, - DPNI_STASH_SIZE_64B = 1, - DPNI_STASH_SIZE_128B = 2, - DPNI_STASH_SIZE_192B = 3, -}; - -/* DPNI FLC stash options */ - -/* stashes the whole annotation area (up to 192 bytes) */ -#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 - -/** - * struct dpni_flc_cfg - Structure representing DPNI FLC configuration - * @flc_type: FLC type - * @options: Mask of available options; - * use 'DPNI_FLC_STASH_<X>' values - * @frame_data_size: Size of frame data to be stashed - * @flow_context_size: Size of flow context to be stashed - * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED': - * this value will be provided in the frame descriptor - * (FD[FLC]) - * 2. In case flc_type is 'DPNI_FLC_STASH': - * this value will be I/O virtual address of the - * flow-context; - * Must be cacheline-aligned and DMA-able memory - */ -struct dpni_flc_cfg { - enum dpni_flc_type flc_type; - uint32_t options; - enum dpni_stash_size frame_data_size; - enum dpni_stash_size flow_context_size; - uint64_t flow_context; -}; - -/* DPNI queue modification options */ - -/* Select to modify the user's context associated with the queue */ -#define DPNI_QUEUE_OPT_USER_CTX 0x00000001 -/* Select to modify the queue's destination */ -#define DPNI_QUEUE_OPT_DEST 0x00000002 -/** Select to modify the flow-context parameters; - * not applicable for Tx-conf/Err queues as the FD comes from the user - */ -#define DPNI_QUEUE_OPT_FLC 0x00000004 -/* Select to modify the queue's order preservation */ -#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 -/* Select to modify the queue's tail-drop threshold */ -#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 - -/** - * struct dpni_queue_cfg - Structure representing queue configuration - * @options: Flags representing the suggested modifications to the queue; - * Use any combination of 'DPNI_QUEUE_OPT_<X>' flags - * @user_ctx: User context value provided in the frame descriptor of each - * dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' - * is contained in 'options' - * @dest_cfg: Queue destination parameters; - * valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options' - * @flc_cfg: Flow context configuration; in case the TC's distribution - * is either NONE or HASH the FLC's settings of flow#0 are used. - * in the case of FS (flow-steering) the flow's FLC settings - * are used. - * valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options' - * @order_preservation_en: enable/disable order preservation; - * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained - * in 'options' - * @tail_drop_threshold: set the queue's tail drop threshold in bytes; - * '0' value disable the threshold; maximum value is 0xE000000; - * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained - * in 'options' - */ -struct dpni_queue_cfg { - uint32_t options; - uint64_t user_ctx; - struct dpni_dest_cfg dest_cfg; - struct dpni_flc_cfg flc_cfg; - int order_preservation_en; - uint32_t tail_drop_threshold; -}; - -/** - * struct dpni_queue_attr - Structure representing queue attributes - * @user_ctx: User context value provided in the frame descriptor of each - * dequeued frame - * @dest_cfg: Queue destination configuration - * @flc_cfg: Flow context configuration - * @order_preservation_en: enable/disable order preservation - * @tail_drop_threshold: queue's tail drop threshold in bytes; - * @fqid: Virtual fqid value to be used for dequeue operations - */ -struct dpni_queue_attr { - uint64_t user_ctx; - struct dpni_dest_cfg dest_cfg; - struct dpni_flc_cfg flc_cfg; - int order_preservation_en; - uint32_t tail_drop_threshold; - uint32_t fqid; -}; - /* DPNI Tx flow modification options */ /* Select to modify the settings for dedicate Tx confirmation/error */ @@ -1126,21 +677,6 @@ struct dpni_queue_attr { #define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020 /** - * dpni_get_api_version - Retrieve DPNI Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPNI major version - * @minor_ver: DPNI minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); - -/** * enum dpni_confirmation_mode - Defines DPNI options supported for Tx * confirmation * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is @@ -1149,7 +685,7 @@ int dpni_get_api_version(struct fsl_mc_io *mc_io, * confirmation queue * @DPNI_CONF_DISABLE: Tx frames are not confirmed. This must be associated * with proper FD set-up to have buffers release to a Buffer Pool, otherwise - * buffers will be leaked. + * buffers will be leaked */ enum dpni_confirmation_mode { DPNI_CONF_AFFINE, @@ -1157,168 +693,194 @@ enum dpni_confirmation_mode { DPNI_CONF_DISABLE, }; -struct dpni_tx_confirmation_mode { - uint32_t pad; - uint8_t confirmation_mode; -}; +/** + * stashes the whole annotation area (up to 192 bytes) + */ +#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 /** * struct dpni_queue - Queue structure - * @fqid: FQID used for enqueueing to and/or configuration of this specific FQ - * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant - * for Tx queues. - * @flc: FLC value for traffic dequeued from this queue. - * @user_context: User data, presented to the user along with any frames - * from this queue. Not relevant for Tx queues. + * @destination - Destination structure + * @destination.id: ID of the destination, only relevant if DEST_TYPE is > 0. + * Identifies either a DPIO or a DPCON object. + * Not relevant for Tx queues. + * @destination.type: May be one of the following: + * 0 - No destination, queue can be manually + * queried, but will not push traffic or + * notifications to a DPIO; + * 1 - The destination is a DPIO. When traffic + * becomes available in the queue a FQDAN + * (FQ data available notification) will be + * generated to selected DPIO; + * 2 - The destination is a DPCON. The queue is + * associated with a DPCON object for the + * purpose of scheduling between multiple + * queues. The DPCON may be independently + * configured to generate notifications. + * Not relevant for Tx queues. + * @destination.hold_active: Hold active, maintains a queue scheduled for longer + * in a DPIO during dequeue to reduce spread of traffic. + * Only relevant if queues are + * not affined to a single DPIO. + * @user_context: User data, presented to the user along with any frames + * from this queue. Not relevant for Tx queues. + * @flc: FD FLow Context structure + * @flc.value: Default FLC value for traffic dequeued from + * this queue. Please check description of FD + * structure for more information. + * Note that FLC values set using dpni_add_fs_entry, + * if any, take precedence over values per queue. + * @flc.stash_control: Boolean, indicates whether the 6 lowest + * - significant bits are used for stash control. + * significant bits are used for stash control. If set, the 6 + * least significant bits in value are interpreted as follows: + * - bits 0-1: indicates the number of 64 byte units of context + * that are stashed. FLC value is interpreted as a memory address + * in this case, excluding the 6 LS bits. + * - bits 2-3: indicates the number of 64 byte units of frame + * annotation to be stashed. Annotation is placed at FD[ADDR]. + * - bits 4-5: indicates the number of 64 byte units of frame + * data to be stashed. Frame data is placed at FD[ADDR] + + * FD[OFFSET]. + * For more details check the Frame Descriptor section in the + * hardware documentation. + *@cgid :indicate the cgid to set relative to dpni */ struct dpni_queue { - /** - * struct destination - Destination structure - * @id: ID of the destination, only relevant if DEST_TYPE is > 0. - * Identifies either a DPIO or a DPCON object. Not relevant for Tx - * queues. - * @type: May be one of the following: - * 0 - No destination, queue can be manually queried, but won't - * push traffic or notifications to a DPIO; - * 1 - The destination is DPIO. When traffic becomes available in - * the queue a FQDAN (FQ data available notification) will be - * generated to selected DPIO; - * 2 - The destination is a DPCON. The queue is associated with a - * DPCON object for purpose of scheduling between multiple - * queues. The DPCON may be independently configured to - * generate notifications. Not relevant for Tx queues. - * @hold_active: Hold active - */ struct { - uint32_t id; + u16 id; enum dpni_dest type; char hold_active; - char stash_ctrl; + u8 priority; } destination; - uint8_t options; - uint32_t fqid; - uint16_t qdbin; - uint64_t flc; - uint64_t user_context; + u64 user_context; + struct { + u64 value; + char stash_control; + } flc; + int cgid; }; /** - * dpni_set_queue() - Set queue parameters - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @type: Type of queue - * @tc: Traffic class, in range 0 to NUM_TCS - 1 - * @index: Selects the specific queue out of the set allocated for the same - * TC. Value must be in range 0 to NUM_QUEUES - 1 - * @queue: Queue structure - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - const struct dpni_queue *queue); - -/** - * dpni_get_queue() - Get queue parameters - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @type: Type of queue - * @tc: Traffic class, in range 0 to NUM_TCS - 1 - * @index: Selects the specific queue out of the set allocated for the same - * TC. Value must be in range 0 to NUM_QUEUES - 1 - * @queue: Queue structure - * - * Return: '0' on Success; Error code otherwise. + * struct dpni_queue_id - Queue identification, used for enqueue commands + * or queue control + * @fqid: FQID used for enqueueing to and/or configuration of this + * specific FQ + * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. + * Only relevant for Tx queues. */ -int dpni_get_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - struct dpni_queue *queue); - -/** - * dpni_set_tx_confirmation_mode() - Set TX conf mode - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mode: DPNI confirmation mode type - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_confirmation_mode mode); -struct dpni_statistics { - /** - * Page_0 statistics structure - * @ingress_all_frames: Ingress frame count - * @ingress_all_bytes: Ingress byte count - * @ingress_multicast_frames: Ingress multicast frame count - * @ingress_multicast_bytes: Ingress multicast byte count - * @ingress_broadcast_frames: Ingress broadcast frame count - * @ingress_broadcast_bytes: Ingress broadcast byte count - * - * Page_1 statistics structure - * @egress_all_frames: Egress frame count - * @egress_all_bytes: Egress byte count - * @egress_multicast_frames: Egress multicast frame count - * @egress_multicast_bytes: Egress multicast byte count - * @egress_broadcast_frames: Egress broadcast frame count - * @egress_broadcast_bytes: Egress broadcast byte count - * - * Page_2 statistics structure - * @ingress_filtered_frames: Ingress filtered frame count - * @ingress_discarded_frames: Ingress discarded frame count - * @ingress_nobuffer_discards: Ingress discarded frame count due to - * lack of buffers. - * @egress_discarded_frames: Egress discarded frame count - * @egress_confirmed_frames: Egress confirmed frame count - */ - - uint64_t counter0; - uint64_t counter1; - uint64_t counter2; - uint64_t counter3; - uint64_t counter4; - uint64_t counter5; - uint64_t counter6; +struct dpni_queue_id { + u32 fqid; + u16 qdbin; }; -/** - * dpni_get_statistics() - Get DPNI statistics - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @page: Selects the statistics page to retrieve, see DPNI_GET_STATISTICS - * output. Pages are numbered 0 to 2. - * @stat: Structure containing the statistics - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t page, - struct dpni_statistics *stat); +int dpni_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + u8 options, const struct dpni_queue *queue); + +int dpni_get_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + struct dpni_queue *queue, struct dpni_queue_id *qid); + +int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 ceetm_ch_idx, enum dpni_confirmation_mode mode); + +#define DPNI_STATISTICS_CNT 7 + +/** + * union dpni_statistics - Union describing the DPNI statistics + * @page_0: Page_0 statistics structure + * @page_0.ingress_all_frames: Ingress frame count + * @page_0.ingress_all_bytes: Ingress byte count + * @page_0.ingress_multicast_frames: Ingress multicast frame count + * @page_0.ingress_multicast_bytes: Ingress multicast byte count + * @page_0.ingress_broadcast_frames: Ingress broadcast frame count + * @page_0.ingress_broadcast_bytes: Ingress broadcast byte count + * @page_1: Page_1 statistics structure + * @page_1.egress_all_frames: Egress frame count + * @page_1.egress_all_bytes: Egress byte count + * @page_1.egress_multicast_frames: Egress multicast frame count + * @page_1.egress_multicast_bytes: Egress multicast byte count + * @page_1.egress_broadcast_frames: Egress broadcast frame count + * @page_1.egress_broadcast_bytes: Egress broadcast byte count + * @page_2: Page_2 statistics structure + * @page_2.ingress_filtered_frames: Ingress filtered frame count + * @page_2.ingress_discarded_frames: Ingress discarded frame count + * @page_2.ingress_nobuffer_discards: Ingress discarded frame count due to + * lack of buffers + * @page_2.egress_discarded_frames: Egress discarded frame count + * @page_2.egress_confirmed_frames: Egress confirmed frame count + * @page_3: Page_3 statistics structure + * @page_3.egress_dequeue_bytes: Cumulative count of the number of bytes + * dequeued from egress FQs + * @page_3.egress_dequeue_frames: Cumulative count of the number of frames + * dequeued from egress FQs + * @page_3.egress_reject_bytes: Cumulative count of the number of bytes in + * egress frames whose enqueue was rejected + * @page_3.egress_reject_frames: Cumulative count of the number of egress + * frames whose enqueue was rejected + * @page_4: Page_4 statistics structure: congestion points + * @page_4.cgr_reject_frames: number of rejected frames due to congestion point + * @page_4.cgr_reject_bytes: number of rejected bytes due to congestion point + * @page_5: Page_5 statistics structure: policer + * @page_5.policer_cnt_red: NUmber of red colored frames + * @page_5.policer_cnt_yellow: number of yellow colored frames + * @page_5.policer_cnt_green: number of green colored frames + * @page_5.policer_cnt_re_red: number of recolored red frames + * @page_5.policer_cnt_re_yellow: number of recolored yellow frames + * @page_6: Page_6 statistics structure + * @page_6.tx_pending_frames: total number of frames pending in egress FQs + * @raw: raw statistics structure, used to index counters + */ +union dpni_statistics { + struct { + u64 ingress_all_frames; + u64 ingress_all_bytes; + u64 ingress_multicast_frames; + u64 ingress_multicast_bytes; + u64 ingress_broadcast_frames; + u64 ingress_broadcast_bytes; + } page_0; + struct { + u64 egress_all_frames; + u64 egress_all_bytes; + u64 egress_multicast_frames; + u64 egress_multicast_bytes; + u64 egress_broadcast_frames; + u64 egress_broadcast_bytes; + } page_1; + struct { + u64 ingress_filtered_frames; + u64 ingress_discarded_frames; + u64 ingress_nobuffer_discards; + u64 egress_discarded_frames; + u64 egress_confirmed_frames; + } page_2; + struct { + u64 egress_dequeue_bytes; + u64 egress_dequeue_frames; + u64 egress_reject_bytes; + u64 egress_reject_frames; + } page_3; + struct { + u64 cgr_reject_frames; + u64 cgr_reject_bytes; + } page_4; + struct { + u64 policer_cnt_red; + u64 policer_cnt_yellow; + u64 policer_cnt_green; + u64 policer_cnt_re_red; + u64 policer_cnt_re_yellow; + } page_5; + struct { + u64 tx_pending_frames; + } page_6; + struct { + u64 counter[DPNI_STATISTICS_CNT]; + } raw; +}; -/** - * dpni_reset_statistics() - Clears DPNI statistics - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_reset_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 page, u16 param, union dpni_statistics *stat); #endif /* _FSL_DPNI_H */ diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index 950ecb0756..fb95ac544a 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -3,7 +3,7 @@ * Freescale Layerscape MC I/O wrapper * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPRC_H #define _FSL_DPRC_H @@ -15,442 +15,82 @@ /* Command IDs */ #define DPRC_CMDID_CLOSE 0x8001 #define DPRC_CMDID_OPEN 0x8051 -#define DPRC_CMDID_CREATE 0x9051 -#define DPRC_CMDID_GET_ATTR 0x0041 -#define DPRC_CMDID_RESET_CONT 0x0051 #define DPRC_CMDID_GET_API_VERSION 0xa051 #define DPRC_CMDID_CREATE_CONT 0x1511 #define DPRC_CMDID_DESTROY_CONT 0x1521 #define DPRC_CMDID_GET_CONT_ID 0x8301 -#define DPRC_CMDID_GET_OBJ_COUNT 0x1591 -#define DPRC_CMDID_GET_OBJ 0x15A1 -#define DPRC_CMDID_GET_RES_COUNT 0x15B1 -#define DPRC_CMDID_GET_RES_IDS 0x15C1 -#define DPRC_CMDID_GET_OBJ_REG 0x15E1 #define DPRC_CMDID_CONNECT 0x1671 #define DPRC_CMDID_DISCONNECT 0x1681 #define DPRC_CMDID_GET_CONNECTION 0x16C1 -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \ - MC_RSP_OP(cmd, 0, 0, 32, int, container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_OPEN(cmd, container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \ - MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \ - MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->container_id); \ - MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\ - MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_count) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ(cmd, obj_index) \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_index) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ - MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ - MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ - MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ - MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ - MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ - MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ - MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ - MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ - MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ - MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ - MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ - MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ - MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ - MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ - MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ - MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ - MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ - MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ - MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ - MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ - MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ - MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ - MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ - MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ - MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ - MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ - MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ - MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ - MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ - MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ - MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ - MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ - MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ - MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ - MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ - MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\ - MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ - MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ - MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ - MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ - MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ - MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ - MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ - MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ - MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ - MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ - MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ - MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ - MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ - MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ - MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ - MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ - MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ - MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ - MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ - MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ - MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ - MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ - MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ - MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ - MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ - MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ - MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ - MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ - MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ - MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ - MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ - MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ - MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ - MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ - MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ - MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ - MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_RES_COUNT(cmd, type) \ -do { \ - MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \ - MC_RSP_OP(cmd, 0, 0, 32, int, res_count) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \ -do { \ - MC_CMD_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ - range_desc->iter_status); \ - MC_CMD_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ - MC_CMD_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ - MC_CMD_OP(cmd, 2, 0, 8, char, type[0]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, type[1]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, type[2]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, type[3]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, type[4]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, type[5]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, type[6]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, type[7]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, type[8]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, type[9]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, type[10]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, type[11]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, type[12]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, type[13]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, type[14]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ - range_desc->iter_status);\ - MC_RSP_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ - MC_RSP_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, region_index);\ - MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ -} while (0) - -/* param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, region_desc->base_offset);\ - MC_RSP_OP(cmd, 2, 0, 32, uint32_t, region_desc->size); \ - MC_RSP_OP(cmd, 2, 32, 4, enum dprc_region_type, region_desc->type);\ - MC_RSP_OP(cmd, 3, 0, 32, uint32_t, region_desc->flags);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, label[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, label[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, label[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, label[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, label[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, label[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, label[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, label[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, label[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, label[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, label[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, label[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, label[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, label[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, label[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, label[15]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ - MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \ - MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[3]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[4]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[5]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[6]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[7]); \ - MC_CMD_OP(cmd, 3, 0, 8, char, endpoint1->type[8]); \ - MC_CMD_OP(cmd, 3, 8, 8, char, endpoint1->type[9]); \ - MC_CMD_OP(cmd, 3, 16, 8, char, endpoint1->type[10]); \ - MC_CMD_OP(cmd, 3, 24, 8, char, endpoint1->type[11]); \ - MC_CMD_OP(cmd, 3, 32, 8, char, endpoint1->type[12]); \ - MC_CMD_OP(cmd, 3, 40, 8, char, endpoint1->type[13]); \ - MC_CMD_OP(cmd, 3, 48, 8, char, endpoint1->type[14]); \ - MC_CMD_OP(cmd, 3, 56, 8, char, endpoint1->type[15]); \ - MC_CMD_OP(cmd, 4, 0, 32, uint32_t, cfg->max_rate); \ - MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->committed_rate); \ - MC_CMD_OP(cmd, 5, 0, 8, char, endpoint2->type[0]); \ - MC_CMD_OP(cmd, 5, 8, 8, char, endpoint2->type[1]); \ - MC_CMD_OP(cmd, 5, 16, 8, char, endpoint2->type[2]); \ - MC_CMD_OP(cmd, 5, 24, 8, char, endpoint2->type[3]); \ - MC_CMD_OP(cmd, 5, 32, 8, char, endpoint2->type[4]); \ - MC_CMD_OP(cmd, 5, 40, 8, char, endpoint2->type[5]); \ - MC_CMD_OP(cmd, 5, 48, 8, char, endpoint2->type[6]); \ - MC_CMD_OP(cmd, 5, 56, 8, char, endpoint2->type[7]); \ - MC_CMD_OP(cmd, 6, 0, 8, char, endpoint2->type[8]); \ - MC_CMD_OP(cmd, 6, 8, 8, char, endpoint2->type[9]); \ - MC_CMD_OP(cmd, 6, 16, 8, char, endpoint2->type[10]); \ - MC_CMD_OP(cmd, 6, 24, 8, char, endpoint2->type[11]); \ - MC_CMD_OP(cmd, 6, 32, 8, char, endpoint2->type[12]); \ - MC_CMD_OP(cmd, 6, 40, 8, char, endpoint2->type[13]); \ - MC_CMD_OP(cmd, 6, 48, 8, char, endpoint2->type[14]); \ - MC_CMD_OP(cmd, 6, 56, 8, char, endpoint2->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_DISCONNECT(cmd, endpoint) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint->id); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, endpoint->type[0]); \ - MC_CMD_OP(cmd, 1, 8, 8, char, endpoint->type[1]); \ - MC_CMD_OP(cmd, 1, 16, 8, char, endpoint->type[2]); \ - MC_CMD_OP(cmd, 1, 24, 8, char, endpoint->type[3]); \ - MC_CMD_OP(cmd, 1, 32, 8, char, endpoint->type[4]); \ - MC_CMD_OP(cmd, 1, 40, 8, char, endpoint->type[5]); \ - MC_CMD_OP(cmd, 1, 48, 8, char, endpoint->type[6]); \ - MC_CMD_OP(cmd, 1, 56, 8, char, endpoint->type[7]); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint->type[8]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint->type[9]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint->type[10]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint->type[11]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint->type[12]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint->type[13]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint->type[14]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \ - MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \ - MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \ - MC_CMD_OP(cmd, 1, 24, 8, char, endpoint1->type[3]); \ - MC_CMD_OP(cmd, 1, 32, 8, char, endpoint1->type[4]); \ - MC_CMD_OP(cmd, 1, 40, 8, char, endpoint1->type[5]); \ - MC_CMD_OP(cmd, 1, 48, 8, char, endpoint1->type[6]); \ - MC_CMD_OP(cmd, 1, 56, 8, char, endpoint1->type[7]); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[8]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[9]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[10]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[11]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[12]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[13]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[14]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \ -do { \ - MC_RSP_OP(cmd, 3, 0, 32, int, endpoint2->id); \ - MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \ - MC_RSP_OP(cmd, 4, 0, 8, char, endpoint2->type[0]); \ - MC_RSP_OP(cmd, 4, 8, 8, char, endpoint2->type[1]); \ - MC_RSP_OP(cmd, 4, 16, 8, char, endpoint2->type[2]); \ - MC_RSP_OP(cmd, 4, 24, 8, char, endpoint2->type[3]); \ - MC_RSP_OP(cmd, 4, 32, 8, char, endpoint2->type[4]); \ - MC_RSP_OP(cmd, 4, 40, 8, char, endpoint2->type[5]); \ - MC_RSP_OP(cmd, 4, 48, 8, char, endpoint2->type[6]); \ - MC_RSP_OP(cmd, 4, 56, 8, char, endpoint2->type[7]); \ - MC_RSP_OP(cmd, 5, 0, 8, char, endpoint2->type[8]); \ - MC_RSP_OP(cmd, 5, 8, 8, char, endpoint2->type[9]); \ - MC_RSP_OP(cmd, 5, 16, 8, char, endpoint2->type[10]); \ - MC_RSP_OP(cmd, 5, 24, 8, char, endpoint2->type[11]); \ - MC_RSP_OP(cmd, 5, 32, 8, char, endpoint2->type[12]); \ - MC_RSP_OP(cmd, 5, 40, 8, char, endpoint2->type[13]); \ - MC_RSP_OP(cmd, 5, 48, 8, char, endpoint2->type[14]); \ - MC_RSP_OP(cmd, 5, 56, 8, char, endpoint2->type[15]); \ - MC_RSP_OP(cmd, 6, 0, 32, int, state); \ -} while (0) +#pragma pack(push, 1) +struct dprc_cmd_open { + __le32 container_id; +}; + +struct dprc_cmd_create_container { + __le32 options; + __le32 icid; + __le32 pad1; + __le32 portal_id; + u8 label[16]; +}; + +struct dprc_rsp_create_container { + __le64 pad0; + __le32 child_container_id; + __le32 pad1; + __le64 child_portal_addr; +}; + +struct dprc_cmd_destroy_container { + __le32 child_container_id; +}; + +struct dprc_cmd_connect { + __le32 ep1_id; + __le16 ep1_interface_id; + __le16 pad0; + + __le32 ep2_id; + __le16 ep2_interface_id; + __le16 pad1; + + u8 ep1_type[16]; + + __le32 max_rate; + __le32 committed_rate; + + u8 ep2_type[16]; +}; + +struct dprc_cmd_disconnect { + __le32 id; + __le32 interface_id; + u8 type[16]; +}; + +struct dprc_cmd_get_connection { + __le32 ep1_id; + __le16 ep1_interface_id; + __le16 pad; + + u8 ep1_type[16]; +}; + +struct dprc_rsp_get_connection { + __le64 pad[3]; + __le32 ep2_id; + __le16 ep2_interface_id; + __le16 pad1; + u8 ep2_type[16]; + __le32 state; +}; + +#pragma pack(pop) /* Data Path Resource Container API * Contains DPRC API for managing and querying DPAA resources @@ -463,7 +103,7 @@ struct fsl_mc_io; * container, in case the ICID is not selected by the user and should be * allocated by the DPRC from the pool of ICIDs. */ -#define DPRC_GET_ICID_FROM_POOL (uint16_t)(~(0)) +#define DPRC_GET_ICID_FROM_POOL (u16)(~(0)) /** * Set this value as the portal_id value in dprc_cfg structure when creating a @@ -472,48 +112,11 @@ struct fsl_mc_io; */ #define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0)) -/** - * dprc_get_container_id() - Get container ID associated with a given portal. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Requested container ID - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_container_id(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int *container_id); +int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id); -/** - * dprc_open() - Open DPRC object for use - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Container ID to open - * @token: Returned token of DPRC object - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Required before any operation on the object. - */ -int dprc_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int container_id, - uint16_t *token); +int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int container_id, u16 *token); -/** - * dprc_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * Container general options @@ -563,395 +166,57 @@ int dprc_close(struct fsl_mc_io *mc_io, * @label: Object's label */ struct dprc_cfg { - uint16_t icid; - int portal_id; - uint64_t options; - char label[16]; -}; - -/** - * dprc_create_container() - Create child container - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @cfg: Child container configuration - * @child_container_id: Returned child container ID - * @child_portal_offset: Returned child portal offset from MC portal base - * - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_create_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_cfg *cfg, - int *child_container_id, - uint64_t *child_portal_offset); - -/** - * dprc_destroy_container() - Destroy child container. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @child_container_id: ID of the container to destroy - * - * This function terminates the child container, so following this call the - * child container ID becomes invalid. - * - * Notes: - * - All resources and objects of the destroyed container are returned to the - * parent container or destroyed if were created be the destroyed container. - * - This function destroy all the child containers of the specified - * container prior to destroying the container itself. - * - * warning: Only the parent container is allowed to destroy a child policy - * Container 0 can't be destroyed - * - * Return: '0' on Success; Error code otherwise. - * - */ -int dprc_destroy_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id); - -/** - * dprc_reset_container - Reset child container. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @child_container_id: ID of the container to reset - * - * In case a software context crashes or becomes non-responsive, the parent - * may wish to reset its resources container before the software context is - * restarted. - * - * This routine informs all objects assigned to the child container that the - * container is being reset, so they may perform any cleanup operations that are - * needed. All objects handles that were owned by the child container shall be - * closed. - * - * Note that such request may be submitted even if the child software context - * has not crashed, but the resulting object cleanup operations will not be - * aware of that. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_reset_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id); - -/** - * struct dprc_attributes - Container attributes - * @container_id: Container's ID - * @icid: Container's ICID - * @portal_id: Container's portal ID - * @options: Container's options as set at container's creation - * @version: DPRC version - */ -struct dprc_attributes { - int container_id; - uint16_t icid; + u16 icid; int portal_id; uint64_t options; -}; - -/** - * dprc_get_attributes() - Obtains container attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @attributes: Returned container attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_attributes *attributes); - -/** - * dprc_get_obj_count() - Obtains the number of objects in the DPRC - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_count: Number of objects assigned to the DPRC - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *obj_count); - -/* Objects Attributes Flags */ - -/* Opened state - Indicates that an object is open by at least one owner */ -#define DPRC_OBJ_STATE_OPEN 0x00000001 -/* Plugged state - Indicates that the object is plugged */ -#define DPRC_OBJ_STATE_PLUGGED 0x00000002 - -/** - * Shareability flag - Object flag indicating no memory shareability. - * the object generates memory accesses that are non coherent with other - * masters; - * user is responsible for proper memory handling through IOMMU configuration. - */ -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 - -/** - * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() - * @type: Type of object: NULL terminated string - * @id: ID of logical object resource - * @vendor: Object vendor identifier - * @ver_major: Major version number - * @ver_minor: Minor version number - * @irq_count: Number of interrupts supported by the object - * @region_count: Number of mappable regions supported by the object - * @state: Object state: combination of DPRC_OBJ_STATE_ states - * @label: Object label - * @flags: Object's flags - */ -struct dprc_obj_desc { - char type[16]; - int id; - uint16_t vendor; - uint16_t ver_major; - uint16_t ver_minor; - uint8_t irq_count; - uint8_t region_count; - uint32_t state; char label[16]; - uint16_t flags; }; -/** - * dprc_get_obj() - Get general information on an object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_index: Index of the object to be queried (< obj_count) - * @obj_desc: Returns the requested object descriptor - * - * The object descriptors are retrieved one by one by incrementing - * obj_index up to (not including) the value of obj_count returned - * from dprc_get_obj_count(). dprc_get_obj_count() must - * be called prior to dprc_get_obj(). - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int obj_index, - struct dprc_obj_desc *obj_desc); - -/** - * dprc_get_res_count() - Obtains the number of free resources that are - * assigned to this container, by pool type - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @type: pool type - * @res_count: Returned number of free resources of the given - * resource type that are assigned to this DPRC - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_res_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - int *res_count); - -/** - * enum dprc_iter_status - Iteration status - * @DPRC_ITER_STATUS_FIRST: Perform first iteration - * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed - * @DPRC_ITER_STATUS_LAST: Indicates last iteration - */ -enum dprc_iter_status { - DPRC_ITER_STATUS_FIRST = 0, - DPRC_ITER_STATUS_MORE = 1, - DPRC_ITER_STATUS_LAST = 2 -}; - -/** - * struct dprc_res_ids_range_desc - Resource ID range descriptor - * @base_id: Base resource ID of this range - * @last_id: Last resource ID of this range - * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at - * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE, - * additional iterations are needed, until the returned marker is - * DPRC_ITER_STATUS_LAST - */ -struct dprc_res_ids_range_desc { - int base_id; - int last_id; - enum dprc_iter_status iter_status; -}; - -/** - * dprc_get_res_ids() - Obtains IDs of free resources in the container - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @type: pool type - * @range_desc: range descriptor - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_res_ids(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - struct dprc_res_ids_range_desc *range_desc); - -/* Region flags */ -/* Cacheable - Indicates that region should be mapped as cacheable */ -#define DPRC_REGION_CACHEABLE 0x00000001 +int dprc_create_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dprc_cfg *cfg, int *child_container_id, + uint64_t *child_portal_offset); -/** - * enum dprc_region_type - Region type - * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region - * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region - */ -enum dprc_region_type { - DPRC_REGION_TYPE_MC_PORTAL, - DPRC_REGION_TYPE_QBMAN_PORTAL -}; +int dprc_destroy_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + int child_container_id); /** - * struct dprc_region_desc - Mappable region descriptor - * @base_offset: Region offset from region's base address. - * For DPMCP and DPRC objects, region base is offset from SoC MC portals - * base address; For DPIO, region base is offset from SoC QMan portals - * base address - * @size: Region size (in bytes) - * @flags: Region attributes - * @type: Portal region type + * struct dprc_connection_cfg - Connection configuration. + * Used for virtual connections only + * @committed_rate: Committed rate (Mbits/s) + * @max_rate: Maximum rate (Mbits/s) */ -struct dprc_region_desc { - uint32_t base_offset; - uint32_t size; - uint32_t flags; - enum dprc_region_type type; +struct dprc_connection_cfg { + u32 committed_rate; + u32 max_rate; }; /** - * dprc_get_obj_region() - Get region information for a specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_type: Object type as returned in dprc_get_obj() - * @obj_id: Unique object instance as returned in dprc_get_obj() - * @region_index: The specific region to query - * @region_desc: Returns the requested region descriptor - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *obj_type, - int obj_id, - uint8_t region_index, - struct dprc_region_desc *region_desc); -/** * struct dprc_endpoint - Endpoint description for link connect/disconnect * operations - * @type: Endpoint object type: NULL terminated string - * @id: Endpoint object ID - * @if_id: Interface ID; should be set for endpoints with multiple + * @type: Endpoint object type: NULL terminated string + * @id: Endpoint object ID + * @if_id: Interface ID; should be set for endpoints with multiple * interfaces ("dpsw", "dpdmux"); for others, always set to 0 */ struct dprc_endpoint { - char type[16]; - int id; - uint16_t if_id; -}; - -/** - * struct dprc_connection_cfg - Connection configuration. - * Used for virtual connections only - * @committed_rate: Committed rate (Mbits/s) - * @max_rate: Maximum rate (Mbits/s) - */ -struct dprc_connection_cfg { - uint32_t committed_rate; - uint32_t max_rate; + char type[16]; + int id; + u16 if_id; }; -/** - * dprc_connect() - Connect two endpoints to create a network link between them - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @endpoint1: Endpoint 1 configuration parameters - * @endpoint2: Endpoint 2 configuration parameters - * @cfg: Connection configuration. The connection configuration is ignored for - * connections made to DPMAC objects, where rate is retrieved from the - * MAC configuration. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_connect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint1, - const struct dprc_endpoint *endpoint2, - const struct dprc_connection_cfg *cfg); +int dprc_connect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint1, + const struct dprc_endpoint *endpoint2, + const struct dprc_connection_cfg *cfg); -/** - * dprc_disconnect() - Disconnect one endpoint to remove its network connection - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @endpoint: Endpoint configuration parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_disconnect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint); +int dprc_disconnect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint); -/** -* dprc_get_connection() - Get connected endpoint and link status if connection -* exists. -* @mc_io: Pointer to MC portal's I/O object -* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -* @token: Token of DPRC object -* @endpoint1: Endpoint 1 configuration parameters -* @endpoint2: Returned endpoint 2 configuration parameters -* @state: Returned link state: -* 1 - link is up; -* 0 - link is down; -* -1 - no connection (endpoint2 information is irrelevant) -* -* Return: '0' on Success; -ENAVAIL if connection does not exist. -*/ -int dprc_get_connection(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint1, - struct dprc_endpoint *endpoint2, - int *state); +int dprc_get_connection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint1, + struct dprc_endpoint *endpoint2, int *state); -/** - * dprc_get_api_version - Retrieve DPRC Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPRC major version - * @minor_ver: DPRC minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dprc_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPRC_H */ diff --git a/include/fsl-mc/fsl_dpsparser.h b/include/fsl-mc/fsl_dpsparser.h index 48fb495059..9619bb1413 100644 --- a/include/fsl-mc/fsl_dpsparser.h +++ b/include/fsl-mc/fsl_dpsparser.h @@ -2,7 +2,7 @@ /* * Data Path Soft Parser API * - * Copyright 2018 NXP + * Copyright 2018, 2023 NXP */ #ifndef _FSL_DPSPARSER_H #define _FSL_DPSPARSER_H @@ -20,13 +20,26 @@ #define DPSPARSER_CMDID_APPLY_SPB 0x1181 -/* cmd, param, offset, width, type, arg_name */ -#define DPSPARSER_CMD_BLOB_SET_ADDR(cmd, addr) \ - MC_CMD_OP(cmd, 0, 0, 64, u64, addr) +#pragma pack(push, 1) -/* cmd, param, offset, width, type, arg_name */ -#define DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, err) \ - MC_RSP_OP(cmd, 0, 0, 16, u16, err) +struct dpsparser_cmd_destroy { + __le32 dpsparser_id; +}; + +struct dpsparser_cmd_blob_set_address { + __le64 blob_addr; +}; + +struct dpsparser_rsp_blob_report_error { + __le16 error; +}; + +struct dpsparser_rsp_get_api_version { + __le16 major; + __le16 minor; +}; + +#pragma pack(pop) /* Data Path Soft Parser API * Contains initialization APIs and runtime control APIs for DPSPARSER @@ -99,110 +112,20 @@ struct fsl_mc_io; NULL, \ } -/** - * dpsparser_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpsparser_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *token); - -/** - * dpsparser_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/** - * dpsparser_create() - Create the DPSPARSER object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Returned token; use in subsequent API calls - * - * Create the DPSPARSER object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpsparser_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_create(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +int dpsparser_open(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *token); + +int dpsparser_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); + +int dpsparser_create(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 *obj_id); -/** - * dpsparser_destroy() - Destroy the DPSPARSER object and release all its - * resources. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * - * Return: '0' on Success; error code otherwise. - */ -int dpsparser_destroy(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +int dpsparser_destroy(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 obj_id); -/** - * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified - * address. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * @blob_addr: Blob loading address - * @error: Error reported by MC related to SP Blob parsing and apply - * - * Return: '0' on Success; error code otherwise. - */ -int dpsparser_apply_spb(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u64 blob_addr, - u16 *error); - -/** - * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPSPARSER major version - * @minor_ver: DPSPARSER minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpsparser_apply_spb(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u64 blob_addr, u16 *error); + +int dpsparser_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPSPARSER_H */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 591cda9685..c239595ed5 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -19,6 +19,15 @@ static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width) return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width)); } +struct mc_cmd_header { + u8 src_id; + u8 flags_hw; + u8 status; + u8 flags_sw; + __le16 token; + __le16 cmd_id; +}; + struct mc_command { uint64_t header; uint64_t params[MC_CMD_NUM_OF_PARAMS]; @@ -74,29 +83,6 @@ enum mc_cmd_status { ((enum mc_cmd_status)mc_dec((_hdr), \ MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) -#define MC_CMD_HDR_READ_TOKEN(_hdr) \ - ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) - -#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ - ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) - -#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ - (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) - -#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ - ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) - -#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ - (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width))) - -/* cmd, param, offset, width, type, arg_name */ -#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \ - MC_RSP_OP(cmd, 0, 0, 32, uint32_t, obj_id) - -/* cmd, param, offset, width, type, arg_name */ -#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, object_id) - static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, uint32_t cmd_flags, uint16_t token) @@ -179,4 +165,19 @@ static inline void mc_cmd_read_api_version(struct mc_command *cmd, *minor_ver = le16_to_cpu(rsp_params->minor_ver); } +static inline uint16_t mc_cmd_hdr_read_token(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 token = le16_to_cpu(hdr->token); + + return token; +} + +static inline uint32_t mc_cmd_read_object_id(struct mc_command *cmd) +{ + struct mc_rsp_create *rsp_params; + + rsp_params = (struct mc_rsp_create *)cmd->params; + return le32_to_cpu(rsp_params->object_id); +} #endif /* __FSL_MC_CMD_H */ diff --git a/include/fsl_validate.h b/include/fsl_validate.h index fbcbd42496..66a5883f1f 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -275,9 +275,9 @@ int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); /* - * This function is used to validate the main U-boot binary from + * This function is used to validate the main U-Boot binary from * SPL just before passing control to it using QorIQ Trust - * Architecture header (appended to U-boot image). + * Architecture header (appended to U-Boot image). */ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); diff --git a/include/fwu.h b/include/fwu.h index 0919ced812..ac5c5de870 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -8,6 +8,8 @@ #include <blk.h> #include <efi.h> +#include <mtd.h> +#include <uuid.h> #include <linux/types.h> @@ -18,83 +20,32 @@ struct fwu_mdata_gpt_blk_priv { struct udevice *blk_dev; }; -/** - * @mdata_check: check the validity of the FWU metadata partitions - * @get_mdata() - Get a FWU metadata copy - * @update_mdata() - Update the FWU metadata copy - */ -struct fwu_mdata_ops { - /** - * check_mdata() - Check if the FWU metadata is valid - * @dev: FWU device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - */ - int (*check_mdata)(struct udevice *dev); - - /** - * get_mdata() - Get a FWU metadata copy - * @dev: FWU device - * @mdata: Pointer to FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Return: 0 if OK, -ve on error - */ - int (*get_mdata)(struct udevice *dev, struct fwu_mdata *mdata); - - /** - * update_mdata() - Update the FWU metadata - * @dev: FWU device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Return: 0 if OK, -ve on error - */ - int (*update_mdata)(struct udevice *dev, struct fwu_mdata *mdata); - - /** - * get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned. - * - * Return: 0 if OK, -ve on error - */ - int (*get_mdata_part_num)(struct udevice *dev, uint *mdata_parts); +struct fwu_mtd_image_info { + u32 start, size; + int bank_num, image_num; + char uuidbuf[UUID_STR_LEN + 1]; +}; +struct fwu_mdata_ops { /** - * read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read - * - * Read the FWU metadata from the specified partition number + * read_mdata() - Populate the asked FWU metadata copy + * @dev: FWU metadata device + * @mdata: Output FWU mdata read + * @primary: If primary or secondary copy of metadata is to be read * * Return: 0 if OK, -ve on error */ - int (*read_mdata_partition)(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num); + int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); /** - * write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number + * write_mdata() - Write the given FWU metadata copy + * @dev: FWU metadata device + * @mdata: Copy of the FWU metadata to write + * @primary: If primary or secondary copy of metadata is to be written * * Return: 0 if OK, -ve on error */ - int (*write_mdata_partition)(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num); + int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); }; #define FWU_MDATA_VERSION 0x1 @@ -127,100 +78,25 @@ struct fwu_mdata_ops { 0xe1, 0xfc, 0xed, 0xf1, 0xc6, 0xf8) /** - * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies - * - * Read both the metadata copies from the storage media, verify their - * checksum, and ascertain that both copies match. If one of the copies - * has gone bad, restore it from the good copy. - * - * Return: 0 if OK, -ve on error - * + * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata() */ -int fwu_check_mdata_validity(void); +int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); /** - * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned - * through the array. - * - * Return: 0 if OK, -ve on error - * + * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata() */ -int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts); +int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); /** - * fwu_read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read + * fwu_get_mdata() - Read, verify and return the FWU metadata * - * Read the FWU metadata from the specified partition number + * Read both the metadata copies from the storage media, verify their checksum, + * and ascertain that both copies match. If one of the copies has gone bad, + * restore it from the good copy. * * Return: 0 if OK, -ve on error - * - */ -int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num); - -/** - * fwu_write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number - * - * Return: 0 if OK, -ve on error - * */ -int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num); - -/** - * fwu_get_mdata() - Get a FWU metadata copy - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Note: This function is to be called first when modifying any fields - * in the metadata. The sequence of calls to modify any field in the - * metadata would be 1) fwu_get_mdata 2) Modify metadata, followed by - * 3) fwu_update_mdata - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata); - -/** - * fwu_update_mdata() - Update the FWU metadata - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Note: This function is not to be called directly to update the - * metadata fields. The sequence of function calls should be - * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata() - * - * The sequence of updating the partitions should be, update the - * primary metadata partition (first partition encountered), followed - * by updating the secondary partition. With this update sequence, in - * the rare scenario that the two metadata partitions are valid but do - * not match, maybe due to power outage at the time of updating the - * metadata copies, the secondary partition can be updated from the - * primary. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata); +int fwu_get_mdata(struct fwu_mdata *mdata); /** * fwu_get_active_index() - Get active_index from the FWU metadata @@ -263,18 +139,6 @@ int fwu_set_active_index(uint active_idx); int fwu_get_image_index(u8 *image_index); /** - * fwu_mdata_check() - Check if the FWU metadata is valid - * @dev: FWU metadata device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_mdata_check(struct udevice *dev); - -/** * fwu_revert_boot_index() - Revert the active index in the FWU metadata * * Revert the active_index value in the FWU metadata, by swapping the values @@ -287,20 +151,6 @@ int fwu_mdata_check(struct udevice *dev); int fwu_revert_boot_index(void); /** - * fwu_verify_mdata() - Verify the FWU metadata - * @mdata: FWU metadata structure - * @pri_part: FWU metadata partition is primary or secondary - * - * Verify the FWU metadata by computing the CRC32 for the metadata - * structure and comparing it against the CRC32 value stored as part - * of the structure. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part); - -/** * fwu_accept_image() - Set the Acceptance bit for the image * @img_type_id: GUID of the image type for which the accepted bit is to be * cleared @@ -409,4 +259,28 @@ u8 fwu_empty_capsule_checks_pass(void); */ int fwu_trial_state_ctr_start(void); +/** + * fwu_gen_alt_info_from_mtd() - Parse dfu_alt_info from metadata in mtd + * @buf: Buffer into which the dfu_alt_info is filled + * @len: Maximum characters that can be written in buf + * @mtd: Pointer to underlying MTD device + * + * Parse dfu_alt_info from metadata in mtd. Used for setting the env. + * + * Return: 0 if OK, -ve on error + */ +int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd); + +/** + * fwu_mtd_get_alt_num() - Mapping of fwu_plat_get_alt_num for MTD device + * @image_guid: Image GUID for which DFU alt number needs to be retrieved + * @alt_num: Pointer to the alt_num + * @mtd_dev: Name of mtd device instance + * + * To map fwu_plat_get_alt_num onto mtd based metadata implementation. + * + * Return: 0 if OK, -ve on error + */ +int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev); + #endif /* _FWU_H_ */ diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h index 8fda4f4ac2..56189e2f40 100644 --- a/include/fwu_mdata.h +++ b/include/fwu_mdata.h @@ -6,6 +6,7 @@ #if !defined _FWU_MDATA_H_ #define _FWU_MDATA_H_ +#include <linux/compiler_attributes.h> #include <efi.h> /** @@ -22,7 +23,7 @@ struct fwu_image_bank_info { efi_guid_t image_uuid; uint32_t accepted; uint32_t reserved; -}; +} __packed; /** * struct fwu_image_entry - information for a particular type of image @@ -38,7 +39,7 @@ struct fwu_image_entry { efi_guid_t image_type_uuid; efi_guid_t location_uuid; struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS]; -}; +} __packed; /** * struct fwu_mdata - FWU metadata structure for multi-bank updates @@ -62,6 +63,6 @@ struct fwu_mdata { uint32_t previous_active_index; struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK]; -}; +} __packed; #endif /* _FWU_MDATA_H_ */ diff --git a/include/imx_sip.h b/include/imx_sip.h index 1b873f231b..ebbb3a16d7 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -4,7 +4,7 @@ */ #ifndef _IMX_SIP_H__ -#define _IMX_SIP_H_ +#define _IMX_SIP_H__ #define IMX_SIP_GPC 0xC2000000 #define IMX_SIP_GPC_PM_DOMAIN 0x03 diff --git a/include/lcd_console.h b/include/lcd_console.h deleted file mode 100644 index 061a6a41bb..0000000000 --- a/include/lcd_console.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ - */ - -/* By default we scroll by a single line */ - -struct console_t { - short curr_col, curr_row; - short cols, rows; - void *fbbase; - u32 lcdsizex, lcdsizey, lcdrot; - void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c); - void (*fp_console_moverow)(struct console_t *pcons, - u32 rowdst, u32 rowsrc); - void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr); -}; - -/** - * console_calc_rowcol() - calculate available rows / columns wihtin a given - * screen-size based on used VIDEO_FONT. - * - * @pcons: Pointer to struct console_t - * @sizex: size X of the screen in pixel - * @sizey: size Y of the screen in pixel - */ -void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey); -/** - * lcd_init_console() - Initialize lcd console parameters - * - * Setup the address of console base, and the number of rows and columns the - * console has. - * - * @address: Console base address - * @vl_rows: Number of rows in the console - * @vl_cols: Number of columns in the console - * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise - */ -void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot); -/** - * lcd_set_col() - Set the number of the current lcd console column - * - * Set the number of the console column where the cursor is. - * - * @col: Column number - */ -void lcd_set_col(short col); - -/** - * lcd_set_row() - Set the number of the current lcd console row - * - * Set the number of the console row where the cursor is. - * - * @row: Row number - */ -void lcd_set_row(short row); - -/** - * lcd_position_cursor() - Position the cursor on the screen - * - * Position the cursor at the given coordinates on the screen. - * - * @col: Column number - * @row: Row number - */ -void lcd_position_cursor(unsigned col, unsigned row); - -/** - * lcd_get_screen_rows() - Get the total number of screen rows - * - * @return: Number of screen rows - */ -int lcd_get_screen_rows(void); - -/** - * lcd_get_screen_columns() - Get the total number of screen columns - * - * @return: Number of screen columns - */ -int lcd_get_screen_columns(void); - -/** - * lcd_putc() - Print to screen a single character at the location of the cursor - * - * @c: The character to print - */ -void lcd_putc(const char c); - -/** - * lcd_puts() - Print to screen a string at the location of the cursor - * - * @s: The string to print - */ -void lcd_puts(const char *s); - -/** - * lcd_printf() - Print to screen a formatted string at location of the cursor - * - * @fmt: The formatted string to print - * @...: The arguments for the formatted string - */ -void lcd_printf(const char *fmt, ...); diff --git a/include/lcdvideo.h b/include/lcdvideo.h deleted file mode 100644 index f0640a5385..0000000000 --- a/include/lcdvideo.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * MPC823 LCD and Video Controller - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - */ -#ifndef __LCDVIDEO_H__ -#define __LCDVIDEO_H__ - - -/* LCD Controller Configuration Register. -*/ -#define LCCR_BNUM ((uint)0xfffe0000) -#define LCCR_EIEN ((uint)0x00010000) -#define LCCR_IEN ((uint)0x00008000) -#define LCCR_IRQL ((uint)0x00007000) -#define LCCR_CLKP ((uint)0x00000800) -#define LCCR_OEP ((uint)0x00000400) -#define LCCR_HSP ((uint)0x00000200) -#define LCCR_VSP ((uint)0x00000100) -#define LCCR_DP ((uint)0x00000080) -#define LCCR_BPIX ((uint)0x00000060) -#define LCCR_LBW ((uint)0x00000010) -#define LCCR_SPLT ((uint)0x00000008) -#define LCCR_CLOR ((uint)0x00000004) -#define LCCR_TFT ((uint)0x00000002) -#define LCCR_PON ((uint)0x00000001) - -/* Define the bit shifts to load values into the register. -*/ -#define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT)) - -#define LCCR_BNUM_BIT ((uint)14) -#define LCCR_EIEN_BIT ((uint)15) -#define LCCR_IEN_BIT ((uint)16) -#define LCCR_IROL_BIT ((uint)19) -#define LCCR_CLKP_BIT ((uint)20) -#define LCCR_OEP_BIT ((uint)21) -#define LCCR_HSP_BIT ((uint)22) -#define LCCR_VSP_BIT ((uint)23) -#define LCCR_DP_BIT ((uint)24) -#define LCCR_BPIX_BIT ((uint)26) -#define LCCR_LBW_BIT ((uint)27) -#define LCCR_SPLT_BIT ((uint)28) -#define LCCR_CLOR_BIT ((uint)29) -#define LCCR_TFT_BIT ((uint)30) -#define LCCR_PON_BIT ((uint)31) - -/* LCD Horizontal control register. -*/ -#define LCHCR_BO ((uint)0x01000000) -#define LCHCR_AT ((uint)0x00e00000) -#define LCHCR_HPC ((uint)0x001ffc00) -#define LCHCR_WBL ((uint)0x000003ff) - -#define LCHCR_AT_BIT ((uint)10) -#define LCHCR_HPC_BIT ((uint)21) -#define LCHCR_WBL_BIT ((uint)31) - -/* LCD Vertical control register. -*/ -#define LCVCR_VPW ((uint)0xf0000000) -#define LCVCR_LCD_AC ((uint)0x01e00000) -#define LCVCR_VPC ((uint)0x001ff800) -#define LCVCR_WBF ((uint)0x000003ff) - -#define LCVCR_VPW_BIT ((uint)3) -#define LCVCR_LCD_AC_BIT ((uint)10) -#define LCVCR_VPC_BIT ((uint)20) - -#endif /* __LCDVIDEO_H__ */ diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h index 9c7088bafa..20c2dc7f4b 100644 --- a/include/linux/build_bug.h +++ b/include/linux/build_bug.h @@ -4,15 +4,16 @@ #include <linux/compiler.h> #ifdef __CHECKER__ -#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) -#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) #define BUILD_BUG_ON_ZERO(e) (0) -#define BUILD_BUG_ON_NULL(e) ((void *)0) -#define BUILD_BUG_ON_INVALID(e) (0) -#define BUILD_BUG_ON_MSG(cond, msg) (0) -#define BUILD_BUG_ON(condition) (0) -#define BUILD_BUG() (0) #else /* __CHECKER__ */ +/* + * Force a compilation error if condition is true, but also produce a + * result (of value 0 and type int), so the expression can be used + * e.g. in a structure initializer (or where-ever else comma expressions + * aren't permitted). + */ +#define BUILD_BUG_ON_ZERO(e) ((int)sizeof(struct { int:(-!!(e)); })) +#endif /* __CHECKER__ */ /* Force a compilation error if a constant expression is not a power of 2 */ #define __BUILD_BUG_ON_NOT_POWER_OF_2(n) \ @@ -21,15 +22,6 @@ BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0)) /* - * Force a compilation error if condition is true, but also produce a - * result (of value 0 and type size_t), so the expression can be used - * e.g. in a structure initializer (or where-ever else comma expressions - * aren't permitted). - */ -#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); })) -#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); })) - -/* * BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the * expression but avoids the generation of any code, even if that expression * has side-effects. @@ -52,23 +44,9 @@ * If you have some code which relies on certain constants being equal, or * some other compile-time-evaluated condition, you should use BUILD_BUG_ON to * detect if someone changes it. - * - * The implementation uses gcc's reluctance to create a negative array, but gcc - * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to - * inline functions). Luckily, in 4.3 they added the "error" function - * attribute just for this type of case. Thus, we use a negative sized array - * (should always create an error on gcc versions older than 4.4) and then call - * an undefined function with the error attribute (should always create an - * error on gcc 4.3 and later). If for some reason, neither creates a - * compile-time error, we'll still have a link-time error, which is harder to - * track down. */ -#ifndef __OPTIMIZE__ -#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) -#else #define BUILD_BUG_ON(condition) \ BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) -#endif /** * BUILD_BUG - break compile if used. @@ -98,6 +76,4 @@ #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) #define __static_assert(expr, msg, ...) _Static_assert(expr, msg) -#endif /* __CHECKER__ */ - #endif /* _LINUX_BUILD_BUG_H */ diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h deleted file mode 100644 index 0644d92b3c..0000000000 --- a/include/linux/mc146818rtc.h +++ /dev/null @@ -1,86 +0,0 @@ -/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM - * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 - * derived from Data Sheet, Copyright Motorola 1984 (!). - * It was written to be part of the Linux operating system. - */ -/* permission is hereby granted to copy, modify and redistribute this code - * in terms of the GNU Library General Public License, Version 2 or later, - * at your option. - */ - -#ifndef _MC146818RTC_H -#define _MC146818RTC_H - -#include <asm/io.h> -#include <linux/rtc.h> /* get the user-level API */ -#include <asm/mc146818rtc.h> /* register access macros */ - -/********************************************************************** - * register summary - **********************************************************************/ -#define RTC_SECONDS 0 -#define RTC_SECONDS_ALARM 1 -#define RTC_MINUTES 2 -#define RTC_MINUTES_ALARM 3 -#define RTC_HOURS 4 -#define RTC_HOURS_ALARM 5 -/* RTC_*_alarm is always true if 2 MSBs are set */ -# define RTC_ALARM_DONT_CARE 0xC0 - -#define RTC_DAY_OF_WEEK 6 -#define RTC_DAY_OF_MONTH 7 -#define RTC_MONTH 8 -#define RTC_YEAR 9 - -/* control registers - Moto names - */ -#define RTC_REG_A 10 -#define RTC_REG_B 11 -#define RTC_REG_C 12 -#define RTC_REG_D 13 - -/********************************************************************** - * register details - **********************************************************************/ -#define RTC_FREQ_SELECT RTC_REG_A - -/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, - * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, - * totalling to a max high interval of 2.228 ms. - */ -# define RTC_UIP 0x80 -# define RTC_DIV_CTL 0x70 - /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ -# define RTC_REF_CLCK_4MHZ 0x00 -# define RTC_REF_CLCK_1MHZ 0x10 -# define RTC_REF_CLCK_32KHZ 0x20 - /* 2 values for divider stage reset, others for "testing purposes only" */ -# define RTC_DIV_RESET1 0x60 -# define RTC_DIV_RESET2 0x70 - /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ -# define RTC_RATE_SELECT 0x0F - -/**********************************************************************/ -#define RTC_CONTROL RTC_REG_B -# define RTC_SET 0x80 /* disable updates for clock setting */ -# define RTC_PIE 0x40 /* periodic interrupt enable */ -# define RTC_AIE 0x20 /* alarm interrupt enable */ -# define RTC_UIE 0x10 /* update-finished interrupt enable */ -# define RTC_SQWE 0x08 /* enable square-wave output */ -# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -/**********************************************************************/ -#define RTC_INTR_FLAGS RTC_REG_C -/* caution - cleared by read */ -# define RTC_IRQF 0x80 /* any of the following 3 is active */ -# define RTC_PF 0x40 -# define RTC_AF 0x20 -# define RTC_UF 0x10 - -/**********************************************************************/ -#define RTC_VALID RTC_REG_D -# define RTC_VRT 0x80 /* valid RAM and time */ -/**********************************************************************/ -#endif /* _MC146818RTC_H */ diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h deleted file mode 100644 index a72cb7d20b..0000000000 --- a/include/linux/mtd/doc2000.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Linux driver for Disk-On-Chip devices - * - * Copyright © 1999 Machine Vision Holdings, Inc. - * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> - * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com> - * Copyright © 2002-2003 SnapGear Inc - * - */ - -#ifndef __MTD_DOC2000_H__ -#define __MTD_DOC2000_H__ - -#include <linux/mtd/mtd.h> -#if 0 -#include <linux/mutex.h> -#endif - -#define DoC_Sig1 0 -#define DoC_Sig2 1 - -#define DoC_ChipID 0x1000 -#define DoC_DOCStatus 0x1001 -#define DoC_DOCControl 0x1002 -#define DoC_FloorSelect 0x1003 -#define DoC_CDSNControl 0x1004 -#define DoC_CDSNDeviceSelect 0x1005 -#define DoC_ECCConf 0x1006 -#define DoC_2k_ECCStatus 0x1007 - -#define DoC_CDSNSlowIO 0x100d -#define DoC_ECCSyndrome0 0x1010 -#define DoC_ECCSyndrome1 0x1011 -#define DoC_ECCSyndrome2 0x1012 -#define DoC_ECCSyndrome3 0x1013 -#define DoC_ECCSyndrome4 0x1014 -#define DoC_ECCSyndrome5 0x1015 -#define DoC_AliasResolution 0x101b -#define DoC_ConfigInput 0x101c -#define DoC_ReadPipeInit 0x101d -#define DoC_WritePipeTerm 0x101e -#define DoC_LastDataRead 0x101f -#define DoC_NOP 0x1020 - -#define DoC_Mil_CDSN_IO 0x0800 -#define DoC_2k_CDSN_IO 0x1800 - -#define DoC_Mplus_NOP 0x1002 -#define DoC_Mplus_AliasResolution 0x1004 -#define DoC_Mplus_DOCControl 0x1006 -#define DoC_Mplus_AccessStatus 0x1008 -#define DoC_Mplus_DeviceSelect 0x1008 -#define DoC_Mplus_Configuration 0x100a -#define DoC_Mplus_OutputControl 0x100c -#define DoC_Mplus_FlashControl 0x1020 -#define DoC_Mplus_FlashSelect 0x1022 -#define DoC_Mplus_FlashCmd 0x1024 -#define DoC_Mplus_FlashAddress 0x1026 -#define DoC_Mplus_FlashData0 0x1028 -#define DoC_Mplus_FlashData1 0x1029 -#define DoC_Mplus_ReadPipeInit 0x102a -#define DoC_Mplus_LastDataRead 0x102c -#define DoC_Mplus_LastDataRead1 0x102d -#define DoC_Mplus_WritePipeTerm 0x102e -#define DoC_Mplus_ECCSyndrome0 0x1040 -#define DoC_Mplus_ECCSyndrome1 0x1041 -#define DoC_Mplus_ECCSyndrome2 0x1042 -#define DoC_Mplus_ECCSyndrome3 0x1043 -#define DoC_Mplus_ECCSyndrome4 0x1044 -#define DoC_Mplus_ECCSyndrome5 0x1045 -#define DoC_Mplus_ECCConf 0x1046 -#define DoC_Mplus_Toggle 0x1046 -#define DoC_Mplus_DownloadStatus 0x1074 -#define DoC_Mplus_CtrlConfirm 0x1076 -#define DoC_Mplus_Power 0x1fff - -/* How to access the device? - * On ARM, it'll be mmap'd directly with 32-bit wide accesses. - * On PPC, it's mmap'd and 16-bit wide. - * Others use readb/writeb - */ -#if defined(__arm__) -#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)))) -#define WriteDOC_(d, adr, reg) do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0) -#define DOC_IOREMAP_LEN 0x8000 -#elif defined(__ppc__) -#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)))) -#define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0) -#define DOC_IOREMAP_LEN 0x4000 -#else -#define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg)) -#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg)) -#define DOC_IOREMAP_LEN 0x2000 - -#endif - -#if defined(__i386__) || defined(__x86_64__) -#define USE_MEMCPY -#endif - -/* These are provided to directly use the DoC_xxx defines */ -#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg) -#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg) - -#define DOC_MODE_RESET 0 -#define DOC_MODE_NORMAL 1 -#define DOC_MODE_RESERVED1 2 -#define DOC_MODE_RESERVED2 3 - -#define DOC_MODE_CLR_ERR 0x80 -#define DOC_MODE_RST_LAT 0x10 -#define DOC_MODE_BDECT 0x08 -#define DOC_MODE_MDWREN 0x04 - -#define DOC_ChipID_Doc2k 0x20 -#define DOC_ChipID_Doc2kTSOP 0x21 /* internal number for MTD */ -#define DOC_ChipID_DocMil 0x30 -#define DOC_ChipID_DocMilPlus32 0x40 -#define DOC_ChipID_DocMilPlus16 0x41 - -#define CDSN_CTRL_FR_B 0x80 -#define CDSN_CTRL_FR_B0 0x40 -#define CDSN_CTRL_FR_B1 0x80 - -#define CDSN_CTRL_ECC_IO 0x20 -#define CDSN_CTRL_FLASH_IO 0x10 -#define CDSN_CTRL_WP 0x08 -#define CDSN_CTRL_ALE 0x04 -#define CDSN_CTRL_CLE 0x02 -#define CDSN_CTRL_CE 0x01 - -#define DOC_ECC_RESET 0 -#define DOC_ECC_ERROR 0x80 -#define DOC_ECC_RW 0x20 -#define DOC_ECC__EN 0x08 -#define DOC_TOGGLE_BIT 0x04 -#define DOC_ECC_RESV 0x02 -#define DOC_ECC_IGNORE 0x01 - -#define DOC_FLASH_CE 0x80 -#define DOC_FLASH_WP 0x40 -#define DOC_FLASH_BANK 0x02 - -/* We have to also set the reserved bit 1 for enable */ -#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV) -#define DOC_ECC_DIS (DOC_ECC_RESV) - -struct Nand { - char floor, chip; - unsigned long curadr; - unsigned char curmode; - /* Also some erase/write/pipeline info when we get that far */ -}; - -#define MAX_FLOORS 4 -#define MAX_CHIPS 4 - -#define MAX_FLOORS_MIL 1 -#define MAX_CHIPS_MIL 1 - -#define MAX_FLOORS_MPLUS 2 -#define MAX_CHIPS_MPLUS 1 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -struct DiskOnChip { - unsigned long physadr; - void __iomem *virtadr; - unsigned long totlen; - unsigned char ChipID; /* Type of DiskOnChip */ - int ioreg; - - unsigned long mfr; /* Flash IDs - only one type of flash per device */ - unsigned long id; - int chipshift; - char page256; - char pageadrlen; - char interleave; /* Internal interleaving - Millennium Plus style */ - unsigned long erasesize; - - int curfloor; - int curchip; - - int numchips; - struct Nand *chips; - struct mtd_info *nextdoc; -/* XXX U-BOOT XXX */ -#if 0 - struct mutex lock; -#endif -}; - -int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]); - -/* XXX U-BOOT XXX */ -#if 1 -/* - * NAND Flash Manufacturer ID Codes - */ -#define NAND_MFR_TOSHIBA 0x98 -#define NAND_MFR_SAMSUNG 0xec -#endif - -#endif /* __MTD_DOC2000_H__ */ diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h deleted file mode 100644 index d0558a9826..0000000000 --- a/include/linux/mtd/ndfc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * linux/include/linux/mtd/ndfc.h - * - * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Info: - * Contains defines, datastructures for ndfc nand controller - * - */ -#ifndef __LINUX_MTD_NDFC_H -#define __LINUX_MTD_NDFC_H - -/* NDFC Register definitions */ -#define NDFC_CMD 0x00 -#define NDFC_ALE 0x04 -#define NDFC_DATA 0x08 -#define NDFC_ECC 0x10 -#define NDFC_BCFG0 0x30 -#define NDFC_BCFG1 0x34 -#define NDFC_BCFG2 0x38 -#define NDFC_BCFG3 0x3c -#define NDFC_CCR 0x40 -#define NDFC_STAT 0x44 -#define NDFC_HWCTL 0x48 -#define NDFC_REVID 0x50 - -#define NDFC_STAT_IS_READY 0x01000000 - -#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ -#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ -#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ -#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ -#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ -#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ -#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ -#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ -#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ -#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ -#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ -#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ -#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ -#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ -#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ -#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ - -#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ -#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ -#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ -#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ -#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ - -#define NDFC_MAX_BANKS 4 - -struct ndfc_controller_settings { - uint32_t ccr_settings; - uint64_t ndfc_erpn; -}; - -struct ndfc_chip_settings { - uint32_t bank_settings; -}; - -#endif diff --git a/include/linux/stddef.h b/include/linux/stddef.h index a7f546fdfe..c732eef65a 100644 --- a/include/linux/stddef.h +++ b/include/linux/stddef.h @@ -14,13 +14,7 @@ #include <linux/types.h> #endif -#ifndef __CHECKER__ #undef offsetof -#ifdef __compiler_offsetof -#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER) -#else -#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER) -#endif -#endif +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif diff --git a/include/linux/unaligned/access_ok.h b/include/linux/unaligned/access_ok.h deleted file mode 100644 index 5f46eee23c..0000000000 --- a/include/linux/unaligned/access_ok.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _LINUX_UNALIGNED_ACCESS_OK_H -#define _LINUX_UNALIGNED_ACCESS_OK_H - -#include <asm/byteorder.h> - -static inline u16 get_unaligned_le16(const void *p) -{ - return le16_to_cpup((__le16 *)p); -} - -static inline u32 get_unaligned_le32(const void *p) -{ - return le32_to_cpup((__le32 *)p); -} - -static inline u64 get_unaligned_le64(const void *p) -{ - return le64_to_cpup((__le64 *)p); -} - -static inline u16 get_unaligned_be16(const void *p) -{ - return be16_to_cpup((__be16 *)p); -} - -static inline u32 get_unaligned_be32(const void *p) -{ - return be32_to_cpup((__be32 *)p); -} - -static inline u64 get_unaligned_be64(const void *p) -{ - return be64_to_cpup((__be64 *)p); -} - -static inline void put_unaligned_le16(u16 val, void *p) -{ - *((__le16 *)p) = cpu_to_le16(val); -} - -static inline void put_unaligned_le32(u32 val, void *p) -{ - *((__le32 *)p) = cpu_to_le32(val); -} - -static inline void put_unaligned_le64(u64 val, void *p) -{ - *((__le64 *)p) = cpu_to_le64(val); -} - -static inline void put_unaligned_be16(u16 val, void *p) -{ - *((__be16 *)p) = cpu_to_be16(val); -} - -static inline void put_unaligned_be32(u32 val, void *p) -{ - *((__be32 *)p) = cpu_to_be32(val); -} - -static inline void put_unaligned_be64(u64 val, void *p) -{ - *((__be64 *)p) = cpu_to_be64(val); -} - -#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */ diff --git a/include/linux_logo.h b/include/linux_logo.h deleted file mode 100644 index 9aa712eb4e..0000000000 --- a/include/linux_logo.h +++ /dev/null @@ -1,1445 +0,0 @@ -/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $ - * include/linux/linux_logo.h: This is a linux logo - * to be displayed on boot. - * - * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu) - * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) - * - * You can put anything here, but: - * LINUX_LOGO_COLORS has to be less than 224 - * image size has to be 80x80 - * values have to start from 0x20 - * (i.e. RGB(linux_logo_red[0], - * linux_logo_green[0], - * linux_logo_blue[0]) is color 0x20) - * BW image has to be 80x80 as well, with MS bit - * on the left - * Serial_console ascii image can be any size, - * but should contain %s to display the version - */ - -#if LINUX_LOGO_COLORS == 214 - -unsigned char linux_logo_red[] __initdata = { - 0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9, - 0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6, - 0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2, - 0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54, - 0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74, - 0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E, - 0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38, - 0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3, - 0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA, - 0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC, - 0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B, - 0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52, - 0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2, - 0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6, - 0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF, - 0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46, - 0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6, - 0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA, - 0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E, - 0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7, - 0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4, - 0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA, - 0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59, - 0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB, - 0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6, - 0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72, - 0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4 -}; - -unsigned char linux_logo_green[] __initdata = { - 0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5, - 0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86, - 0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96, - 0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54, - 0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74, - 0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42, - 0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24, - 0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C, - 0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2, - 0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D, - 0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E, - 0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A, - 0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE, - 0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE, - 0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB, - 0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E, - 0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E, - 0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A, - 0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62, - 0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6, - 0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA, - 0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6, - 0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45, - 0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92, - 0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA, - 0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56, - 0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE -}; - -unsigned char linux_logo_blue[] __initdata = { - 0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7, - 0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20, - 0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40, - 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0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C, - 0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C, - 0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24, - 0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7 -}; - -unsigned char linux_logo[] __initdata = { - 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C, - 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95, - 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, - 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6, - 0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55, - 0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A, - 0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, - 0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, - 0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, - 0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, - 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95, - 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB, - 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C, - 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C, - 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C, - 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6, - 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0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD, - 0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1, - 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94, - 0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95, - 0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1, - 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95, - 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C, - 0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C, - 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95, - 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF, - 0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1, - 0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70, - 0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55, - 0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1, - 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55, - 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95, - 0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95, - 0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95, - 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1, - 0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D, - 0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, - 0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB, - 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, - 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95, - 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95, - 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, - 0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C, - 0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, - 0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, - 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55, - 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, - 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95, - 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6, - 0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55, - 0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95, - 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, - 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, - 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, - 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, - 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55 -}; - -#endif - -#ifdef INCLUDE_LINUX_LOGOBW - -unsigned char linux_logo_bw[] __initdata = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, - 0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, - 0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, - 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7, - 0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, - 0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, - 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4, - 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C, - 0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF, - 0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF, - 0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29, - 0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F, - 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00, - 0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, - 0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF, - 0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19, - 0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E, - 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00, - 0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, - 0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF, - 0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11, - 0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06, - 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00, - 0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1, - 0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF, - 0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10, - 0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00, - 0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00, - 0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7, - 0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, - 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0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61, - 0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58, - 0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55, - 0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68, - 0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68, - 0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66, - 0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88, - 0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55, - 0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66, - 0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68, - 0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66, - 0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88, - 0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85, - 0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68, - 0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88, - 0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a -}; - -#endif diff --git a/include/lxt971a.h b/include/lxt971a.h deleted file mode 100644 index a5dd82b62a..0000000000 --- a/include/lxt971a.h +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $ - * @Author: Markus Pietrek - * @References: [1] NS9750 Hardware Reference, December 2003 - * [2] Intel LXT971 Datasheet #249414 Rev. 02 - * [3] NS7520 Linux Ethernet Driver - */ - -#ifndef __LXT971A_H__ -#define __LXT971A_H__ - -/* PHY definitions (LXT971A) [2] */ -#define PHY_LXT971_PORT_CFG (0x10) -#define PHY_LXT971_STAT2 (0x11) -#define PHY_LXT971_INT_ENABLE (0x12) -#define PHY_LXT971_INT_STATUS (0x13) -#define PHY_LXT971_LED_CFG (0x14) -#define PHY_LXT971_DIG_CFG (0x1A) -#define PHY_LXT971_TX_CTRL (0x1E) - -/* PORT_CFG Port Configuration Register Bit Fields */ -#define PHY_LXT971_PORT_CFG_RES1 (0x8000) -#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) -#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000) -#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000) -#define PHY_LXT971_PORT_CFG_RES2 (0x0800) -#define PHY_LXT971_PORT_CFG_JABBER (0x0400) -#define PHY_LXT971_PORT_CFG_SQE (0x0200) -#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100) -#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080) -#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040) -#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020) -#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018) -#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010) -#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001) -#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000) -#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004) -#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002) -#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001) - -/* STAT2 Status Register #2 Bit Fields */ -#define PHY_LXT971_STAT2_RES1 (0x8000) -#define PHY_LXT971_STAT2_100BTX (0x4000) -#define PHY_LXT971_STAT2_TX_STATUS (0x2000) -#define PHY_LXT971_STAT2_RX_STATUS (0x1000) -#define PHY_LXT971_STAT2_COL_STATUS (0x0800) -#define PHY_LXT971_STAT2_LINK (0x0400) -#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200) -#define PHY_LXT971_STAT2_AUTO_NEG (0x0100) -#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080) -#define PHY_LXT971_STAT2_RES2 (0x0040) -#define PHY_LXT971_STAT2_POLARITY (0x0020) -#define PHY_LXT971_STAT2_PAUSE (0x0010) -#define PHY_LXT971_STAT2_ERROR (0x0008) -#define PHY_LXT971_STAT2_RES3 (0x0007) - -/* INT_ENABLE Interrupt Enable Register Bit Fields */ -#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00) -#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080) -#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040) -#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020) -#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010) -#define PHY_LXT971_INT_ENABLE_RES2 (0x000C) -#define PHY_LXT971_INT_ENABLE_INTEN (0x0002) -#define PHY_LXT971_INT_ENABLE_TINT (0x0001) - -/* INT_STATUS Interrupt Status Register Bit Fields */ -#define PHY_LXT971_INT_STATUS_RES1 (0xFF00) -#define PHY_LXT971_INT_STATUS_ANDONE (0x0080) -#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040) -#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020) -#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010) -#define PHY_LXT971_INT_STATUS_RES2 (0x0008) -#define PHY_LXT971_INT_STATUS_MDINT (0x0004) -#define PHY_LXT971_INT_STATUS_RES3 (0x0003) - -/* LED_CFG Interrupt LED Configuration Register Bit Fields */ -#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C) -#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008) -#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004) -#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C) -#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C) -#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008) -#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004) -#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000) -#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002) -#define PHY_LXT971_LED_CFG_RES1 (0x0001) - -/* only one of these values must be shifted for each SHIFT_LED? */ -#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F) -#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E) -#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D) -#define PHY_LXT971_LED_CFG_LINK_RX (0x000C) -#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B) -#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A) -#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009) -#define PHY_LXT971_LED_CFG_TEST_ON (0x0008) -#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007) -#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006) -#define PHY_LXT971_LED_CFG_DUPLEX (0x0005) -#define PHY_LXT971_LED_CFG_LINK (0x0004) -#define PHY_LXT971_LED_CFG_COLLISION (0x0003) -#define PHY_LXT971_LED_CFG_RECEIVE (0x0002) -#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001) -#define PHY_LXT971_LED_CFG_SPEED (0x0000) - -/* DIG_CFG Digitial Configuration Register Bit Fields */ -#define PHY_LXT971_DIG_CFG_RES1 (0xF000) -#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800) -#define PHY_LXT971_DIG_CFG_RES2 (0x0400) -#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200) -#define PHY_LXT971_DIG_CFG_RES3 (0x01FF) - -#define PHY_LXT971_MDIO_MAX_CLK (8000000) -#define PHY_MDIO_MAX_CLK (2500000) - -/* TX_CTRL Transmit Control Register Bit Fields - documentation is buggy for this register, therefore setting not included */ - -typedef enum -{ - PHY_NONE = 0x0000, /* no PHY detected yet */ - PHY_LXT971A = 0x0013 -} PhyType; - -#endif /* __LXT971A_H__ */ diff --git a/include/mc13783.h b/include/mc13783.h deleted file mode 100644 index c7ee03b0f9..0000000000 --- a/include/mc13783.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at - */ - - -#ifndef __MC13783_H__ -#define __MC13783_H__ - -/* REG_MODE_0 */ -#define VAUDIOEN (1 << 0) -#define VAUDIOSTBY (1 << 1) -#define VAUDIOMODE (1 << 2) -#define VIOHIEN (1 << 3) -#define VIOHISTBY (1 << 4) -#define VIOHIMODE (1 << 5) -#define VIOLOEN (1 << 6) -#define VIOLOSTBY (1 << 7) -#define VIOLOMODE (1 << 8) -#define VDIGEN (1 << 9) -#define VDIGSTBY (1 << 10) -#define VDIGMODE (1 << 11) -#define VGENEN (1 << 12) -#define VGENSTBY (1 << 13) -#define VGENMODE (1 << 14) -#define VRFDIGEN (1 << 15) -#define VRFDIGSTBY (1 << 16) -#define VRFDIGMODE (1 << 17) -#define VRFREFEN (1 << 18) -#define VRFREFSTBY (1 << 19) -#define VRFREFMODE (1 << 20) -#define VRFCPEN (1 << 21) -#define VRFCPSTBY (1 << 22) -#define VRFCPMODE (1 << 23) - -/* REG_MODE_1 */ -#define VSIMEN (1 << 0) -#define VSIMSTBY (1 << 1) -#define VSIMMODE (1 << 2) -#define VESIMEN (1 << 3) -#define VESIMSTBY (1 << 4) -#define VESIMMODE (1 << 5) -#define VCAMEN (1 << 6) -#define VCAMSTBY (1 << 7) -#define VCAMMODE (1 << 8) -#define VRFBGEN (1 << 9) -#define VRFBGSTBY (1 << 10) -#define VVIBEN (1 << 11) -#define VRF1EN (1 << 12) -#define VRF1STBY (1 << 13) -#define VRF1MODE (1 << 14) -#define VRF2EN (1 << 15) -#define VRF2STBY (1 << 16) -#define VRF2MODE (1 << 17) -#define VMMC1EN (1 << 18) -#define VMMC1STBY (1 << 19) -#define VMMC1MODE (1 << 20) -#define VMMC2EN (1 << 21) -#define VMMC2STBY (1 << 22) -#define VMMC2MODE (1 << 23) - -#endif diff --git a/include/mc34704.h b/include/mc34704.h deleted file mode 100644 index b837ddaa1d..0000000000 --- a/include/mc34704.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __MC34704_H__ -#define __MC34704_H__ - -enum { - MC34704_RESERVED0_REG = 0, /* 0x00 */ - MC34704_GENERAL1_REG, /* 0x01 */ - MC34704_GENERAL2_REG, /* 0x02 */ - MC34704_GENERAL3_REG, /* 0x03 */ - MC34704_RESERVED4_REG, /* 0x04 */ - MC34704_VGSET2_REG, /* 0x05 */ - MC34704_REG2SET1_REG, /* 0x06 */ - MC34704_REG2SET2_REG, /* 0x07 */ - MC34704_REG3SET1_REG, /* 0x08 */ - MC34704_REG3SET2_REG, /* 0x09 */ - MC34704_REG4SET1_REG, /* 0x0a */ - MC34704_REG4SET2_REG, /* 0x0b */ - MC34704_REG5SET1_REG, /* 0x0c */ - MC34704_REG5SET2_REG, /* 0x0d */ - MC34704_REG5SET3_REG, /* 0x0e */ - MC34704_RESERVEDF_REG, /* 0x0f */ - MC34704_RESERVED10_REG, /* 0x10 */ - MC34704_RESERVED11_REG, /* 0x11 */ - MC34704_RESERVED12_REG, /* 0x12 */ - MC34704_FSW2SET_REG, /* 0x13 */ - MC34704_RESERVED14_REG, /* 0x14 */ - MC34704_REG8SET1_REG, /* 0x15 */ - MC34704_REG8SET2_REG, /* 0x16 */ - MC34704_REG8SET3_REG, /* 0x17 */ - MC34704_FAULTS_REG, /* 0x18 */ - MC34704_I2CSET1, /* 0x19 */ - MC34704_NUM_OF_REGS, -}; - -/* GENERAL2 register fields */ -#define ONOFFE (1 << 0) -#define ONOFFD (1 << 1) -#define ONOFFA (1 << 3) -#define ALLOFF (1 << 4) - -#endif /* __MC34704_H__ */ diff --git a/include/mc9sdz60.h b/include/mc9sdz60.h deleted file mode 100644 index ffe376bf50..0000000000 --- a/include/mc9sdz60.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> - * - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MC9SDZ60_H -#define __ASM_ARCH_MC9SDZ60_H - -/** - * Register addresses for the MC9SDZ60 - * - * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h - * but not include/linux/mfd/mc9s08dz60/pmic.h - * - */ -enum mc9sdz60_reg { - MC9SDZ60_REG_VERSION = 0x00, - /* reserved 0x01 */ - MC9SDZ60_REG_SECS = 0x02, - MC9SDZ60_REG_MINS = 0x03, - MC9SDZ60_REG_HRS = 0x04, - MC9SDZ60_REG_DAY = 0x05, - MC9SDZ60_REG_DATE = 0x06, - MC9SDZ60_REG_MONTH = 0x07, - MC9SDZ60_REG_YEAR = 0x08, - MC9SDZ60_REG_ALARM_SECS = 0x09, - MC9SDZ60_REG_ALARM_MINS = 0x0a, - MC9SDZ60_REG_ALARM_HRS = 0x0b, - /* reserved 0x0c */ - /* reserved 0x0d */ - MC9SDZ60_REG_TS_CONTROL = 0x0e, - MC9SDZ60_REG_X_LOW = 0x0f, - MC9SDZ60_REG_Y_LOW = 0x10, - MC9SDZ60_REG_XY_HIGH = 0x11, - MC9SDZ60_REG_X_LEFT_LOW = 0x12, - MC9SDZ60_REG_X_LEFT_HIGH = 0x13, - MC9SDZ60_REG_X_RIGHT = 0x14, - MC9SDZ60_REG_Y_TOP_LOW = 0x15, - MC9SDZ60_REG_Y_TOP_HIGH = 0x16, - MC9SDZ60_REG_Y_BOTTOM = 0x17, - /* reserved 0x18 */ - /* reserved 0x19 */ - MC9SDZ60_REG_RESET_1 = 0x1a, - MC9SDZ60_REG_RESET_2 = 0x1b, - MC9SDZ60_REG_POWER_CTL = 0x1c, - MC9SDZ60_REG_DELAY_CONFIG = 0x1d, - /* reserved 0x1e */ - /* reserved 0x1f */ - MC9SDZ60_REG_GPIO_1 = 0x20, - MC9SDZ60_REG_GPIO_2 = 0x21, - MC9SDZ60_REG_KPD_1 = 0x22, - MC9SDZ60_REG_KPD_2 = 0x23, - MC9SDZ60_REG_KPD_CONTROL = 0x24, - MC9SDZ60_REG_INT_ENABLE_1 = 0x25, - MC9SDZ60_REG_INT_ENABLE_2 = 0x26, - MC9SDZ60_REG_INT_FLAG_1 = 0x27, - MC9SDZ60_REG_INT_FLAG_2 = 0x28, - MC9SDZ60_REG_DES_FLAG = 0x29, -}; - -extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg); -extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val); - -#endif /* __ASM_ARCH_MC9SDZ60_H */ diff --git a/include/mii_phy.h b/include/mii_phy.h deleted file mode 100644 index f0d3e62823..0000000000 --- a/include/mii_phy.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _MII_PHY_H_ -#define _MII_PHY_H_ - -void mii_discover_phy(void); -unsigned short mii_phy_read(unsigned short reg); -void mii_phy_write(unsigned short reg, unsigned short val); - -#endif diff --git a/include/mk48t59.h b/include/mk48t59.h deleted file mode 100644 index f95d349c17..0000000000 --- a/include/mk48t59.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - */ - -/* - * Date & Time support for the MK48T59 RTC - */ - - -#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE) - -#define RTC_PORT_ADDR0 0x70 -#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1 -#define RTC_PORT_DATA 0x76 - -/* RTC Offsets */ -#define RTC_SECONDS 0x1FF9 -#define RTC_MINUTES 0x1FFA -#define RTC_HOURS 0x1FFB -#define RTC_DAY_OF_WEEK 0x1FFC -#define RTC_DAY_OF_MONTH 0x1FFD -#define RTC_MONTH 0x1FFE -#define RTC_YEAR 0x1FFF - -#define RTC_CONTROLA 0x1FF8 -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 -#define RTC_CA_CALIB_SIGN 0x20 -#define RTC_CA_CALIB_MASK 0x1f - -#define RTC_CONTROLB 0x1FF9 -#define RTC_CB_STOP 0x80 - -#define RTC_WATCHDOG 0x1FF7 -#define RTC_WDS 0x80 -#define RTC_WD_RB_16TH 0x0 -#define RTC_WD_RB_4TH 0x1 -#define RTC_WD_RB_1 0x2 -#define RTC_WD_RB_4 0x3 - -void rtc_set_watchdog(short multi, short res); -void *nvram_read(void *dest, const short src, size_t count); -void nvram_write(short dest, const void *src, size_t count); - -#endif diff --git a/include/mpc106.h b/include/mpc106.h deleted file mode 100644 index 2157b32407..0000000000 --- a/include/mpc106.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - */ - -#ifndef _MPC106_PCI_H -#define _MPC106_PCI_H - -/* - * Defines for the MPC106 PCI Config address and data registers followed by - * defines for the standard PCI device configuration header. - */ -#define PCIDEVID_MPC106 0x0 - -/* - * MPC106 Registers - */ -#define MPC106_REG 0x80000000 - -#ifdef CONFIG_SYS_ADDRESS_MAP_A -#define MPC106_REG_ADDR 0x80000cf8 -#define MPC106_REG_DATA 0x80000cfc -#define MPC106_ISA_IO_PHYS 0x80000000 -#define MPC106_ISA_IO_BUS 0x00000000 -#define MPC106_ISA_IO_SIZE 0x00800000 -#define MPC106_PCI_IO_PHYS 0x81000000 -#define MPC106_PCI_IO_BUS 0x01000000 -#define MPC106_PCI_IO_SIZE 0x3e800000 -#define MPC106_PCI_MEM_PHYS 0xc0000000 -#define MPC106_PCI_MEM_BUS 0x00000000 -#define MPC106_PCI_MEM_SIZE 0x3f000000 -#define MPC106_PCI_MEMORY_PHYS 0x00000000 -#define MPC106_PCI_MEMORY_BUS 0x80000000 -#define MPC106_PCI_MEMORY_SIZE 0x80000000 -#else -#define MPC106_REG_ADDR 0xfec00cf8 -#define MPC106_REG_DATA 0xfee00cfc -#define MPC106_ISA_MEM_PHYS 0xfd000000 -#define MPC106_ISA_MEM_BUS 0x00000000 -#define MPC106_ISA_MEM_SIZE 0x01000000 -#define MPC106_ISA_IO_PHYS 0xfe000000 -#define MPC106_ISA_IO_BUS 0x00000000 -#define MPC106_ISA_IO_SIZE 0x00800000 -#define MPC106_PCI_IO_PHYS 0xfe800000 -#define MPC106_PCI_IO_BUS 0x00800000 -#define MPC106_PCI_IO_SIZE 0x00400000 -#define MPC106_PCI_MEM_PHYS 0x80000000 -#define MPC106_PCI_MEM_BUS 0x80000000 -#define MPC106_PCI_MEM_SIZE 0x7d000000 -#define MPC106_PCI_MEMORY_PHYS 0x00000000 -#define MPC106_PCI_MEMORY_BUS 0x00000000 -#define MPC106_PCI_MEMORY_SIZE 0x40000000 -#endif - -#define CMD_SERR 0x0100 -#define PCI_CMD_MASTER 0x0004 -#define PCI_CMD_MEMEN 0x0002 -#define PCI_CMD_IOEN 0x0001 - -#define PCI_STAT_NO_RSV_BITS 0xffff - -#define PCI_BUSNUM 0x40 -#define PCI_SUBBUSNUM 0x41 -#define PCI_DISCOUNT 0x42 - -#define PCI_PICR1 0xA8 -#define PICR1_CF_CBA(value) ((value & 0xff) << 24) -#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) -#define PICR1_PROC_TYPE_603 0x40000 -#define PICR1_PROC_TYPE_604 0x60000 -#define PICR1_MCP_EN 0x800 -#define PICR1_CF_DPARK 0x200 -#define PICR1_CF_LOOP_SNOOP 0x10 -#define PICR1_CF_L2_COPY_BACK 0x2 -#define PICR1_CF_L2_CACHE_MASK 0x3 -#define PICR1_CF_APARK 0x8 -#define PICR1_ADDRESS_MAP 0x10000 -#define PICR1_XIO_MODE 0x80000 -#define PICR1_CF_CACHE_1G 0x200000 - -#define PCI_PICR2 0xAC -#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) -#define PICR2_CF_FLUSH_L2 0x10000000 -#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) -#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) -#define PICR2_CF_INV_MODE 0x00001000 -#define PICR2_CF_MOD_HIGH 0x00020000 -#define PICR2_CF_HIT_HIGH 0x00010000 -#define PICR2_L2_SIZE_256K 0x00000000 -#define PICR2_L2_SIZE_512K 0x00000010 -#define PICR2_L2_SIZE_1MB 0x00000020 -#define PICR2_L2_EN 0x40000000 -#define PICR2_L2_UPDATE_EN 0x80000000 -#define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 -#define PICR2_CF_FAST_CASTOUT 0x00000080 -#define PICR2_CF_WDATA 0x00000001 -#define PICR2_CF_DATA_RAM_PBURST 0x00400000 - -/* - * Memory controller - */ -#define MPC106_MCCR1 0xF0 -#define MCCR1_TYPE_EDO 0x00020000 -#define MCCR1_BK0_9BITS 0x0 -#define MCCR1_BK0_10BITS 0x1 -#define MCCR1_BK0_11BITS 0x2 -#define MCCR1_BK0_12BITS 0x3 -#define MCCR1_BK1_9BITS 0x0 -#define MCCR1_BK1_10BITS 0x4 -#define MCCR1_BK1_11BITS 0x8 -#define MCCR1_BK1_12BITS 0xC -#define MCCR1_BK2_9BITS 0x00 -#define MCCR1_BK2_10BITS 0x10 -#define MCCR1_BK2_11BITS 0x20 -#define MCCR1_BK2_12BITS 0x30 -#define MCCR1_BK3_9BITS 0x00 -#define MCCR1_BK3_10BITS 0x40 -#define MCCR1_BK3_11BITS 0x80 -#define MCCR1_BK3_12BITS 0xC0 -#define MCCR1_MEMGO 0x00080000 - -#define MPC106_MCCR2 0xF4 -#define MPC106_MCCR3 0xF8 -#define MPC106_MCCR4 0xFC - -#define MPC106_MSAR1 0x80 -#define MPC106_EMSAR1 0x88 -#define MPC106_EMSAR2 0x8C -#define MPC106_MEAR1 0x90 -#define MPC106_EMEAR1 0x98 -#define MPC106_EMEAR2 0x9C - -#define MPC106_MBER 0xA0 -#define MBER_BANK0 0x1 -#define MBER_BANK1 0x2 -#define MBER_BANK2 0x4 -#define MBER_BANK3 0x8 - -#endif diff --git a/include/mpc86xx.h b/include/mpc86xx.h deleted file mode 100644 index ea8d17d557..0000000000 --- a/include/mpc86xx.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2006 Freescale Semiconductor. - * Jeffrey Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -#ifndef __MPC86xx_H__ -#define __MPC86xx_H__ - -#include <asm/fsl_lbc.h> - -#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/* - * platform register addresses - */ - -#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000) -#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008) - -/* - * l2cr values. Look in config_<BOARD>.h for the actual setup - */ -#define l2cr 1017 - -#define L2CR_L2E 0x80000000 /* bit 0 - enable */ -#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ -#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ -#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ -#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ -#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ -#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ -#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ - -#define HID0_XBSEN 0x00000100 -#define HID0_HIGH_BAT_EN 0x00800000 -#define HID0_XAEN 0x00020000 - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned long freq_processor; - unsigned long freq_systembus; - unsigned long freq_localbus; -} MPC86xx_SYS_INFO; - -#define l1icache_enable icache_enable - -void l2cache_enable(void); -void l1dcache_enable(void); - -static __inline__ unsigned long get_hid0 (void) -{ - unsigned long hid0; - asm volatile("mfspr %0, 1008" : "=r" (hid0) :); - return hid0; -} - -static __inline__ unsigned long get_hid1 (void) -{ - unsigned long hid1; - asm volatile("mfspr %0, 1009" : "=r" (hid1) :); - return hid1; -} - -static __inline__ void set_hid0 (unsigned long hid0) -{ - asm volatile("mtspr 1008, %0" : : "r" (hid0)); -} - -static __inline__ void set_hid1 (unsigned long hid1) -{ - asm volatile("mtspr 1009, %0" : : "r" (hid1)); -} - - -static __inline__ unsigned long get_l2cr (void) -{ - unsigned long l2cr_val; - asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); - return l2cr_val; -} - -void setup_ddr_bat(phys_addr_t dram_size); -extern void setup_bats(void); - -#endif /* _ASMLANGUAGE */ -#endif /* __MPC86xx_H__ */ diff --git a/include/mvmfp.h b/include/mvmfp.h deleted file mode 100644 index de86ffd5e2..0000000000 --- a/include/mvmfp.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - */ - -#ifndef __MVMFP_H -#define __MVMFP_H - -/* - * Header file for MultiFunctionPin (MFP) Configururation framework - * - * Processors Supported: - * 1. Marvell ARMADA100 Processors - * - * processor to be supported should be added here - */ - -/* - * MFP configuration is represented by a 32-bit unsigned integer - */ -#ifdef CONFIG_MVMFP_V2 -#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ - /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ - /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ - /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \ - /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \ - /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ - /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ - /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) -#else -#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ - /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ - /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ - /* bit 12 - Unused */ \ - /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \ - /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ - /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ - /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) -#endif - -/* - * to facilitate the definition, the following macros are provided - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) -#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) -#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16) - -#define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1) -#define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2) -#define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3) -#define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4) -#define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5) -#define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6) -#define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7) -#define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7) - -#define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0) -#define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0) -#define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0) -#define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0) -#define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0) - -#define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0) -#define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0) -#define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0) -#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0) -#define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0) - -#define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0) - -#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0) -#define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0) -#define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0) -#define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0) - -#define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0) -#define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0) -#define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0) -#define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0) -#define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0) - -#define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \ - | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \ - | MFP_AF_MASK) -#define MFP_EOC 0xffffffff /* indicates end-of-conf */ - -/* Functions */ -void mfp_config(u32 *mfp_cfgs); - -#endif /* __MVMFP_H */ diff --git a/include/net.h b/include/net.h index 785cb1059e..e254df7d7f 100644 --- a/include/net.h +++ b/include/net.h @@ -167,6 +167,9 @@ enum eth_recv_flags { * to the network stack. This function should fill in the * eth_pdata::enetaddr field - optional * set_promisc: Enable or Disable promiscuous mode + * get_sset_count: Number of statistics counters + * get_string: Names of the statistic counters + * get_stats: The values of the statistic counters */ struct eth_ops { int (*start)(struct udevice *dev); @@ -178,6 +181,9 @@ struct eth_ops { int (*write_hwaddr)(struct udevice *dev); int (*read_rom_hwaddr)(struct udevice *dev); int (*set_promisc)(struct udevice *dev, bool enable); + int (*get_sset_count)(struct udevice *dev); + void (*get_strings)(struct udevice *dev, u8 *data); + void (*get_stats)(struct udevice *dev, u64 *data); }; #define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops) diff --git a/include/nvmxip.h b/include/nvmxip.h new file mode 100644 index 0000000000..f4ef37725d --- /dev/null +++ b/include/nvmxip.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com> + * + * Authors: + * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> + */ + +#ifndef __DRIVER_NVMXIP_H__ +#define __DRIVER_NVMXIP_H__ + +#include <blk.h> + +#define NVMXIP_BLKDRV_NAME "nvmxip-blk" +#define NVMXIP_BLKDEV_NAME_SZ 20 + +/** + * struct nvmxip_plat - the NVMXIP driver plat + * + * @phys_base: NVM XIP device base address + * @lba_shift: block size shift count + * @lba: number of blocks + * + * The NVMXIP information read from the DT. + */ +struct nvmxip_plat { + phys_addr_t phys_base; + u32 lba_shift; + lbaint_t lba; +}; + +#endif /* __DRIVER_NVMXIP_H__ */ diff --git a/include/omap3_spi.h b/include/omap3_spi.h index cae3770583..5381431d43 100644 --- a/include/omap3_spi.h +++ b/include/omap3_spi.h @@ -46,6 +46,8 @@ #define OMAP4_MCSPI_REG_OFFSET 0x100 +#define OMAP4_MCSPI_CHAN_NB 4 + /* OMAP3 McSPI registers */ struct mcspi_channel { unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ @@ -64,7 +66,7 @@ struct mcspi { unsigned int wakeupenable; /* 0x20 */ unsigned int syst; /* 0x24 */ unsigned int modulctrl; /* 0x28 */ - struct mcspi_channel channel[4]; + struct mcspi_channel channel[OMAP4_MCSPI_CHAN_NB]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ /* channel1: 0x40 - 0x50, bus 0 & 1 */ /* channel2: 0x54 - 0x64, bus 0 & 1 */ diff --git a/include/pca9564.h b/include/pca9564.h deleted file mode 100644 index 99e8bcd9ad..0000000000 --- a/include/pca9564.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * File: include/pca9564.h - * Author: - * - * Created: 2009-06-23 - * Description: PCA9564 i2c bridge driver - * - * Modified: - * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ - * - * Bugs: - */ - -#ifndef _PCA9564_H -#define _PCA9564_H - -/* Clock speeds for the bus */ -#define PCA_CON_330kHz 0x00 -#define PCA_CON_288kHz 0x01 -#define PCA_CON_217kHz 0x02 -#define PCA_CON_146kHz 0x03 -#define PCA_CON_88kHz 0x04 -#define PCA_CON_59kHz 0x05 -#define PCA_CON_44kHz 0x06 -#define PCA_CON_36kHz 0x07 - -#define PCA_CON_AA 0x80 /* Assert Acknowledge */ -#define PCA_CON_ENSIO 0x40 /* Enable */ -#define PCA_CON_STA 0x20 /* Start */ -#define PCA_CON_STO 0x10 /* Stop */ -#define PCA_CON_SI 0x08 /* Serial Interrupt */ -#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */ - -#endif diff --git a/include/phy.h b/include/phy.h index 247223d92b..f023a3c268 100644 --- a/include/phy.h +++ b/include/phy.h @@ -224,15 +224,6 @@ static inline struct phy_device *fixed_phy_create(ofnode node) #endif /** - * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices - * @phydev: PHY device - * @dev: Ethernet device - * @interface: type of MAC-PHY interface - */ -void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, - phy_interface_t interface); - -/** * phy_connect() - Creates a PHY device for the Ethernet interface * Creates a PHY device for the PHY at the given address, if one doesn't exist * already, and associates it with the Ethernet device. diff --git a/include/power/pmic.h b/include/power/pmic.h index 70f2709bd0..636221692d 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -86,7 +86,7 @@ struct pmic { #endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ /* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ -#ifdef CONFIG_DM_PMIC +#if defined(CONFIG_DM_PMIC) || !CONFIG_IS_ENABLED(POWER_LEGACY) /** * U-Boot PMIC Framework * ===================== diff --git a/include/sja1000.h b/include/sja1000.h deleted file mode 100644 index 6ceb6f4d48..0000000000 --- a/include/sja1000.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> - * - * SJA1000 register layout for basic CAN mode - */ - -#ifndef _SJA1000_H_ -#define _SJA1000_H_ - -/* - * SJA1000 register layout in basic can mode - */ -struct sja1000_basic_s { - u8 cr; - u8 cmr; - u8 sr; - u8 ir; - u8 ac; - u8 am; - u8 btr0; - u8 btr1; - u8 oc; - u8 txb[10]; - u8 rxb[10]; - u8 unused; - u8 cdr; -}; - -/* control register */ -#define CR_RR 0x01 - -/* output control register */ -#define OC_MODE0 0x01 -#define OC_MODE1 0x02 -#define OC_POL0 0x04 -#define OC_TN0 0x08 -#define OC_TP0 0x10 -#define OC_POL1 0x20 -#define OC_TN1 0x40 -#define OC_TP1 0x80 - -#endif diff --git a/include/spl.h b/include/spl.h index 98f57328a5..658d36481d 100644 --- a/include/spl.h +++ b/include/spl.h @@ -672,6 +672,9 @@ int spl_load_image_ext(struct spl_image_info *spl_image, int spl_load_image_ext_os(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct blk_desc *block_dev, int partition); +int spl_blk_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + enum uclass_id uclass_id, int devnum, int partnum); /** * spl_early_init() - Set up device tree and driver model in SPL if enabled diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 3105928970..77bf8a8970 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -84,13 +84,6 @@ int stdio_init_tables(void); */ int stdio_add_devices(void); -/** - * stdio_init() - Sets up stdio ready for use - * - * This calls stdio_init_tables() and stdio_add_devices() - */ -int stdio_init(void); - void stdio_print_current_devices(void); /** diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h deleted file mode 100644 index 7628c33195..0000000000 --- a/include/sym53c8xx.h +++ /dev/null @@ -1,552 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * Most of these definitions are derived from - * linux/drivers/scsi/sym53c8xx_defs.h - */ - -#ifndef _SYM53C8XX_DEFS_H -#define _SYM53C8XX_DEFS_H - - -#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ - -#define SCNTL1 0x01 /* no reset */ - #define ISCON 0x10 /* connected to scsi */ - #define CRST 0x08 /* force reset */ - #define IARB 0x02 /* immediate arbitration */ - -#define SCNTL2 0x02 /* no disconnect expected */ - #define SDU 0x80 /* cmd: disconnect will raise error */ - #define CHM 0x40 /* sta: chained mode */ - #define WSS 0x08 /* sta: wide scsi send [W]*/ - #define WSR 0x01 /* sta: wide scsi received [W]*/ - -#define SCNTL3 0x03 /* cnf system clock dependent */ - #define EWS 0x08 /* cmd: enable wide scsi [W]*/ - #define ULTRA 0x80 /* cmd: ULTRA enable */ - /* bits 0-2, 7 rsvd for C1010 */ - -#define SCID 0x04 /* cnf host adapter scsi address */ - #define RRE 0x40 /* r/w:e enable response to resel. */ - #define SRE 0x20 /* r/w:e enable response to select */ - -#define SXFER 0x05 /* ### Sync speed and count */ - /* bits 6-7 rsvd for C1010 */ - -#define SDID 0x06 /* ### Destination-ID */ - -#define GPREG 0x07 /* ??? IO-Pins */ - -#define SFBR 0x08 /* ### First byte in phase */ - -#define SOCL 0x09 - #define CREQ 0x80 /* r/w: SCSI-REQ */ - #define CACK 0x40 /* r/w: SCSI-ACK */ - #define CBSY 0x20 /* r/w: SCSI-BSY */ - #define CSEL 0x10 /* r/w: SCSI-SEL */ - #define CATN 0x08 /* r/w: SCSI-ATN */ - #define CMSG 0x04 /* r/w: SCSI-MSG */ - #define CC_D 0x02 /* r/w: SCSI-C_D */ - #define CI_O 0x01 /* r/w: SCSI-I_O */ - -#define SSID 0x0a - -#define SBCL 0x0b - -#define DSTAT 0x0c - #define DFE 0x80 /* sta: dma fifo empty */ - #define MDPE 0x40 /* int: master data parity error */ - #define BF 0x20 /* int: script: bus fault */ - #define ABRT 0x10 /* int: script: command aborted */ - #define SSI 0x08 /* int: script: single step */ - #define SIR 0x04 /* int: script: interrupt instruct. */ - #define IID 0x01 /* int: script: illegal instruct. */ - -#define SSTAT0 0x0d - #define ILF 0x80 /* sta: data in SIDL register lsb */ - #define ORF 0x40 /* sta: data in SODR register lsb */ - #define OLF 0x20 /* sta: data in SODL register lsb */ - #define AIP 0x10 /* sta: arbitration in progress */ - #define LOA 0x08 /* sta: arbitration lost */ - #define WOA 0x04 /* sta: arbitration won */ - #define IRST 0x02 /* sta: scsi reset signal */ - #define SDP 0x01 /* sta: scsi parity signal */ - -#define SSTAT1 0x0e - #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ - -#define SSTAT2 0x0f - #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ - #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ - #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ - #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ - #define LDSC 0x02 /* sta: disconnect & reconnect */ - -#define DSA 0x10 /* --> Base page */ -#define DSA1 0x11 -#define DSA2 0x12 -#define DSA3 0x13 - -#define ISTAT 0x14 /* --> Main Command and status */ - #define CABRT 0x80 /* cmd: abort current operation */ - #define SRST 0x40 /* mod: reset chip */ - #define SIGP 0x20 /* r/w: message from host to ncr */ - #define SEM 0x10 /* r/w: message between host + ncr */ - #define CON 0x08 /* sta: connected to scsi */ - #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ - #define SIP 0x02 /* sta: scsi-interrupt */ - #define DIP 0x01 /* sta: host/script interrupt */ - - -#define CTEST0 0x18 -#define CTEST1 0x19 -#define CTEST2 0x1a - #define CSIGP 0x40 - /* bits 0-2,7 rsvd for C1010 */ - -#define CTEST3 0x1b - #define FLF 0x08 /* cmd: flush dma fifo */ - #define CLF 0x04 /* cmd: clear dma fifo */ - #define FM 0x02 /* mod: fetch pin mode */ - #define WRIE 0x01 /* mod: write and invalidate enable */ - /* bits 4-7 rsvd for C1010 */ - -#define DFIFO 0x20 -#define CTEST4 0x21 - #define BDIS 0x80 /* mod: burst disable */ - #define MPEE 0x08 /* mod: master parity error enable */ - -#define CTEST5 0x22 - #define DFS 0x20 /* mod: dma fifo size */ - /* bits 0-1, 3-7 rsvd for C1010 */ -#define CTEST6 0x23 - -#define DBC 0x24 /* ### Byte count and command */ -#define DNAD 0x28 /* ### Next command register */ -#define DSP 0x2c /* --> Script Pointer */ -#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ - -#define SCRATCHA 0x34 /* Temporary register a */ -#define SCRATCHA1 0x35 -#define SCRATCHA2 0x36 -#define SCRATCHA3 0x37 - -#define DMODE 0x38 - #define BL_2 0x80 /* mod: burst length shift value +2 */ - #define BL_1 0x40 /* mod: burst length shift value +1 */ - #define ERL 0x08 /* mod: enable read line */ - #define ERMP 0x04 /* mod: enable read multiple */ - #define BOF 0x02 /* mod: burst op code fetch */ - #define MAN 0x01 /* mod: manual start */ - -#define DIEN 0x39 -#define SBR 0x3a - -#define DCNTL 0x3b /* --> Script execution control */ - #define CLSE 0x80 /* mod: cache line size enable */ - #define PFF 0x40 /* cmd: pre-fetch flush */ - #define PFEN 0x20 /* mod: pre-fetch enable */ - #define SSM 0x10 /* mod: single step mode */ - #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ - #define STD 0x04 /* cmd: start dma mode */ - #define IRQD 0x02 /* mod: irq disable */ - #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ - /* bits 0-1 rsvd for C1010 */ - -#define ADDER 0x3c - -#define SIEN 0x40 /* -->: interrupt enable */ -#define SIST 0x42 /* <--: interrupt status */ - #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ - #define STO 0x0400/* sta: timeout (select) */ - #define GEN 0x0200/* sta: timeout (general) */ - #define HTH 0x0100/* sta: timeout (handshake) */ - #define MA 0x80 /* sta: phase mismatch */ - #define CMP 0x40 /* sta: arbitration complete */ - #define SEL 0x20 /* sta: selected by another device */ - #define RSL 0x10 /* sta: reselected by another device*/ - #define SGE 0x08 /* sta: gross error (over/underflow)*/ - #define UDC 0x04 /* sta: unexpected disconnect */ - #define RST 0x02 /* sta: scsi bus reset detected */ - #define PAR 0x01 /* sta: scsi parity error */ - -#define SLPAR 0x44 -#define SWIDE 0x45 -#define MACNTL 0x46 -#define GPCNTL 0x47 -#define STIME0 0x48 /* cmd: timeout for select&handshake*/ -#define STIME1 0x49 /* cmd: timeout user defined */ -#define RESPID 0x4a /* sta: Reselect-IDs */ - -#define STEST0 0x4c - -#define STEST1 0x4d - #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ - #define DBLEN 0x08 /* clock doubler running */ - #define DBLSEL 0x04 /* clock doubler selected */ - - -#define STEST2 0x4e - #define ROF 0x40 /* reset scsi offset (after gross error!) */ - #define EXT 0x02 /* extended filtering */ - -#define STEST3 0x4f - #define TE 0x80 /* c: tolerAnt enable */ - #define HSC 0x20 /* c: Halt SCSI Clock */ - #define CSF 0x02 /* c: clear scsi fifo */ - -#define SIDL 0x50 /* Lowlevel: latched from scsi data */ -#define STEST4 0x52 - #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ - #define SMODE_HVD 0x40 /* High Voltage Differential */ - #define SMODE_SE 0x80 /* Single Ended */ - #define SMODE_LVD 0xc0 /* Low Voltage Differential */ - #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ - /* bits 0-5 rsvd for C1010 */ - -#define SODL 0x54 /* Lowlevel: data out to scsi data */ - -#define SBDL 0x58 /* Lowlevel: data from scsi data */ - - -/*----------------------------------------------------------- -** -** Utility macros for the script. -** -**----------------------------------------------------------- -*/ - -#define REG(r) (r) - -/*----------------------------------------------------------- -** -** SCSI phases -** -** DT phases illegal for ncr driver. -** -**----------------------------------------------------------- -*/ - -#define SCR_DATA_OUT 0x00000000 -#define SCR_DATA_IN 0x01000000 -#define SCR_COMMAND 0x02000000 -#define SCR_STATUS 0x03000000 -#define SCR_DT_DATA_OUT 0x04000000 -#define SCR_DT_DATA_IN 0x05000000 -#define SCR_MSG_OUT 0x06000000 -#define SCR_MSG_IN 0x07000000 - -#define SCR_ILG_OUT 0x04000000 -#define SCR_ILG_IN 0x05000000 - -/*----------------------------------------------------------- -** -** Data transfer via SCSI. -** -**----------------------------------------------------------- -** -** MOVE_ABS (LEN) -** <<start address>> -** -** MOVE_IND (LEN) -** <<dnad_offset>> -** -** MOVE_TBL -** <<dnad_offset>> -** -**----------------------------------------------------------- -*/ - -#define OPC_MOVE 0x08000000 - -#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) - -#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) -#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) -#define SCR_CHMOV_TBL (0x10000000) - - -/*----------------------------------------------------------- -** -** Selection -** -**----------------------------------------------------------- -** -** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] -** <<alternate_address>> -** -** SEL_TBL | << dnad_offset>> [ | REL_JMP] -** <<alternate_address>> -** -**----------------------------------------------------------- -*/ - -#define SCR_SEL_ABS 0x40000000 -#define SCR_SEL_ABS_ATN 0x41000000 -#define SCR_SEL_TBL 0x42000000 -#define SCR_SEL_TBL_ATN 0x43000000 - - -#define SCR_JMP_REL 0x04000000 -#define SCR_ID(id) (((unsigned long)(id)) << 16) - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** WAIT_DISC -** dummy: <<alternate_address>> -** -** WAIT_RESEL -** <<alternate_address>> -** -**----------------------------------------------------------- -*/ - -#define SCR_WAIT_DISC 0x48000000 -#define SCR_WAIT_RESEL 0x50000000 - -/*----------------------------------------------------------- -** -** Bit Set / Reset -** -**----------------------------------------------------------- -** -** SET (flags {|.. }) -** -** CLR (flags {|.. }) -** -**----------------------------------------------------------- -*/ - -#define SCR_SET(f) (0x58000000 | (f)) -#define SCR_CLR(f) (0x60000000 | (f)) - -#define SCR_CARRY 0x00000400 -#define SCR_TRG 0x00000200 -#define SCR_ACK 0x00000040 -#define SCR_ATN 0x00000008 - - -/*----------------------------------------------------------- -** -** Memory to memory move -** -**----------------------------------------------------------- -** -** COPY (bytecount) -** << source_address >> -** << destination_address >> -** -** SCR_COPY sets the NO FLUSH option by default. -** SCR_COPY_F does not set this option. -** -** For chips which do not support this option, -** ncr_copy_and_bind() will remove this bit. -**----------------------------------------------------------- -*/ - -#define SCR_NO_FLUSH 0x01000000 - -#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) -#define SCR_COPY_F(n) (0xc0000000 | (n)) - -/*----------------------------------------------------------- -** -** Register move and binary operations -** -**----------------------------------------------------------- -** -** SFBR_REG (reg, op, data) reg = SFBR op data -** << 0 >> -** -** REG_SFBR (reg, op, data) SFBR = reg op data -** << 0 >> -** -** REG_REG (reg, op, data) reg = reg op data -** << 0 >> -** -**----------------------------------------------------------- -** On 810A, 860, 825A, 875, 895 and 896 chips the content -** of SFBR register can be used as data (SCR_SFBR_DATA). -** The 896 has additionnal IO registers starting at -** offset 0x80. Bit 7 of register offset is stored in -** bit 7 of the SCRIPTS instruction first DWORD. -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ - -#define SCR_SFBR_REG(reg,op,data) \ - (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_SFBR(reg,op,data) \ - (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_REG(reg,op,data) \ - (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - - -#define SCR_LOAD 0x00000000 -#define SCR_SHL 0x01000000 -#define SCR_OR 0x02000000 -#define SCR_XOR 0x03000000 -#define SCR_AND 0x04000000 -#define SCR_SHR 0x05000000 -#define SCR_ADD 0x06000000 -#define SCR_ADDC 0x07000000 - -#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ - -/*----------------------------------------------------------- -** -** FROM_REG (reg) SFBR = reg -** << 0 >> -** -** TO_REG (reg) reg = SFBR -** << 0 >> -** -** LOAD_REG (reg, data) reg = <data> -** << 0 >> -** -** LOAD_SFBR(data) SFBR = <data> -** << 0 >> -** -**----------------------------------------------------------- -*/ - -#define SCR_FROM_REG(reg) \ - SCR_REG_SFBR(reg,SCR_OR,0) - -#define SCR_TO_REG(reg) \ - SCR_SFBR_REG(reg,SCR_OR,0) - -#define SCR_LOAD_REG(reg,data) \ - SCR_REG_REG(reg,SCR_LOAD,data) - -#define SCR_LOAD_SFBR(data) \ - (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) - -/*----------------------------------------------------------- -** -** LOAD from memory to register. -** STORE from register to memory. -** -** Only supported by 810A, 860, 825A, 875, 895 and 896. -** -**----------------------------------------------------------- -** -** LOAD_ABS (LEN) -** <<start address>> -** -** LOAD_REL (LEN) (DSA relative) -** <<dsa_offset>> -** -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) -#define SCR_NO_FLUSH2 0x02000000 -#define SCR_DSA_REL2 0x10000000 - -#define SCR_LOAD_R(reg, how, n) \ - (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_STORE_R(reg, how, n) \ - (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) -#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) -#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) -#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) - -#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) -#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) -#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) -#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) - - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** JUMP [ | IFTRUE/IFFALSE ( ... ) ] -** <<address>> -** -** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] -** <<distance>> -** -** CALL [ | IFTRUE/IFFALSE ( ... ) ] -** <<address>> -** -** CALLR [ | IFTRUE/IFFALSE ( ... ) ] -** <<distance>> -** -** RETURN [ | IFTRUE/IFFALSE ( ... ) ] -** <<dummy>> -** -** INT [ | IFTRUE/IFFALSE ( ... ) ] -** <<ident>> -** -** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] -** <<ident>> -** -** Conditions: -** WHEN (phase) -** IF (phase) -** CARRYSET -** DATA (data, mask) -** -**----------------------------------------------------------- -*/ - -#define SCR_NO_OP 0x80000000 -#define SCR_JUMP 0x80080000 -#define SCR_JUMP64 0x80480000 -#define SCR_JUMPR 0x80880000 -#define SCR_CALL 0x88080000 -#define SCR_CALLR 0x88880000 -#define SCR_RETURN 0x90080000 -#define SCR_INT 0x98080000 -#define SCR_INT_FLY 0x98180000 - -#define IFFALSE(arg) (0x00080000 | (arg)) -#define IFTRUE(arg) (0x00000000 | (arg)) - -#define WHEN(phase) (0x00030000 | (phase)) -#define IF(phase) (0x00020000 | (phase)) - -#define DATA(D) (0x00040000 | ((D) & 0xff)) -#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) - -#define CARRYSET (0x00200000) - - -#define SIR_COMPLETE 0x10000000 -/* script errors */ -#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 -#define SIR_CMD_OUT_ILL_PH 0x00000002 -#define SIR_STATUS_ILL_PH 0x00000003 -#define SIR_MSG_RECEIVED 0x00000004 -#define SIR_DATA_IN_ERR 0x00000005 -#define SIR_DATA_OUT_ERR 0x00000006 -#define SIR_SCRIPT_ERROR 0x00000007 -#define SIR_MSG_OUT_NO_CMD 0x00000008 -#define SIR_MSG_OVER7 0x00000009 -/* Fly interrupt */ -#define INT_ON_FY 0x00000080 - -/* Hardware errors are defined in scsi.h */ - -#define SCSI_IDENTIFY 0xC0 - -#endif diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h deleted file mode 100644 index 6bb5cff305..0000000000 --- a/include/synopsys/dwcddr21mctl.h +++ /dev/null @@ -1,324 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin <macpaul@andestech.com> - */ - -/* - * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller - */ -#ifndef __DWCDDR21MCTL_H -#define __DWCDDR21MCTL_H - -#ifndef __ASSEMBLY__ -struct dwcddr21mctl { - unsigned int ccr; /* Controller Configuration */ - unsigned int dcr; /* DRAM Configuration */ - unsigned int iocr; /* I/O Configuration */ - unsigned int csr; /* Controller Status */ - unsigned int drr; /* DRAM refresh */ - unsigned int tpr0; /* SDRAM Timing Parameters 0 */ - unsigned int tpr1; /* SDRAM Timing Parameters 1 */ - unsigned int tpr2; /* SDRAM Timing Parameters 2 */ - unsigned int gdllcr; /* Global DLL Control */ - unsigned int dllcr[10]; /* DLL Control */ - unsigned int rslr[4]; /* Rank System Lantency */ - unsigned int rdgr[4]; /* Rank DQS Gating */ - unsigned int dqtr[9]; /* DQ Timing */ - unsigned int dqstr; /* DQS Timing */ - unsigned int dqsbtr; /* DQS_b Timing */ - unsigned int odtcr; /* ODT Configuration */ - unsigned int dtr[2]; /* Data Training */ - unsigned int dtar; /* Data Training Address */ - unsigned int rsved[82]; /* Reserved */ - unsigned int mr; /* Mode Register */ - unsigned int emr; /* Extended Mode Register */ - unsigned int emr2; /* Extended Mode Register 2 */ - unsigned int emr3; /* Extended Mode Register 3 */ - unsigned int hpcr[32]; /* Host Port Configurarion */ - unsigned int pqcr[8]; /* Priority Queue Configuration */ - unsigned int mmgcr; /* Memory Manager General Config */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Control Configuration Register - */ -#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) -#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) -#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) -#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) -#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) -#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) -#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) -#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) -#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) -#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) -#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28) -#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) -#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) -#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) - -/* - * DRAM Configuration Register - */ -#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) -#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1) -#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9) -#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12) -#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13) -#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25) -#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27) -#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31) - -/* - * I/O Configuration Register - */ -#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8) -#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26) -#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29) -#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30) -#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31) - -/* - * Controller Status Register - */ -#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0) -#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18) -#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19) -#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20) -#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21) -#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22) - -/* - * DRAM Refresh Register - */ -#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0) -#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8) -#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 0 - */ -#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2) -#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5) -#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16) -#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21) -#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25) -#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 1 - */ -#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2) -#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3) -#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14) -#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23) -#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27) -#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 2 - */ -#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0) -#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10) -#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15) - -/* - * Global DLL Control Register - */ -#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2) -#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5) -#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9) -#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11) -#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12) -#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20) -#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29) - -/* - * DLL Control Register 0-9 - */ -#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14) -#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18) -#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19) -#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31) - -/* - * Rank System Lantency Register - */ -#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24) - -/* - * Rank DQS Gating Register - */ -#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2) -#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4) -#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6) -#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8) -#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14) -#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16) - -/* - * DQ Timing Register - */ -#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16) -#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20) -#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28) - -/* - * DQS Timing Register - */ -#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24) - -/* - * DQS_b (DQSBTR) Timing Register - */ -#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24) - -/* - * ODT Configuration Register - */ -#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16) -#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20) -#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28) - -/* - * Data Training Register - */ -#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */ -#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */ -#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */ -#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */ - -#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */ -#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */ -#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */ -#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */ - -/* - * Data Training Address Register - */ -#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0) -#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12) -#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28) - -/* - * Mode Register - */ -#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_MR_BT(x) ((x) << 3) -#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4) -#define DWCDDR21MCTL_MR_TM(x) ((x) << 7) -#define DWCDDR21MCTL_MR_DR(x) ((x) << 8) -#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_MR_PD(x) ((x) << 12) - -/* - * Extended Mode register - */ -#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0) -#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1) -#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2) -#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6) -#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7) -#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10) -#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11) -#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12) - -#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x) -#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x) - -#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0)) -#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1)) -#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0)) -#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1)) - -/* - * Extended Mode register 2 - */ -#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3) -#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7) - -/* - * Extended Mode register 3: [15:0] reserved for JEDEC. - */ - -/* - * Host port Configuration register 0-31 - */ -#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0) - -/* - * Priority Queue Configuration register 0-7 - */ -#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8) -#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12) -#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20) -#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25) -#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28) - -/* - * Memory Manager General Configuration register - */ -#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0) - -#endif /* __DWCDDR21MCTL_H */ diff --git a/include/test/suites.h b/include/test/suites.h index 7349ce5aa6..1c7dc65966 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -28,6 +28,7 @@ int cmd_ut_category(const char *name, const char *prefix, int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/include/version_string.h b/include/version_string.h index a89a6e4370..a7d07e4cc7 100644 --- a/include/version_string.h +++ b/include/version_string.h @@ -4,5 +4,7 @@ #define __VERSION_STRING_H__ extern const char version_string[]; +extern const unsigned short version_num; +extern const unsigned char version_num_patch; #endif /* __VERSION_STRING_H__ */ diff --git a/include/video.h b/include/video.h index 29c4f51efb..03434a8123 100644 --- a/include/video.h +++ b/include/video.h @@ -64,6 +64,7 @@ enum video_log2_bpp { enum video_format { VIDEO_UNKNOWN, + VIDEO_RGBA8888, VIDEO_X8B8G8R8, VIDEO_X8R8G8B8, VIDEO_X2R10G10B10, diff --git a/include/video_easylogo.h b/include/video_easylogo.h deleted file mode 100644 index ce93868da0..0000000000 --- a/include/video_easylogo.h +++ /dev/null @@ -1,26 +0,0 @@ -/* -** video easylogo -** ============== -** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) -** AIRVENT SAM s.p.a - RIMINI(ITALY) -** -** This utility is still under construction! -*/ - -#ifndef _EASYLOGO_H_ -#define _EASYLOGO_H_ - -#if 0 -#define ENABLE_ASCII_BANNERS -#endif - -typedef struct { - unsigned char *data; - int width; - int height; - int bpp; - int pixel_size; - int size; -} fastimage_t ; - -#endif /* _EASYLOGO_H_ */ diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f7a4a39d35..1192d5902d 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -35,7 +35,7 @@ enum pm_api_id { PM_FPGA_LOAD = 22, PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, - /* ID 25 is been used by U-boot to process secure boot images */ + /* ID 25 is been used by U-Boot to process secure boot images */ /* Secure library generic API functions */ PM_SECURE_SHA = 26, PM_SECURE_RSA = 27, |