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-rw-r--r--include/configs/P3041DS.h18
-rw-r--r--include/configs/P4080DS.h17
-rw-r--r--include/configs/P5040DS.h13
-rw-r--r--include/configs/armadillo-800eva.h61
-rw-r--r--include/configs/cm_t335.h98
-rw-r--r--include/configs/edminiv2.h134
-rw-r--r--include/configs/km/km-mpc8309.h119
-rw-r--r--include/configs/kmtegr1.h58
-rw-r--r--include/configs/kzm9g.h57
-rw-r--r--include/configs/ls1021aqds.h8
-rw-r--r--include/configs/warp.h112
-rw-r--r--include/linux/immap_qe.h2
-rw-r--r--include/mpc83xx.h151
13 files changed, 1 insertions, 847 deletions
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
deleted file mode 100644
index 42e507bac0..0000000000
--- a/include/configs/P3041DS.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P3041 DS board configuration file
- *
- */
-#define CONFIG_SYS_DPAA_RMAN
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
deleted file mode 100644
index fd558398e4..0000000000
--- a/include/configs/P4080DS.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P4080 DS board configuration file
- * Also supports P4040 DS
- */
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
deleted file mode 100644
index c8fc879d2f..0000000000
--- a/include/configs/P5040DS.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P5040 DS board configuration file
- *
- */
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
deleted file mode 100644
index da02a96889..0000000000
--- a/include/configs/armadillo-800eva.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the bonito board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __ARMADILLO_800EVA_H
-#define __ARMADILLO_800EVA_H
-
-#define CONFIG_SH_GPIO_PFC
-
-#include <asm/arch/rmobile.h>
-
-#define BOARD_LATE_INIT
-
-#define CONFIG_TMU_TIMER
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
-
-/* STACK */
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
- (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
-
-/* MEMORY */
-#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
-#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define SCIF0_BASE 0xe6c40000
-#define SCIF1_BASE 0xe6c50000
-#define SCIF2_BASE 0xe6c60000
-#define SCIF4_BASE 0xe6c80000
-#define CONFIG_SCIF_A
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-
-/* ENV setting */
-
-/* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT 0
-#define CONFIG_SH_ETHER_PHY_ADDR 0x0
-#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
-#define CONFIG_SH_ETHER_SH7734_MII (0x01)
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#endif /* __ARMADILLO_800EVA_H */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
deleted file mode 100644
index 84b4271c36..0000000000
--- a/include/configs/cm_t335.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Config file for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#ifndef __CONFIG_CM_T335_H
-#define __CONFIG_CM_T335_H
-
-#include <configs/ti_am335x_common.h>
-
-#undef CONFIG_MAX_RAM_BANK_SIZE
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
-
-/* Clock Defines */
-#define V_OSCK 25000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-#define MMCARGS \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
- "mmcrootfstype=ext4\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0"
-
-#define NANDARGS \
- "nandroot=ubi0:rootfs rw\0" \
- "nandrootfstype=ubifs\0" \
- "nandargs=setenv bootargs console=${console} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype} " \
- "ubi.mtd=${rootfs_name}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nboot ${loadaddr} nand0 900000; " \
- "bootm ${loadaddr}\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=82000000\0" \
- "console=ttyO0,115200n8\0" \
- "rootfs_name=rootfs\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- MMCARGS \
- NANDARGS
-
-/* Serial console configuration */
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-
-/* I2C Configuration */
-
-/* SPL */
-
-/* Network. */
-
-/* NAND support */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-
-/* GPIO pin + bank to pin ID mapping */
-#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
-
-/* Status LED */
-/* Status LED polarity is inversed, so init it in the "off" state */
-
-/* EEPROM */
-
-/*
- * Enable PCA9555 at I2C0-0x26.
- * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
- */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} }
-
-#endif /* __CONFIG_CM_T335_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
deleted file mode 100644
index d2f1cd5d5c..0000000000
--- a/include/configs/edminiv2.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef _CONFIG_EDMINIV2_H
-#define _CONFIG_EDMINIV2_H
-
-/*
- * SPL
- */
-
-#define CONFIG_SYS_UBOOT_BASE 0xfff90000
-#define CONFIG_SYS_UBOOT_START 0x00800000
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#include <asm/arch/orion5x.h>
-/*
- * CLKs configurations
- */
-
-/*
- * Board-specific values for Orion5x MPP low level init:
- * - MPPs 12 to 15 are SATA LEDs (mode 5)
- * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
- * MPP16 to MPP19, mode 0 for others
- */
-
-#define ORION5X_MPP0_7 0x00000003
-#define ORION5X_MPP8_15 0x55550000
-#define ORION5X_MPP16_23 0x00005555
-
-/*
- * Board-specific values for Orion5x GPIO low level init:
- * - GPIO3 is input (RTC interrupt)
- * - GPIO16 is Power LED control (0 = on, 1 = off)
- * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
- * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
- * - GPIO22 is SATA disk power status ()
- * - GPIO23 is supply status for SATA disk ()
- * - GPIO24 is supply control for board (write 1 to power off)
- * Last GPIO is 25, further bits are supposed to be 0.
- * Enable mask has ones for INPUT, 0 for OUTPUT.
- * Default is LED ON, board ON :)
- */
-
-#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
-#define ORION5X_GPIO_OUT_VALUE 0x00000000
-#define ORION5X_GPIO_IN_POLARITY 0x000000d0
-
-/*
- * NS16550 Configuration
- */
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
-
-/*
- * FLASH configuration
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xfff80000
-
-/* auto boot */
-
-/*
- * Network
- */
-
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
-#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
-#define CONFIG_PHY_BASE_ADR 0x8
-#endif
-
-/*
- * IDE
- */
-#ifdef CONFIG_IDE
-#define __io
-/* Data, registers and alternate blocks are at the same offset */
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-/* A single bus, a single device */
-/* ATA registers base is at SATA controller base */
-/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
-/* end of IDE defines */
-#endif /* CMD_IDE */
-
-/*
- * Common USB/EHCI configuration
- */
-#ifdef CONFIG_CMD_USB
-#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
-#endif /* CONFIG_CMD_USB */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
-#endif
-
-/*
- * Environment variables configurations
- */
-
-/* Enable command line editing */
-
-/* provide extensive help */
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0
-
-#endif /* _CONFIG_EDMINIV2_H */
diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h
deleted file mode 100644
index 0468ed5e83..0000000000
--- a/include/configs/km/km-mpc8309.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-
-/* QE microcode/firmware address */
-/* between the u-boot partition and env */
-
-/*
- * System IO Config
- */
-/* 0x14000180 SICR_1 */
-#ifndef CONFIG_SYS_SICRL
-#define CONFIG_SYS_SICRL (0 \
- | SICR_1_UART1_UART1RTS \
- | SICR_1_I2C_CKSTOP \
- | SICR_1_IRQ_A_IRQ \
- | SICR_1_IRQ_B_IRQ \
- | SICR_1_GPIO_A_GPIO \
- | SICR_1_GPIO_B_GPIO \
- | SICR_1_GPIO_C_GPIO \
- | SICR_1_GPIO_D_GPIO \
- | SICR_1_GPIO_E_GPIO \
- | SICR_1_GPIO_F_GPIO \
- | SICR_1_USB_A_UART2S \
- | SICR_1_USB_B_UART2RTS \
- | SICR_1_FEC1_FEC1 \
- | SICR_1_FEC2_FEC2 \
- )
-#endif
-
-/* 0x00080400 SICR_2 */
-#define CONFIG_SYS_SICRH (0 \
- | SICR_2_FEC3_FEC3 \
- | SICR_2_HDLC1_A_HDLC1 \
- | SICR_2_ELBC_A_LA \
- | SICR_2_ELBC_B_LCLK \
- | SICR_2_HDLC2_A_HDLC2 \
- | SICR_2_USB_D_GPIO \
- | SICR_2_PCI_PCI \
- | SICR_2_HDLC1_B_HDLC1 \
- | SICR_2_HDLC1_C_HDLC1 \
- | SICR_2_HDLC2_B_GPIO \
- | SICR_2_HDLC2_C_HDLC2 \
- | SICR_2_QUIESCE_B \
- )
-
-/* GPR_1 */
-#define CONFIG_SYS_GPR1 0x50008060
-
-#define CONFIG_SYS_DDRCDR (\
- DDRCDR_EN | \
- DDRCDR_PZ_MAXZ | \
- DDRCDR_NZ_MAXZ | \
- DDRCDR_M_ODR)
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
- SDRAM_CFG_32_BE | \
- SDRAM_CFG_SREN | \
- SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ODT_RD_NEVER | \
- CSCONFIG_ODT_WR_ONLY_CURRENT | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE 0x47860242
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (7 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
-
-/* EEprom support */
-
-/* ethernet port connected to piggy (UEC2) */
-#define CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
deleted file mode 100644
index bdd35cc7fb..0000000000
--- a/include/configs/kmtegr1.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_HOSTNAME "kmtegr1"
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
-#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
-
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-
-#define CONFIG_SYS_SICRL (0 \
- | SICR_1_UART1_UART1RTS \
- | SICR_1_I2C_CKSTOP \
- | SICR_1_IRQ_A_IRQ \
- | SICR_1_IRQ_B_IRQ \
- | SICR_1_GPIO_A_GPIO \
- | SICR_1_GPIO_B_GPIO \
- | SICR_1_GPIO_C_GPIO \
- | SICR_1_GPIO_D_GPIO \
- | SICR_1_GPIO_E_LCS \
- | SICR_1_GPIO_F_GPIO \
- | SICR_1_USB_A_UART2S \
- | SICR_1_USB_B_UART2RTS \
- | SICR_1_FEC1_FEC1 \
- | SICR_1_FEC2_FEC2 \
- )
-
-/* include common defines/options for all Keymile boards */
-#include "km/keymile-common.h"
-#include "km/km-powerpc.h"
-#include "km/km-mpc83xx.h"
-#include "km/km-mpc8309.h"
-
-/* must be after the include because KMBEC_FPGA is otherwise undefined */
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
deleted file mode 100644
index 602c1c5391..0000000000
--- a/include/configs/kzm9g.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __KZM9G_H
-#define __KZM9G_H
-
-#define CONFIG_SH73A0
-
-#include <asm/arch/rmobile.h>
-
-/* MEMORY */
-#define KZM_SDRAM_BASE (0x40000000)
-#define PHYS_SDRAM KZM_SDRAM_BASE
-#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
-
-/* NOR Flash */
-#define KZM_FLASH_BASE (0x00000000)
-#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
-
-/* prompt */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
-#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
-#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
-#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
-
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
-
-/* FLASH */
-#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
-
-/* Timeout for Flash erase operations (in ms) */
-/* Timeout for Flash write operations (in ms) */
-/* Timeout for Flash set sector lock bit operations (in ms) */
-/* Timeout for Flash clear lock bit operations (in ms) */
-
-/* GPIO / PFC */
-#define CONFIG_SH_GPIO_PFC
-
-/* Clock */
-#define CONFIG_GLOBAL_TIMER
-#define CONFIG_SYS_CPU_CLK (1196000000)
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
-
-#endif /* __KZM9G_H */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d9a973c13f..aaf28a346d 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -285,14 +285,6 @@
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
-
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1b
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE 8
-#endif
-
#endif
#define CONFIG_PEN_ADDR_BIG_ENDIAN
diff --git a/include/configs/warp.h b/include/configs/warp.h
deleted file mode 100644
index d2c4391935..0000000000
--- a/include/configs/warp.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 O.S. Systems Software LTDA.
- * Copyright (C) 2014 Kynetics LLC.
- * Copyright (C) 2014 Revolution Robotics, Inc.
- *
- * Author: Otavio Salvador <otavio@ossystems.com.br>
- *
- * Configuration settings for the WaRP Board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-
-/* Watchdog */
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-/* VDD voltage 1.65 - 1.95 */
-#define CONFIG_SYS_SD_VOLTAGE 0x00000080
-
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#endif
-
-#define CONFIG_USBD_HS
-
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-
-/* I2C Configs */
-
-/* PMIC */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=imx6sl-warp.dtb\0" \
- "fdt_addr=0x88000000\0" \
- "initrd_addr=0x83800000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcpart=1\0" \
- "finduuid=part uuid mmc 0:2 uuid\0" \
- "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=PARTUUID=${uuid} rootwait rw\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run finduuid; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${image}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0"
-
-#endif /* __CONFIG_H */
diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h
index 022771fff5..45307f51c1 100644
--- a/include/linux/immap_qe.h
+++ b/include/linux/immap_qe.h
@@ -16,7 +16,7 @@
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
+#elif defined(CONFIG_ARCH_MPC832X)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 2181a90b59..5926c8090a 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -340,85 +340,6 @@
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
-#elif defined(CONFIG_ARCH_MPC8309)
-/* SICR_1 */
-#define SICR_1_UART1_UART1S (0 << (30-2))
-#define SICR_1_UART1_UART1RTS (1 << (30-2))
-#define SICR_1_I2C_I2C (0 << (30-4))
-#define SICR_1_I2C_CKSTOP (1 << (30-4))
-#define SICR_1_IRQ_A_IRQ (0 << (30-6))
-#define SICR_1_IRQ_A_MCP (1 << (30-6))
-#define SICR_1_IRQ_B_IRQ (0 << (30-8))
-#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
-#define SICR_1_GPIO_A_GPIO (0 << (30-10))
-#define SICR_1_GPIO_A_SD (2 << (30-10))
-#define SICR_1_GPIO_A_DDR (3 << (30-10))
-#define SICR_1_GPIO_B_GPIO (0 << (30-12))
-#define SICR_1_GPIO_B_SD (2 << (30-12))
-#define SICR_1_GPIO_B_QE (3 << (30-12))
-#define SICR_1_GPIO_C_GPIO (0 << (30-14))
-#define SICR_1_GPIO_C_CAN (1 << (30-14))
-#define SICR_1_GPIO_C_DDR (2 << (30-14))
-#define SICR_1_GPIO_C_LCS (3 << (30-14))
-#define SICR_1_GPIO_D_GPIO (0 << (30-16))
-#define SICR_1_GPIO_D_CAN (1 << (30-16))
-#define SICR_1_GPIO_D_DDR (2 << (30-16))
-#define SICR_1_GPIO_D_LCS (3 << (30-16))
-#define SICR_1_GPIO_E_GPIO (0 << (30-18))
-#define SICR_1_GPIO_E_CAN (1 << (30-18))
-#define SICR_1_GPIO_E_DDR (2 << (30-18))
-#define SICR_1_GPIO_E_LCS (3 << (30-18))
-#define SICR_1_GPIO_F_GPIO (0 << (30-20))
-#define SICR_1_GPIO_F_CAN (1 << (30-20))
-#define SICR_1_GPIO_F_CK (2 << (30-20))
-#define SICR_1_USB_A_USBDR (0 << (30-22))
-#define SICR_1_USB_A_UART2S (1 << (30-22))
-#define SICR_1_USB_B_USBDR (0 << (30-24))
-#define SICR_1_USB_B_UART2S (1 << (30-24))
-#define SICR_1_USB_B_UART2RTS (2 << (30-24))
-#define SICR_1_USB_C_USBDR (0 << (30-26))
-#define SICR_1_USB_C_QE_EXT (3 << (30-26))
-#define SICR_1_FEC1_FEC1 (0 << (30-28))
-#define SICR_1_FEC1_GTM (1 << (30-28))
-#define SICR_1_FEC1_GPIO (2 << (30-28))
-#define SICR_1_FEC2_FEC2 (0 << (30-30))
-#define SICR_1_FEC2_GTM (1 << (30-30))
-#define SICR_1_FEC2_GPIO (2 << (30-30))
-/* SICR_2 */
-#define SICR_2_FEC3_FEC3 (0 << (30-0))
-#define SICR_2_FEC3_TMR (1 << (30-0))
-#define SICR_2_FEC3_GPIO (2 << (30-0))
-#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
-#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
-#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
-#define SICR_2_ELBC_A_LA (0 << (30-4))
-#define SICR_2_ELBC_B_LCLK (0 << (30-6))
-#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
-#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
-#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
-/* bits 10-11 unused */
-#define SICR_2_USB_D_USBDR (0 << (30-12))
-#define SICR_2_USB_D_GPIO (2 << (30-12))
-#define SICR_2_USB_D_QE_BRG (3 << (30-12))
-#define SICR_2_PCI_PCI (0 << (30-14))
-#define SICR_2_PCI_CPCI_HS (2 << (30-14))
-#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
-#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
-#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
-#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
-#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
-#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
-#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
-#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
-#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
-#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
-#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
-#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
-#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
-#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
-#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
-#define SICR_2_QUIESCE_B (0 << (30-24))
-
#endif
/*
@@ -610,63 +531,6 @@
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_ARCH_MPC8309)
-
-#define HRCWL_CEVCOD 0x000000C0
-#define HRCWL_CEVCOD_SHIFT 6
-/*
- * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
- * these are different than with 8360, 832x
- */
-#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
-#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
-#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
-
-#define HRCWL_CEPDF 0x00000020
-#define HRCWL_CEPDF_SHIFT 5
-#define HRCWL_CE_PLL_DIV_1X1 0x00000000
-#define HRCWL_CE_PLL_DIV_2X1 0x00000020
-
-#define HRCWL_CEPMF 0x0000001F
-#define HRCWL_CEPMF_SHIFT 0
-#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
-#define HRCWL_CE_TO_PLL_1X2 0x00000002
-#define HRCWL_CE_TO_PLL_1X3 0x00000003
-#define HRCWL_CE_TO_PLL_1X4 0x00000004
-#define HRCWL_CE_TO_PLL_1X5 0x00000005
-#define HRCWL_CE_TO_PLL_1X6 0x00000006
-#define HRCWL_CE_TO_PLL_1X7 0x00000007
-#define HRCWL_CE_TO_PLL_1X8 0x00000008
-#define HRCWL_CE_TO_PLL_1X9 0x00000009
-#define HRCWL_CE_TO_PLL_1X10 0x0000000A
-#define HRCWL_CE_TO_PLL_1X11 0x0000000B
-#define HRCWL_CE_TO_PLL_1X12 0x0000000C
-#define HRCWL_CE_TO_PLL_1X13 0x0000000D
-#define HRCWL_CE_TO_PLL_1X14 0x0000000E
-#define HRCWL_CE_TO_PLL_1X15 0x0000000F
-#define HRCWL_CE_TO_PLL_1X16 0x00000010
-#define HRCWL_CE_TO_PLL_1X17 0x00000011
-#define HRCWL_CE_TO_PLL_1X18 0x00000012
-#define HRCWL_CE_TO_PLL_1X19 0x00000013
-#define HRCWL_CE_TO_PLL_1X20 0x00000014
-#define HRCWL_CE_TO_PLL_1X21 0x00000015
-#define HRCWL_CE_TO_PLL_1X22 0x00000016
-#define HRCWL_CE_TO_PLL_1X23 0x00000017
-#define HRCWL_CE_TO_PLL_1X24 0x00000018
-#define HRCWL_CE_TO_PLL_1X25 0x00000019
-#define HRCWL_CE_TO_PLL_1X26 0x0000001A
-#define HRCWL_CE_TO_PLL_1X27 0x0000001B
-#define HRCWL_CE_TO_PLL_1X28 0x0000001C
-#define HRCWL_CE_TO_PLL_1X29 0x0000001D
-#define HRCWL_CE_TO_PLL_1X30 0x0000001E
-#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-
-#define HRCWL_SVCOD 0x30000000
-#define HRCWL_SVCOD_SHIFT 28
-#define HRCWL_SVCOD_DIV_2 0x00000000
-#define HRCWL_SVCOD_DIV_4 0x10000000
-#define HRCWL_SVCOD_DIV_8 0x20000000
-#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/*
@@ -1027,21 +891,6 @@
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
-#elif defined(CONFIG_ARCH_MPC8309)
-/* SCCR bits - MPC8309 specific */
-#define SCCR_SDHCCM 0x0c000000
-#define SCCR_SDHCCM_SHIFT 26
-#define SCCR_SDHCCM_0 0x00000000
-#define SCCR_SDHCCM_1 0x04000000
-#define SCCR_SDHCCM_2 0x08000000
-#define SCCR_SDHCCM_3 0x0c000000
-
-#define SCCR_USBDRCM 0x00c00000
-#define SCCR_USBDRCM_SHIFT 22
-#define SCCR_USBDRCM_0 0x00000000
-#define SCCR_USBDRCM_1 0x00400000
-#define SCCR_USBDRCM_2 0x00800000
-#define SCCR_USBDRCM_3 0x00c00000
#endif
#define SCCR_PCIEXP1CM 0x00300000
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-30 10:45:42 +0000