diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/clk.h | 28 | ||||
| -rw-r--r-- | include/configs/boston.h | 81 | ||||
| -rw-r--r-- | include/configs/imgtec_xilfpga.h | 68 | ||||
| -rw-r--r-- | include/configs/mx6sxsabreauto.h | 1 | ||||
| -rw-r--r-- | include/configs/mx6ul_14x14_evk.h | 4 | ||||
| -rw-r--r-- | include/configs/xilinx_zynqmp.h | 39 | ||||
| -rw-r--r-- | include/configs/xilinx_zynqmp_ep.h | 1 | ||||
| -rw-r--r-- | include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h | 15 | ||||
| -rw-r--r-- | include/dt-bindings/clock/boston-clock.h | 13 | ||||
| -rw-r--r-- | include/dt-bindings/interrupt-controller/mips-gic.h | 9 | ||||
| -rw-r--r-- | include/mmc.h | 9 | ||||
| -rw-r--r-- | include/sdhci.h | 2 | ||||
| -rw-r--r-- | include/spi.h | 13 | ||||
| -rw-r--r-- | include/xilinx.h | 2 | ||||
| -rw-r--r-- | include/zynqmppl.h | 24 |
15 files changed, 257 insertions, 52 deletions
diff --git a/include/clk.h b/include/clk.h index dc18b0310a..7273127bb4 100644 --- a/include/clk.h +++ b/include/clk.h @@ -10,6 +10,7 @@ #define _CLK_H_ #include <linux/types.h> +#include <asm/errno.h> /** * A clock is a hardware signal that oscillates autonomously at a specific @@ -59,7 +60,7 @@ struct clk { unsigned long id; }; -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) struct phandle_2_cell; int clk_get_by_index_platdata(struct udevice *dev, int index, struct phandle_2_cell *cells, struct clk *clk); @@ -97,19 +98,6 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk); * @return 0 if OK, or a negative error code. */ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk); -#else -static inline int clk_get_by_index(struct udevice *dev, int index, - struct clk *clk) -{ - return -ENOSYS; -} - -static inline int clk_get_by_name(struct udevice *dev, const char *name, - struct clk *clk) -{ - return -ENOSYS; -} -#endif /** * clk_request - Request a clock by provider-specific ID. @@ -174,5 +162,17 @@ int clk_enable(struct clk *clk); int clk_disable(struct clk *clk); int soc_clk_dump(void); +#else +static inline int clk_get_by_index(struct udevice *dev, int index, + struct clk *clk) +{ + return -ENOSYS; +} +static inline int clk_get_by_name(struct udevice *dev, const char *name, + struct clk *clk) +{ + return -ENOSYS; +} +#endif #endif diff --git a/include/configs/boston.h b/include/configs/boston.h new file mode 100644 index 0000000000..e95805408a --- /dev/null +++ b/include/configs/boston.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016 Imagination Technologies + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIGS_BOSTON_H__ +#define __CONFIGS_BOSTON_H__ + +/* + * General board configuration + */ +#define CONFIG_DISPLAY_BOARDINFO + +/* + * CPU + */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000 + +/* + * PCI + */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI + +/* + * Memory map + */ +#ifdef CONFIG_64BIT +# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#else +# define CONFIG_SYS_SDRAM_BASE 0x80000000 +#endif + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000) + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) + +/* + * Console + */ +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_BAUDRATE 115200 + +/* + * Flash + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#ifdef CONFIG_64BIT +# define CONFIG_ENV_ADDR \ + (0xffffffffb8000000 + (128 << 20) - CONFIG_ENV_SIZE) +#else +# define CONFIG_ENV_ADDR \ + (0xb8000000 + (128 << 20) - CONFIG_ENV_SIZE) +#endif + +#endif /* __CONFIGS_BOSTON_H__ */ diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h new file mode 100644 index 0000000000..0a7fe60214 --- /dev/null +++ b/include/configs/imgtec_xilfpga.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2016, Imagination Technologies Ltd. + * + * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Imagination Technologies Ltd. MIPSfpga + */ + +#ifndef __XILFPGA_CONFIG_H +#define __XILFPGA_CONFIG_H + +/* BootROM + MIG is pretty smart. DDR and Cache initialized */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +/*-------------------------------------------- + * CPU configuration + */ +/* CPU Timer rate */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 + +/* Cache Configuration */ +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT + +/*---------------------------------------------------------------------- + * Memory Layout + */ + +/* SDRAM Configuration (for final code, data, stack, heap) */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) + +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ + +/*---------------------------------------------------------------------- + * Commands + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +/*------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_SYS_NO_FLASH + +/*------------------------------------------------------------ + * Console Configuration + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ +#define CONFIG_BAUDRATE 115200 + +/* ------------------------------------------------- + * Environment + */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x4000 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#endif /* __XILFPGA_CONFIG_H */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 274cb36002..c30e3dd668 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -173,7 +173,6 @@ #define CONFIG_IMX_THERMAL -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SYS_FSL_QSPI_AHB #define CONFIG_SF_DEFAULT_BUS 0 diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 823405fb9e..925a4183fb 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -186,15 +186,11 @@ #ifndef CONFIG_SYS_DCACHE_OFF #endif -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SPI_FLASH_STMICRO #define FSL_QSPI_FLASH_NUM 1 #define FSL_QSPI_FLASH_SIZE SZ_32M #endif diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index c43ea19807..5ed8beb9c2 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -75,7 +75,9 @@ /* Diff from config_distro_defaults.h */ #define CONFIG_SUPPORT_RAW_INITRD +#if !defined(CONFIG_SPL_BUILD) #define CONFIG_ENV_VARS_UBOOT_CONFIG +#endif #define CONFIG_AUTO_COMPLETE /* PXE */ @@ -108,7 +110,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_XHCI_ZYNQMP @@ -136,7 +138,6 @@ # define DFU_ALT_INFO #endif - #define CONFIG_BOARD_LATE_INIT /* Do not preserve environment */ @@ -185,7 +186,6 @@ #endif #ifdef CONFIG_SATA_CEVA -#define CONFIG_AHCI #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT @@ -247,13 +247,24 @@ DFU_ALT_INFO #endif +/* SPL can't handle all huge variables - define just DFU */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT) +#undef CONFIG_EXTRA_ENV_SETTINGS +# define CONFIG_EXTRA_ENV_SETTINGS \ + "dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \ + "atf-uboot.ub ram 0x10000000 0x1000000;" \ + "Image ram 0x80000 0x3f80000;" \ + "system.dtb ram 0x4000000 0x100000\0" \ + "dfu_bufsiz=0x1000\0" +#endif + #define CONFIG_SPL_TEXT_BASE 0xfffc0000 #define CONFIG_SPL_STACK 0xfffffffc -#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_MAX_SIZE 0x40000 /* Just random location in OCM */ -#define CONFIG_SPL_BSS_START_ADDR 0x1000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000000 +#define CONFIG_SPL_BSS_START_ADDR 0x0 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT @@ -265,7 +276,7 @@ #define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 /* ATF is my kernel image */ -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf.ub" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" /* FIT load address for RAM boot */ #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 @@ -279,4 +290,18 @@ # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT) +# undef CONFIG_CMD_BOOTD +# define CONFIG_SPL_ENV_SUPPORT +# define CONFIG_SPL_HASH_SUPPORT +# define CONFIG_ENV_MAX_ENTRIES 10 + +# define CONFIG_SYS_SPL_MALLOC_START 0x20000000 +# define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000000 + +#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE +# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" +#endif +#endif + #endif /* __XILINX_ZYNQMP_H */ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 44434aab7b..8e4b96033b 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -16,7 +16,6 @@ #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) #define CONFIG_ZYNQ_EEPROM -#define CONFIG_AHCI #define CONFIG_SATA_CEVA #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h deleted file mode 100644 index 4866b612d1..0000000000 --- a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Configuration for Xilinx ZynqMP zc1751 XM018 DC4 - * - * (C) Copyright 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H -#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */ diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h new file mode 100644 index 0000000000..25f9cd25f2 --- /dev/null +++ b/include/dt-bindings/clock/boston-clock.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016 Imagination Technologies + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ +#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ + +#define BOSTON_CLK_SYS 0 +#define BOSTON_CLK_CPU 1 + +#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h new file mode 100644 index 0000000000..cf35a577e3 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/mips-gic.h @@ -0,0 +1,9 @@ +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H + +#include <dt-bindings/interrupt-controller/irq.h> + +#define GIC_SHARED 0 +#define GIC_LOCAL 1 + +#endif diff --git a/include/mmc.h b/include/mmc.h index aa6d5d1d4f..e815eb3736 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -11,6 +11,7 @@ #define _MMC_H_ #include <linux/list.h> +#include <linux/sizes.h> #include <linux/compiler.h> #include <part.h> @@ -102,6 +103,7 @@ #define SD_CMD_SWITCH_UHS18V 11 #define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_SD_STATUS 13 #define SD_CMD_ERASE_WR_BLK_START 32 #define SD_CMD_ERASE_WR_BLK_END 33 #define SD_CMD_APP_SEND_OP_COND 41 @@ -392,6 +394,12 @@ struct mmc_config { unsigned char part_type; }; +struct sd_ssr { + unsigned int au; /* In sectors */ + unsigned int erase_timeout; /* In milliseconds */ + unsigned int erase_offset; /* In milliseconds */ +}; + /* * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device * with mmc_get_mmc_dev(). @@ -426,6 +434,7 @@ struct mmc { uint write_bl_len; uint erase_grp_size; /* in 512-byte sectors */ uint hc_wp_grp_size; /* in 512-byte sectors */ + struct sd_ssr ssr; /* SD status register */ u64 capacity; u64 capacity_user; u64 capacity_boot; diff --git a/include/sdhci.h b/include/sdhci.h index 6844c73bdc..144570f2be 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -97,6 +97,7 @@ #define SDHCI_DIV_MASK 0xFF #define SDHCI_DIV_MASK_LEN 8 #define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 @@ -242,6 +243,7 @@ struct sdhci_host { unsigned int quirks; unsigned int host_caps; unsigned int version; + unsigned int clk_mul; /* Clock Multiplier value */ unsigned int clock; struct mmc *mmc; const struct sdhci_ops *ops; diff --git a/include/spi.h b/include/spi.h index ca96fa4b31..4c179838ee 100644 --- a/include/spi.h +++ b/include/spi.h @@ -26,12 +26,9 @@ #define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */ #define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */ #define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */ - -/* SPI mode_rx flags */ -#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */ -#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */ -#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */ -#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */ +#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */ +#define SPI_RX_DUAL BIT(12) /* receive with 2 wires */ +#define SPI_RX_QUAD BIT(13) /* receive with 4 wires */ /* SPI bus connection options - see enum spi_dual_flash */ #define SPI_CONN_DUAL_SHARED (1 << 0) @@ -61,13 +58,11 @@ struct dm_spi_bus { * @cs: Chip select number (0..n-1) * @max_hz: Maximum bus speed that this slave can tolerate * @mode: SPI mode to use for this device (see SPI mode flags) - * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags) */ struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode; - u8 mode_rx; }; #endif /* CONFIG_DM_SPI */ @@ -94,7 +89,6 @@ struct dm_spi_slave_platdata { * bus (bus->seq) so does not need to be stored * @cs: ID of the chip select connected to the slave. * @mode: SPI mode to use for this slave (see SPI mode flags) - * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags) * @wordlen: Size of SPI word in number of bits * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. @@ -112,7 +106,6 @@ struct spi_slave { unsigned int cs; #endif uint mode; - u8 mode_rx; unsigned int wordlen; unsigned int max_write_size; void *memory_map; diff --git a/include/xilinx.h b/include/xilinx.h index aebcb3bfdf..d2a2ea71e1 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -21,6 +21,7 @@ typedef enum { /* typedef xilinx_iface */ master_selectmap, /* master SelectMap (virtex2) */ slave_selectmap, /* slave SelectMap (virtex2) */ devcfg, /* devcfg interface (zynq) */ + csu_dma, /* csu_dma interface (zynqmp) */ max_xilinx_iface_type /* insert all new types before this */ } xilinx_iface; /* end, typedef xilinx_iface */ @@ -31,6 +32,7 @@ typedef enum { /* typedef xilinx_family */ xilinx_virtex2, /* Virtex2 Family */ xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ + xilinx_zynqmp, /* ZynqMP Family */ max_xilinx_type /* insert all new types before this */ } xilinx_family; /* end, typedef xilinx_family */ diff --git a/include/zynqmppl.h b/include/zynqmppl.h new file mode 100644 index 0000000000..542ace9a03 --- /dev/null +++ b/include/zynqmppl.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2015 Xilinx, Inc, + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ZYNQMPPL_H_ +#define _ZYNQMPPL_H_ + +#include <xilinx.h> + +#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 +#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 +#define ZYNQMP_FPGA_OP_INIT (1 << 0) +#define ZYNQMP_FPGA_OP_LOAD (1 << 1) +#define ZYNQMP_FPGA_OP_DONE (1 << 2) + +extern struct xilinx_fpga_op zynqmp_op; + +#define XILINX_ZYNQMP_DESC \ +{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } + +#endif /* _ZYNQMPPL_H_ */ |