diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/falcon.h | 12 | ||||
| -rw-r--r-- | include/configs/rcar-gen4-common.h | 30 | ||||
| -rw-r--r-- | include/configs/spider.h | 14 | ||||
| -rw-r--r-- | include/configs/whitehawk.h | 14 | ||||
| -rw-r--r-- | include/dm/platform_data/serial_sh.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a779f0-cpg-mssr.h | 64 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 | ||||
| -rw-r--r-- | include/dt-bindings/power/r8a779f0-sysc.h | 30 | ||||
| -rw-r--r-- | include/dt-bindings/power/r8a779g0-sysc.h | 46 | ||||
| -rw-r--r-- | include/generic-phy.h | 190 | ||||
| -rw-r--r-- | include/linux/mdio.h | 18 | ||||
| -rw-r--r-- | include/marvell_phy.h | 47 | ||||
| -rw-r--r-- | include/phy.h | 77 | ||||
| -rw-r--r-- | include/phy_interface.h | 66 |
14 files changed, 581 insertions, 118 deletions
diff --git a/include/configs/falcon.h b/include/configs/falcon.h index 446261cedc..0b62ff9fbe 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -9,17 +9,7 @@ #ifndef __FALCON_H #define __FALCON_H -#include "rcar-gen3-common.h" - -/* - * Generic Interrupt Controller Definitions. Undefine v2 locations and define - * v3 locations. - */ -#undef GICD_BASE -#undef GICC_BASE -#undef GICR_BASE -#define GICD_BASE 0xF1000000 -#define GICR_BASE 0xF1060000 +#include "rcar-gen4-common.h" /* Board Clock */ /* XTAL_CLK : 16.66MHz */ diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h new file mode 100644 index 0000000000..c4f506df62 --- /dev/null +++ b/include/configs/rcar-gen4-common.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/rcar-gen4-common.h + * This file is R-Car Gen4 common configuration file. + * + * Copyright (C) 2021 Renesas Electronics Corporation + */ + +#ifndef __RCAR_GEN4_COMMON_H +#define __RCAR_GEN4_COMMON_H + +#include <asm/arch/rmobile.h> + +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 } + +/* Memory */ +#define DRAM_RSV_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) + +/* PHY needs a longer autoneg timeout */ +#define PHY_ANEG_TIMEOUT 20000 + +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +#endif /* __RCAR_GEN4_COMMON_H */ diff --git a/include/configs/spider.h b/include/configs/spider.h new file mode 100644 index 0000000000..e9b7d6bad5 --- /dev/null +++ b/include/configs/spider.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/spider.h + * This file is Spider board configuration. + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#ifndef __SPIDER_H +#define __SPIDER_H + +#include "rcar-gen4-common.h" + +#endif /* __SPIDER_H */ diff --git a/include/configs/whitehawk.h b/include/configs/whitehawk.h new file mode 100644 index 0000000000..4b4cf63596 --- /dev/null +++ b/include/configs/whitehawk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/whitehawk.h + * This file is White Hawk board configuration. + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#ifndef __WHITEHAWK_H +#define __WHITEHAWK_H + +#include "rcar-gen4-common.h" + +#endif /* __WHITEHAWK_H */ diff --git a/include/dm/platform_data/serial_sh.h b/include/dm/platform_data/serial_sh.h index 69cd012fc5..1a20285d92 100644 --- a/include/dm/platform_data/serial_sh.h +++ b/include/dm/platform_data/serial_sh.h @@ -17,6 +17,7 @@ enum sh_serial_type { PORT_SCIF, PORT_SCIFA, PORT_SCIFB, + PORT_HSCIF, }; /* diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h new file mode 100644 index 0000000000..f2ae1c6a82 --- /dev/null +++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779f0 CPG Core Clocks */ + +#define R8A779F0_CLK_ZX 0 +#define R8A779F0_CLK_ZS 1 +#define R8A779F0_CLK_ZT 2 +#define R8A779F0_CLK_ZTR 3 +#define R8A779F0_CLK_S0D2 4 +#define R8A779F0_CLK_S0D3 5 +#define R8A779F0_CLK_S0D4 6 +#define R8A779F0_CLK_S0D2_MM 7 +#define R8A779F0_CLK_S0D3_MM 8 +#define R8A779F0_CLK_S0D4_MM 9 +#define R8A779F0_CLK_S0D2_RT 10 +#define R8A779F0_CLK_S0D3_RT 11 +#define R8A779F0_CLK_S0D4_RT 12 +#define R8A779F0_CLK_S0D6_RT 13 +#define R8A779F0_CLK_S0D3_PER 14 +#define R8A779F0_CLK_S0D6_PER 15 +#define R8A779F0_CLK_S0D12_PER 16 +#define R8A779F0_CLK_S0D24_PER 17 +#define R8A779F0_CLK_S0D2_HSC 18 +#define R8A779F0_CLK_S0D3_HSC 19 +#define R8A779F0_CLK_S0D4_HSC 20 +#define R8A779F0_CLK_S0D6_HSC 21 +#define R8A779F0_CLK_S0D12_HSC 22 +#define R8A779F0_CLK_S0D2_CC 23 +#define R8A779F0_CLK_CL 24 +#define R8A779F0_CLK_CL16M 25 +#define R8A779F0_CLK_CL16M_MM 26 +#define R8A779F0_CLK_CL16M_RT 27 +#define R8A779F0_CLK_CL16M_PER 28 +#define R8A779F0_CLK_CL16M_HSC 29 +#define R8A779F0_CLK_Z0 30 +#define R8A779F0_CLK_Z1 31 +#define R8A779F0_CLK_ZB3 32 +#define R8A779F0_CLK_ZB3D2 33 +#define R8A779F0_CLK_ZB3D4 34 +#define R8A779F0_CLK_SD0H 35 +#define R8A779F0_CLK_SD0 36 +#define R8A779F0_CLK_RPC 37 +#define R8A779F0_CLK_RPCD2 38 +#define R8A779F0_CLK_MSO 39 +#define R8A779F0_CLK_SASYNCRT 40 +#define R8A779F0_CLK_SASYNCPERD1 41 +#define R8A779F0_CLK_SASYNCPERD2 42 +#define R8A779F0_CLK_SASYNCPERD4 43 +#define R8A779F0_CLK_DBGSOC_HSC 44 +#define R8A779F0_CLK_RSW2 45 +#define R8A779F0_CLK_OSC 46 +#define R8A779F0_CLK_ZR 47 +#define R8A779F0_CLK_CPEX 48 +#define R8A779F0_CLK_CBFUSA 49 +#define R8A779F0_CLK_R 50 + +#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h new file mode 100644 index 0000000000..754c54a6eb --- /dev/null +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779g0 CPG Core Clocks */ + +#define R8A779G0_CLK_ZX 0 +#define R8A779G0_CLK_ZS 1 +#define R8A779G0_CLK_ZT 2 +#define R8A779G0_CLK_ZTR 3 +#define R8A779G0_CLK_S0D2 4 +#define R8A779G0_CLK_S0D3 5 +#define R8A779G0_CLK_S0D4 6 +#define R8A779G0_CLK_S0D1_VIO 7 +#define R8A779G0_CLK_S0D2_VIO 8 +#define R8A779G0_CLK_S0D4_VIO 9 +#define R8A779G0_CLK_S0D8_VIO 10 +#define R8A779G0_CLK_S0D1_VC 11 +#define R8A779G0_CLK_S0D2_VC 12 +#define R8A779G0_CLK_S0D4_VC 13 +#define R8A779G0_CLK_S0D2_MM 14 +#define R8A779G0_CLK_S0D4_MM 15 +#define R8A779G0_CLK_S0D2_U3DG 16 +#define R8A779G0_CLK_S0D4_U3DG 17 +#define R8A779G0_CLK_S0D2_RT 18 +#define R8A779G0_CLK_S0D3_RT 19 +#define R8A779G0_CLK_S0D4_RT 20 +#define R8A779G0_CLK_S0D6_RT 21 +#define R8A779G0_CLK_S0D24_RT 22 +#define R8A779G0_CLK_S0D2_PER 23 +#define R8A779G0_CLK_S0D3_PER 24 +#define R8A779G0_CLK_S0D4_PER 25 +#define R8A779G0_CLK_S0D6_PER 26 +#define R8A779G0_CLK_S0D12_PER 27 +#define R8A779G0_CLK_S0D24_PER 28 +#define R8A779G0_CLK_S0D1_HSC 29 +#define R8A779G0_CLK_S0D2_HSC 30 +#define R8A779G0_CLK_S0D4_HSC 31 +#define R8A779G0_CLK_S0D2_CC 32 +#define R8A779G0_CLK_SVD1_IR 33 +#define R8A779G0_CLK_SVD2_IR 34 +#define R8A779G0_CLK_SVD1_VIP 35 +#define R8A779G0_CLK_SVD2_VIP 36 +#define R8A779G0_CLK_CL 37 +#define R8A779G0_CLK_CL16M 38 +#define R8A779G0_CLK_CL16M_MM 39 +#define R8A779G0_CLK_CL16M_RT 40 +#define R8A779G0_CLK_CL16M_PER 41 +#define R8A779G0_CLK_CL16M_HSC 42 +#define R8A779G0_CLK_Z0 43 +#define R8A779G0_CLK_ZB3 44 +#define R8A779G0_CLK_ZB3D2 45 +#define R8A779G0_CLK_ZB3D4 46 +#define R8A779G0_CLK_ZG 47 +#define R8A779G0_CLK_SD0H 48 +#define R8A779G0_CLK_SD0 49 +#define R8A779G0_CLK_RPC 50 +#define R8A779G0_CLK_RPCD2 51 +#define R8A779G0_CLK_MSO 52 +#define R8A779G0_CLK_CANFD 53 +#define R8A779G0_CLK_CSI 54 +#define R8A779G0_CLK_FRAY 55 +#define R8A779G0_CLK_IPC 56 +#define R8A779G0_CLK_SASYNCRT 57 +#define R8A779G0_CLK_SASYNCPERD1 58 +#define R8A779G0_CLK_SASYNCPERD2 59 +#define R8A779G0_CLK_SASYNCPERD4 60 +#define R8A779G0_CLK_VIOBUS 61 +#define R8A779G0_CLK_VIOBUSD2 62 +#define R8A779G0_CLK_VCBUS 63 +#define R8A779G0_CLK_VCBUSD2 64 +#define R8A779G0_CLK_DSIEXT 65 +#define R8A779G0_CLK_DSIREF 66 +#define R8A779G0_CLK_ADGH 67 +#define R8A779G0_CLK_OSC 68 +#define R8A779G0_CLK_ZR0 69 +#define R8A779G0_CLK_ZR1 70 +#define R8A779G0_CLK_ZR2 71 +#define R8A779G0_CLK_IMPA 72 +#define R8A779G0_CLK_IMPAD4 73 +#define R8A779G0_CLK_CPEX 74 +#define R8A779G0_CLK_CBFUSA 75 +#define R8A779G0_CLK_R 76 + +#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h new file mode 100644 index 0000000000..0ec8ad727e --- /dev/null +++ b/include/dt-bindings/power/r8a779f0-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779F0_PD_A1E0D0C0 0 +#define R8A779F0_PD_A1E0D0C1 1 +#define R8A779F0_PD_A1E0D1C0 2 +#define R8A779F0_PD_A1E0D1C1 3 +#define R8A779F0_PD_A1E1D0C0 4 +#define R8A779F0_PD_A1E1D0C1 5 +#define R8A779F0_PD_A1E1D1C0 6 +#define R8A779F0_PD_A1E1D1C1 7 +#define R8A779F0_PD_A2E0D0 16 +#define R8A779F0_PD_A2E0D1 17 +#define R8A779F0_PD_A2E1D0 18 +#define R8A779F0_PD_A2E1D1 19 +#define R8A779F0_PD_A3E0 20 +#define R8A779F0_PD_A3E1 21 + +/* Always-on power area */ +#define R8A779F0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/ diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h new file mode 100644 index 0000000000..c7b139fb07 --- /dev/null +++ b/include/dt-bindings/power/r8a779g0-sysc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779G0_PD_A1E0D0C0 0 +#define R8A779G0_PD_A1E0D0C1 1 +#define R8A779G0_PD_A1E0D1C0 2 +#define R8A779G0_PD_A1E0D1C1 3 +#define R8A779G0_PD_A2E0D0 16 +#define R8A779G0_PD_A2E0D1 17 +#define R8A779G0_PD_A3E0 20 +#define R8A779G0_PD_A33DGA 24 +#define R8A779G0_PD_A23DGB 25 +#define R8A779G0_PD_A1DSP0 33 +#define R8A779G0_PD_A2IMP01 34 +#define R8A779G0_PD_A2PSC 35 +#define R8A779G0_PD_A2CV0 36 +#define R8A779G0_PD_A2CV1 37 +#define R8A779G0_PD_A1CNN0 41 +#define R8A779G0_PD_A2CN0 42 +#define R8A779G0_PD_A3IR 43 +#define R8A779G0_PD_A1DSP1 45 +#define R8A779G0_PD_A2IMP23 46 +#define R8A779G0_PD_A2DMA 47 +#define R8A779G0_PD_A2CV2 48 +#define R8A779G0_PD_A2CV3 49 +#define R8A779G0_PD_A1DSP2 53 +#define R8A779G0_PD_A1DSP3 54 +#define R8A779G0_PD_A3VIP0 56 +#define R8A779G0_PD_A3VIP1 57 +#define R8A779G0_PD_A3VIP2 58 +#define R8A779G0_PD_A3ISP0 60 +#define R8A779G0_PD_A3ISP1 61 +#define R8A779G0_PD_A3DUL 62 + +/* Always-on power area */ +#define R8A779G0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/ diff --git a/include/generic-phy.h b/include/generic-phy.h index f8eddeff67..bee4de8a0b 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -11,6 +11,29 @@ struct ofnode_phandle_args; +enum phy_mode { + PHY_MODE_INVALID, + PHY_MODE_USB_HOST, + PHY_MODE_USB_HOST_LS, + PHY_MODE_USB_HOST_FS, + PHY_MODE_USB_HOST_HS, + PHY_MODE_USB_HOST_SS, + PHY_MODE_USB_DEVICE, + PHY_MODE_USB_DEVICE_LS, + PHY_MODE_USB_DEVICE_FS, + PHY_MODE_USB_DEVICE_HS, + PHY_MODE_USB_DEVICE_SS, + PHY_MODE_USB_OTG, + PHY_MODE_UFS_HS_A, + PHY_MODE_UFS_HS_B, + PHY_MODE_PCIE, + PHY_MODE_ETHERNET, + PHY_MODE_MIPI_DPHY, + PHY_MODE_SATA, + PHY_MODE_LVDS, + PHY_MODE_DP +}; + /** * struct phy - A handle to (allowing control of) a single phy port. * @@ -69,73 +92,99 @@ struct phy_ops { int (*init)(struct phy *phy); /** - * exit - de-initialize the PHY device - * - * Hardware de-intialization should be done here. Every step done in - * init() should be undone here. - * This could be used to suspend the phy to reduce power consumption or - * to put the phy in a known condition before booting the OS (though it - * is NOT called automatically before booting the OS) - * If power_off() is not implemented, it must power down the phy. - * - * @phy: PHY port to be de-initialized - * Return: 0 if OK, or a negative error code - */ + * exit - de-initialize the PHY device + * + * Hardware de-intialization should be done here. Every step done in + * init() should be undone here. + * This could be used to suspend the phy to reduce power consumption or + * to put the phy in a known condition before booting the OS (though it + * is NOT called automatically before booting the OS) + * If power_off() is not implemented, it must power down the phy. + * + * @phy: PHY port to be de-initialized + * Return: 0 if OK, or a negative error code + */ int (*exit)(struct phy *phy); /** - * reset - resets a PHY device without shutting down - * - * @phy: PHY port to be reset - * - * During runtime, the PHY may need to be reset in order to - * re-establish connection etc without being shut down or exit. - * - * Return: 0 if OK, or a negative error code - */ + * reset - resets a PHY device without shutting down + * + * @phy: PHY port to be reset + * + * During runtime, the PHY may need to be reset in order to + * re-establish connection etc without being shut down or exit. + * + * Return: 0 if OK, or a negative error code + */ int (*reset)(struct phy *phy); /** - * power_on - power on a PHY device - * - * @phy: PHY port to be powered on - * - * During runtime, the PHY may need to be powered on or off several - * times. This function is used to power on the PHY. It relies on the - * setup done in init(). If init() is not implemented, it must take care - * of setting up the context (PLLs, ...) - * - * Return: 0 if OK, or a negative error code - */ + * power_on - power on a PHY device + * + * @phy: PHY port to be powered on + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power on the PHY. It relies on the + * setup done in init(). If init() is not implemented, it must take care + * of setting up the context (PLLs, ...) + * + * Return: 0 if OK, or a negative error code + */ int (*power_on)(struct phy *phy); /** - * power_off - power off a PHY device - * - * @phy: PHY port to be powered off - * - * During runtime, the PHY may need to be powered on or off several - * times. This function is used to power off the PHY. Except if - * init()/deinit() are not implemented, it must not de-initialize - * everything. - * - * Return: 0 if OK, or a negative error code - */ + * power_off - power off a PHY device + * + * @phy: PHY port to be powered off + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power off the PHY. Except if + * init()/deinit() are not implemented, it must not de-initialize + * everything. + * + * Return: 0 if OK, or a negative error code + */ int (*power_off)(struct phy *phy); /** - * configure - configure a PHY device - * - * @phy: PHY port to be configured - * @params: PHY Parameters, underlying data is specific to the PHY function - * - * During runtime, the PHY may need to be configured for it's main function. - * This function configures the PHY for it's main function following - * power_on/off() after beeing initialized. - * - * Return: 0 if OK, or a negative error code - */ + * configure - configure a PHY device + * + * @phy: PHY port to be configured + * @params: PHY Parameters, underlying data is specific to the PHY function + * + * During runtime, the PHY may need to be configured for it's main function. + * This function configures the PHY for it's main function following + * power_on/off() after being initialized. + * + * Return: 0 if OK, or a negative error code + */ int (*configure)(struct phy *phy, void *params); + + /** + * set_mode - set PHY device mode + * + * @phy: PHY port to be configured + * @mode: PHY mode + * @submode: PHY submode + * + * Configure PHY mode (e.g. USB, Ethernet, ...) and submode + * (e.g. for Ethernet this can be RGMII). + * + * Return: 0 if OK, or a negative error code + */ + int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode); + + /** + * set_speed - set PHY device speed + * + * @phy: PHY port to be configured + * @speed: PHY speed + * + * Configure PHY speed (e.g. for Ethernet, this could be 10 or 100 ...). + * + * Return: 0 if OK, or a negative error code + */ + int (*set_speed)(struct phy *phy, int speed); }; /** @@ -206,6 +255,24 @@ int generic_phy_power_off(struct phy *phy); */ int generic_phy_configure(struct phy *phy, void *params); +/** + * generic_phy_set_mode() - set PHY device mode + * + * @phy: PHY port to be configured + * @mode: PHY mode + * @submode: PHY submode + * Return: 0 if OK, or a negative error code + */ +int generic_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode); + +/** + * generic_phy_set_speed() - set PHY device speed + * + * @phy: PHY port to be configured + * @speed: PHY speed + * Return: 0 if OK, or a negative error code + */ +int generic_phy_set_speed(struct phy *phy, int speed); /** * generic_phy_get_by_index() - Get a PHY device by integer index. @@ -389,6 +456,21 @@ static inline int generic_phy_power_off(struct phy *phy) return 0; } +static inline int generic_phy_configure(struct phy *phy, void *params) +{ + return 0; +} + +static inline int generic_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + return 0; +} + +static inline int generic_phy_set_speed(struct phy *phy, int speed) +{ + return 0; +} + static inline int generic_phy_get_by_index(struct udevice *user, int index, struct phy *phy) { diff --git a/include/linux/mdio.h b/include/linux/mdio.h index 6e821d906f..b7c845155e 100644 --- a/include/linux/mdio.h +++ b/include/linux/mdio.h @@ -44,6 +44,7 @@ #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ #define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */ +#define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */ #define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */ #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ @@ -91,6 +92,10 @@ #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) /* 10PASS-TS/2BASE-TL */ #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) +/* 2.5 Gb/s */ +#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) +/* 5 Gb/s */ +#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) /* Status register 1. */ #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ @@ -111,6 +116,8 @@ #define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ +#define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */ +#define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */ /* Device present registers. */ #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) @@ -150,6 +157,8 @@ #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ +#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */ +#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */ #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ @@ -203,6 +212,7 @@ #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ +#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */ /* PHY XGXS lane state register. */ #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 @@ -239,9 +249,13 @@ #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 /* AN 10GBASE-T control register. */ +#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */ +#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */ #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ /* AN 10GBASE-T status register. */ +#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */ +#define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */ #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ #define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ @@ -270,6 +284,10 @@ #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ +/* 2.5G/5G Extended abilities register. */ +#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */ +#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */ + /* LASI RX_ALARM control/status registers. */ #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ diff --git a/include/marvell_phy.h b/include/marvell_phy.h new file mode 100644 index 0000000000..0f06c2287b --- /dev/null +++ b/include/marvell_phy.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _MARVELL_PHY_H +#define _MARVELL_PHY_H + +/* Mask used for ID comparisons */ +#define MARVELL_PHY_ID_MASK 0xfffffff0 + +/* Known PHY IDs */ +#define MARVELL_PHY_ID_88E1101 0x01410c60 +#define MARVELL_PHY_ID_88E1112 0x01410c90 +#define MARVELL_PHY_ID_88E1111 0x01410cc0 +#define MARVELL_PHY_ID_88E1118 0x01410e10 +#define MARVELL_PHY_ID_88E1121R 0x01410cb0 +#define MARVELL_PHY_ID_88E1145 0x01410cd0 +#define MARVELL_PHY_ID_88E1149R 0x01410e50 +#define MARVELL_PHY_ID_88E1240 0x01410e30 +#define MARVELL_PHY_ID_88E1318S 0x01410e90 +#define MARVELL_PHY_ID_88E1340S 0x01410dc0 +#define MARVELL_PHY_ID_88E1116R 0x01410e40 +#define MARVELL_PHY_ID_88E1510 0x01410dd0 +#define MARVELL_PHY_ID_88E1540 0x01410eb0 +#define MARVELL_PHY_ID_88E1545 0x01410ea0 +#define MARVELL_PHY_ID_88E1548P 0x01410ec0 +#define MARVELL_PHY_ID_88E3016 0x01410e60 +#define MARVELL_PHY_ID_88X3310 0x002b09a0 +#define MARVELL_PHY_ID_88E2110 0x002b09b0 +#define MARVELL_PHY_ID_88X2222 0x01410f10 + +/* Marvel 88E1111 in Finisar SFP module with modified PHY ID */ +#define MARVELL_PHY_ID_88E1111_FINISAR 0x01ff0cc0 + +/* These Ethernet switch families contain embedded PHYs, but they do + * not have a model ID. So the switch driver traps reads to the ID2 + * register and returns the switch family ID + */ +#define MARVELL_PHY_ID_88E6341_FAMILY 0x01410f41 +#define MARVELL_PHY_ID_88E6390_FAMILY 0x01410f90 +#define MARVELL_PHY_ID_88E6393_FAMILY 0x002b0b9b + +#define MARVELL_PHY_FAMILY_ID(id) ((id) >> 4) + +/* struct phy_device dev_flags definitions */ +#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x00000001 +#define MARVELL_PHY_M1118_DNS323_LEDS 0x00000002 +#define MARVELL_PHY_LED0_LINK_LED1_ACTIVE 0x00000004 + +#endif /* _MARVELL_PHY_H */ diff --git a/include/phy.h b/include/phy.h index 87aa86c2e7..a837fed723 100644 --- a/include/phy.h +++ b/include/phy.h @@ -125,8 +125,6 @@ struct phy_driver { int (*write_mmd)(struct phy_device *phydev, int devad, int reg, u16 val); - struct list_head list; - /* driver private data */ ulong data; }; @@ -173,10 +171,6 @@ struct fixed_link { int asym_pause; }; -#ifdef CONFIG_PHYLIB_10G -extern struct phy_driver gen10g_driver; -#endif - /** * phy_init() - Initializes the PHY drivers * This function registers all available PHY drivers @@ -288,6 +282,37 @@ static inline ofnode phy_get_ofnode(struct phy_device *phydev) return dev_ofnode(phydev->dev); } +/** + * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a + * condition is met or a timeout occurs + * + * @phydev: The phy_device struct + * @devaddr: The MMD to read from + * @regnum: The register on the MMD to read + * @val: Variable to read the register into + * @cond: Break condition (usually involving @val) + * @sleep_us: Maximum time to sleep between reads in us (0 + * tight-loops). Should be less than ~20ms since usleep_range + * is used (see Documentation/timers/timers-howto.rst). + * @timeout_us: Timeout in us, 0 means never timeout + * @sleep_before_read: if it is true, sleep @sleep_us before read. + * Returns 0 on success and -ETIMEDOUT upon a timeout. In either + * case, the last read value at @args is stored in @val. Must not + * be called from atomic context if sleep_us or timeout_us are used. + */ +#define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \ + sleep_us, timeout_us, sleep_before_read) \ +({ \ + int __ret = read_poll_timeout(phy_read_mmd, val, (cond) || val < 0, \ + sleep_us, timeout_us, \ + phydev, devaddr, regnum); \ + if (val < 0) \ + __ret = val; \ + if (__ret) \ + dev_err(phydev->dev, "%s failed: %d\n", __func__, __ret); \ + __ret; \ +}) + int phy_read(struct phy_device *phydev, int devad, int regnum); int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val); void phy_mmd_start_indirect(struct phy_device *phydev, int devad, int regnum); @@ -295,11 +320,14 @@ int phy_read_mmd(struct phy_device *phydev, int devad, int regnum); int phy_write_mmd(struct phy_device *phydev, int devad, int regnum, u16 val); int phy_set_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); +int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, + u16 mask, u16 set); +int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, + u16 mask, u16 set); int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); -int phy_register(struct phy_driver *drv); int phy_set_supported(struct phy_device *phydev, u32 max_speed); int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask, u16 set); @@ -315,35 +343,12 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev); -int phy_b53_init(void); -int phy_mv88e61xx_init(void); -int phy_adin_init(void); -int phy_aquantia_init(void); -int phy_atheros_init(void); -int phy_broadcom_init(void); -int phy_cortina_init(void); -int phy_cortina_access_init(void); -int phy_davicom_init(void); -int phy_et1011c_init(void); -int phy_lxt_init(void); -int phy_marvell_init(void); -int phy_micrel_ksz8xxx_init(void); -int phy_micrel_ksz90x1_init(void); -int phy_meson_gxl_init(void); -int phy_natsemi_init(void); -int phy_nxp_c45_tja11xx_init(void); -int phy_nxp_tja11xx_init(void); -int phy_realtek_init(void); -int phy_smsc_init(void); -int phy_teranetics_init(void); -int phy_ti_init(void); -int phy_vitesse_init(void); -int phy_xilinx_init(void); -int phy_xway_init(void); -int phy_mscc_init(void); -int phy_fixed_init(void); -int phy_ncsi_init(void); -int phy_xilinx_gmii2rgmii_init(void); +/** + * U_BOOT_PHY_DRIVER() - Declare a new U-Boot driver + * @__name: name of the driver + */ +#define U_BOOT_PHY_DRIVER(__name) \ + ll_entry_declare(struct phy_driver, __name, phy_driver) int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); diff --git a/include/phy_interface.h b/include/phy_interface.h index fed3357b9a..31be3228c7 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -14,63 +14,95 @@ typedef enum { PHY_INTERFACE_MODE_NA, /* don't touch */ + PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_SGMII, - PHY_INTERFACE_MODE_SGMII_2500, - PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_REVMII, PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_REVRMII, PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_RGMII_ID, PHY_INTERFACE_MODE_RGMII_RXID, PHY_INTERFACE_MODE_RGMII_TXID, PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_SMII, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_XLGMII, + PHY_INTERFACE_MODE_MOCA, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TRGMII, + PHY_INTERFACE_MODE_100BASEX, PHY_INTERFACE_MODE_1000BASEX, PHY_INTERFACE_MODE_2500BASEX, - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_XAUI, + PHY_INTERFACE_MODE_5GBASER, PHY_INTERFACE_MODE_RXAUI, - PHY_INTERFACE_MODE_SFI, - PHY_INTERFACE_MODE_INTERNAL, + PHY_INTERFACE_MODE_XAUI, + /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ + PHY_INTERFACE_MODE_10GBASER, + PHY_INTERFACE_MODE_25GBASER, + PHY_INTERFACE_MODE_USXGMII, + /* 10GBASE-KR - with Clause 73 AN */ + PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_QUSGMII, + PHY_INTERFACE_MODE_1000BASEKX, +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) + /* LX2160A SERDES modes */ PHY_INTERFACE_MODE_25G_AUI, PHY_INTERFACE_MODE_XLAUI, PHY_INTERFACE_MODE_CAUI2, PHY_INTERFACE_MODE_CAUI4, +#endif +#if defined(CONFIG_PHY_NCSI) PHY_INTERFACE_MODE_NCSI, - PHY_INTERFACE_MODE_10GBASER, - PHY_INTERFACE_MODE_USXGMII, +#endif PHY_INTERFACE_MODE_MAX, } phy_interface_t; static const char * const phy_interface_strings[] = { - [PHY_INTERFACE_MODE_NA] = "", + [PHY_INTERFACE_MODE_NA] = "", + [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_MII] = "mii", [PHY_INTERFACE_MODE_GMII] = "gmii", [PHY_INTERFACE_MODE_SGMII] = "sgmii", - [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", - [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", [PHY_INTERFACE_MODE_TBI] = "tbi", + [PHY_INTERFACE_MODE_REVMII] = "rev-mii", [PHY_INTERFACE_MODE_RMII] = "rmii", + [PHY_INTERFACE_MODE_REVRMII] = "rev-rmii", [PHY_INTERFACE_MODE_RGMII] = "rgmii", [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", [PHY_INTERFACE_MODE_RTBI] = "rtbi", + [PHY_INTERFACE_MODE_SMII] = "smii", + [PHY_INTERFACE_MODE_XGMII] = "xgmii", + [PHY_INTERFACE_MODE_XLGMII] = "xlgmii", + [PHY_INTERFACE_MODE_MOCA] = "moca", + [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", + [PHY_INTERFACE_MODE_TRGMII] = "trgmii", [PHY_INTERFACE_MODE_1000BASEX] = "1000base-x", + [PHY_INTERFACE_MODE_1000BASEKX] = "1000base-kx", [PHY_INTERFACE_MODE_2500BASEX] = "2500base-x", - [PHY_INTERFACE_MODE_XGMII] = "xgmii", - [PHY_INTERFACE_MODE_XAUI] = "xaui", + [PHY_INTERFACE_MODE_5GBASER] = "5gbase-r", [PHY_INTERFACE_MODE_RXAUI] = "rxaui", - [PHY_INTERFACE_MODE_SFI] = "sfi", - [PHY_INTERFACE_MODE_INTERNAL] = "internal", + [PHY_INTERFACE_MODE_XAUI] = "xaui", + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", + [PHY_INTERFACE_MODE_25GBASER] = "25gbase-r", + [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", + [PHY_INTERFACE_MODE_10GKR] = "10gbase-kr", + [PHY_INTERFACE_MODE_100BASEX] = "100base-x", + [PHY_INTERFACE_MODE_QUSGMII] = "qusgmii", +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) + /* LX2160A SERDES modes */ [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui", [PHY_INTERFACE_MODE_XLAUI] = "xlaui4", [PHY_INTERFACE_MODE_CAUI2] = "caui2", [PHY_INTERFACE_MODE_CAUI4] = "caui4", +#endif +#if defined(CONFIG_PHY_NCSI) [PHY_INTERFACE_MODE_NCSI] = "NC-SI", - [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", - [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", +#endif }; /* Backplane modes: |