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-rw-r--r--drivers/clk/clk_zynqmp.c1
-rw-r--r--drivers/firmware/firmware-zynqmp.c22
-rw-r--r--drivers/mailbox/zynqmp-ipi.c159
-rw-r--r--drivers/net/xilinx_axi_emac.c9
-rw-r--r--drivers/pci/pcie_xilinx.c37
-rw-r--r--drivers/spi/xilinx_spi.c68
6 files changed, 245 insertions, 51 deletions
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 1cfe0e25b1..c059b9e8e6 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -844,6 +844,7 @@ static int zynqmp_clk_enable(struct clk *clk)
break;
case qspi_ref ... can1_ref:
case lpd_lsbus:
+ case topsw_lsbus:
clkact_shift = 24;
mask = 0x1;
break;
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 8ea15c7ed3..dfad798a2e 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <dm/lists.h>
#include <log.h>
#include <zynqmp_firmware.h>
@@ -290,10 +291,31 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
static int zynqmp_power_probe(struct udevice *dev)
{
+ struct udevice *ipi_dev;
+ ofnode ipi_node;
int ret;
debug("%s, (dev=%p)\n", __func__, dev);
+ /*
+ * Probe all IPI parent node driver. It is important to have IPI
+ * devices available when requested by mbox_get_by* API.
+ * If IPI device isn't available, then mailbox request fails and
+ * that causes system boot failure.
+ * To avoid this make sure all IPI parent drivers are probed here,
+ * and IPI parent driver binds each child node to mailbox driver.
+ * This way mbox_get_by_* API will have correct mailbox device
+ * driver probed.
+ */
+ ofnode_for_each_compatible_node(ipi_node, "xlnx,zynqmp-ipi-mailbox") {
+ ret = uclass_get_device_by_ofnode(UCLASS_NOP, ipi_node, &ipi_dev);
+ if (ret) {
+ dev_err(dev, "failed to get IPI device from node %s\n",
+ ofnode_get_name(ipi_node));
+ return ret;
+ }
+ }
+
ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan);
if (ret) {
debug("%s: Cannot find tx mailbox\n", __func__);
diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 3e4ec47389..eb86847bbe 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -8,9 +8,13 @@
#include <common.h>
#include <log.h>
#include <asm/io.h>
+#include <asm/system.h>
#include <dm.h>
#include <mailbox-uclass.h>
#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <dm/of_access.h>
+#include <linux/arm-smccc.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <wait_bit.h>
@@ -21,6 +25,43 @@
#define IPI_BIT_MASK_PMU0 0x10000
#define IPI_INT_REG_BASE_APU 0xFF300000
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN 0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+
+/*
+ * Flag to indicate if notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK BIT(0)
+
+/*
+ * Flag to indicate if notification interrupt
+ * to be enabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK BIT(0)
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
struct ipi_int_regs {
u32 trig; /* 0x0 */
u32 obs; /* 0x4 */
@@ -39,8 +80,24 @@ struct zynqmp_ipi {
void __iomem *local_res_regs;
void __iomem *remote_req_regs;
void __iomem *remote_res_regs;
+ u32 remote_id;
+ u32 local_id;
+ bool el3_supported;
};
+static int zynqmp_ipi_fw_call(struct zynqmp_ipi *ipi_mbox,
+ unsigned long a0, unsigned long a3)
+{
+ struct arm_smccc_res res = {0};
+ unsigned long a1, a2;
+
+ a1 = ipi_mbox->local_id;
+ a2 = ipi_mbox->remote_id;
+ arm_smccc_smc(a0, a1, a2, a3, 0, 0, 0, 0, &res);
+
+ return (int)res.a0;
+}
+
static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
{
const struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
@@ -51,6 +108,21 @@ static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
for (size_t i = 0; i < msg->len; i++)
writel(msg->buf[i], &mbx[i]);
+ /* Use SMC calls for Exception Level less than 3 where TF-A is available */
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
+ ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_NOTIFY, 0);
+
+ debug("%s, send %ld bytes\n", __func__, msg->len);
+
+ return ret;
+ }
+
+ /* Return if EL3 is not supported */
+ if (!zynqmp->el3_supported) {
+ dev_err(chan->dev, "mailbox in EL3 only supported for zynqmp");
+ return -EOPNOTSUPP;
+ }
+
/* Write trigger interrupt */
writel(IPI_BIT_MASK_PMU0, &ipi_int_apu->trig);
@@ -67,29 +139,50 @@ static int zynqmp_ipi_recv(struct mbox_chan *chan, void *data)
struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev);
u32 *mbx = (u32 *)zynqmp->local_res_regs;
+ int ret = 0;
/*
* PMU Firmware does not trigger IPI interrupt for API call responses so
- * there is no need to check ISR flags
+ * there is no need to check ISR flags for EL3.
*/
for (size_t i = 0; i < msg->len; i++)
msg->buf[i] = readl(&mbx[i]);
+ /* Ack to remote if EL is not 3 */
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
+ ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_ACK,
+ IPI_SMC_ACK_EIRQ_MASK);
+ }
+
debug("%s, recv %ld bytes\n", __func__, msg->len);
- return 0;
+ return ret;
};
-static int zynqmp_ipi_probe(struct udevice *dev)
+static int zynqmp_ipi_dest_probe(struct udevice *dev)
{
struct zynqmp_ipi *zynqmp = dev_get_priv(dev);
struct resource res;
ofnode node;
+ int ret;
debug("%s(dev=%p)\n", __func__, dev);
- /* Get subnode where the regs are defined */
- /* Note IPI mailbox node needs to be the first one in DT */
- node = ofnode_first_subnode(dev_ofnode(dev));
+ node = dev_ofnode(dev);
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
+ zynqmp->el3_supported = true;
+
+ ret = dev_read_u32(dev->parent, "xlnx,ipi-id", &zynqmp->local_id);
+ if (ret) {
+ dev_err(dev, "can't get local ipi id\n");
+ return ret;
+ }
+
+ ret = ofnode_read_u32(node, "xlnx,ipi-id", &zynqmp->remote_id);
+ if (ret) {
+ dev_err(dev, "can't get remote ipi id\n");
+ return ret;
+ }
if (ofnode_read_resource_byname(node, "local_request_region", &res)) {
dev_err(dev, "No reg property for local_request_region\n");
@@ -97,6 +190,8 @@ static int zynqmp_ipi_probe(struct udevice *dev)
};
zynqmp->local_req_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->local_req_regs)
+ return -EINVAL;
if (ofnode_read_resource_byname(node, "local_response_region", &res)) {
dev_err(dev, "No reg property for local_response_region\n");
@@ -104,6 +199,8 @@ static int zynqmp_ipi_probe(struct udevice *dev)
};
zynqmp->local_res_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->local_res_regs)
+ return -EINVAL;
if (ofnode_read_resource_byname(node, "remote_request_region", &res)) {
dev_err(dev, "No reg property for remote_request_region\n");
@@ -111,6 +208,8 @@ static int zynqmp_ipi_probe(struct udevice *dev)
};
zynqmp->remote_req_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->remote_req_regs)
+ return -EINVAL;
if (ofnode_read_resource_byname(node, "remote_response_region", &res)) {
dev_err(dev, "No reg property for remote_response_region\n");
@@ -118,25 +217,59 @@ static int zynqmp_ipi_probe(struct udevice *dev)
};
zynqmp->remote_res_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->remote_res_regs)
+ return -EINVAL;
return 0;
};
-static const struct udevice_id zynqmp_ipi_ids[] = {
- { .compatible = "xlnx,zynqmp-ipi-mailbox" },
- { }
+static int zynqmp_ipi_probe(struct udevice *dev)
+{
+ struct udevice *cdev;
+ ofnode cnode;
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ dev_for_each_subnode(cnode, dev) {
+ ret = device_bind_driver_to_node(dev, "zynqmp_ipi_dest",
+ ofnode_get_name(cnode),
+ cnode, &cdev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
};
-struct mbox_ops zynqmp_ipi_mbox_ops = {
+struct mbox_ops zynqmp_ipi_dest_mbox_ops = {
.send = zynqmp_ipi_send,
.recv = zynqmp_ipi_recv,
};
+static const struct udevice_id zynqmp_ipi_dest_ids[] = {
+ { .compatible = "xlnx,zynqmp-ipi-dest-mailbox" },
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_ipi_dest) = {
+ .name = "zynqmp_ipi_dest",
+ .id = UCLASS_MAILBOX,
+ .of_match = zynqmp_ipi_dest_ids,
+ .probe = zynqmp_ipi_dest_probe,
+ .priv_auto = sizeof(struct zynqmp_ipi),
+ .ops = &zynqmp_ipi_dest_mbox_ops,
+};
+
+static const struct udevice_id zynqmp_ipi_ids[] = {
+ { .compatible = "xlnx,zynqmp-ipi-mailbox" },
+ { }
+};
+
U_BOOT_DRIVER(zynqmp_ipi) = {
.name = "zynqmp_ipi",
- .id = UCLASS_MAILBOX,
+ .id = UCLASS_NOP,
.of_match = zynqmp_ipi_ids,
.probe = zynqmp_ipi_probe,
- .priv_auto = sizeof(struct zynqmp_ipi),
- .ops = &zynqmp_ipi_mbox_ops,
+ .flags = DM_FLAG_PROBE_AFTER_BIND,
};
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 54f2232768..ef151ee51b 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -903,12 +903,11 @@ static int axi_emac_of_to_plat(struct udevice *dev)
ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0,
&axistream_node);
- if (ret) {
- printf("%s: axistream is not found\n", __func__);
- return -EINVAL;
- }
+ if (!ret)
+ plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node);
+ else
+ plat->dmatx = (struct axidma_reg *)dev_read_addr_index(dev, 1);
- plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node);
if (!plat->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index 53fd121e90..3db460b5f9 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -8,11 +8,10 @@
#include <common.h>
#include <dm.h>
#include <pci.h>
-#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/printk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/err.h>
/**
* struct xilinx_pcie - Xilinx PCIe controller state
@@ -25,6 +24,8 @@ struct xilinx_pcie {
/* Register definitions */
#define XILINX_PCIE_REG_PSCR 0x144
#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
+#define XILINX_PCIE_REG_RPSC 0x148
+#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
/**
* pcie_xilinx_link_up() - Check whether the PCIe link is up
@@ -140,20 +141,22 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
static int pcie_xilinx_of_to_plat(struct udevice *dev)
{
struct xilinx_pcie *pcie = dev_get_priv(dev);
- struct fdt_resource reg_res;
- DECLARE_GLOBAL_DATA_PTR;
- int err;
-
- err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
- 0, &reg_res);
- if (err < 0) {
- pr_err("\"reg\" resource not found\n");
- return err;
- }
-
- pcie->cfg_base = map_physmem(reg_res.start,
- fdt_resource_size(&reg_res),
- MAP_NOCACHE);
+ fdt_addr_t addr;
+ fdt_size_t size;
+ u32 rpsc;
+
+ addr = dev_read_addr_size(dev, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ pcie->cfg_base = devm_ioremap(dev, addr, size);
+ if (IS_ERR(pcie->cfg_base))
+ return PTR_ERR(pcie->cfg_base);
+
+ /* Enable the Bridge enable bit */
+ rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+ rpsc |= XILINX_PCIE_REG_RPSC_BEN;
+ __raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
return 0;
}
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index b58a3f632a..94ddf4967e 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -67,7 +67,7 @@
/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
#define SPISSR_MASK(cs) (1 << (cs))
#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
-#define SPISSR_OFF ~0UL
+#define SPISSR_OFF (~0U)
/* SPI Software Reset Register (ssr) */
#define SPISSR_RESET_VALUE 0x0a
@@ -109,6 +109,27 @@ struct xilinx_spi_priv {
u8 startup;
};
+static int xilinx_spi_find_buffer_size(struct xilinx_spi_regs *regs)
+{
+ u8 sr;
+ int n_words = 0;
+
+ /*
+ * Before the buffer_size detection reset the core
+ * to make sure to start with a clean state.
+ */
+ writel(SPISSR_RESET_VALUE, &regs->srr);
+
+ /* Fill the Tx FIFO with as many words as possible */
+ do {
+ writel(0, &regs->spidtr);
+ sr = readl(&regs->spisr);
+ n_words++;
+ } while (!(sr & SPISR_TX_FULL));
+
+ return n_words;
+}
+
static int xilinx_spi_probe(struct udevice *bus)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
@@ -116,6 +137,8 @@ static int xilinx_spi_probe(struct udevice *bus)
regs = priv->regs = dev_read_addr_ptr(bus);
priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
+ if (!priv->fifo_depth)
+ priv->fifo_depth = xilinx_spi_find_buffer_size(regs);
writel(SPISSR_RESET_VALUE, &regs->srr);
@@ -217,9 +240,9 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
return i;
}
-static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len)
+static int start_transfer(struct udevice *dev, const void *dout, void *din, u32 len)
{
- struct udevice *bus = spi->dev->parent;
+ struct udevice *bus = dev->parent;
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
u32 count, txbytes, rxbytes;
@@ -259,10 +282,9 @@ static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u3
return 0;
}
-static void xilinx_spi_startup_block(struct spi_slave *spi)
+static void xilinx_spi_startup_block(struct udevice *dev)
{
- struct dm_spi_slave_plat *slave_plat =
- dev_get_parent_plat(spi->dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
unsigned char txp;
unsigned char rxp[8];
@@ -270,13 +292,25 @@ static void xilinx_spi_startup_block(struct spi_slave *spi)
* Perform a dummy read as a work around for
* the startup block issue.
*/
- spi_cs_activate(spi->dev, slave_plat->cs);
+ spi_cs_activate(dev, slave_plat->cs);
txp = 0x9f;
- start_transfer(spi, (void *)&txp, NULL, 1);
+ start_transfer(dev, (void *)&txp, NULL, 1);
- start_transfer(spi, NULL, (void *)rxp, 6);
+ start_transfer(dev, NULL, (void *)rxp, 6);
- spi_cs_deactivate(spi->dev);
+ spi_cs_deactivate(dev);
+}
+
+static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ int ret;
+
+ spi_cs_activate(dev, slave_plat->cs);
+ ret = start_transfer(dev, dout, din, bitlen / 8);
+ spi_cs_deactivate(dev);
+ return ret;
}
static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
@@ -294,14 +328,15 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
* as QSPI provides command. So first command fails.
*/
if (!startup) {
- xilinx_spi_startup_block(spi);
+ xilinx_spi_startup_block(spi->dev);
startup++;
}
spi_cs_activate(spi->dev, slave_plat->cs);
if (op->cmd.opcode) {
- ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
+ ret = start_transfer(spi->dev, (void *)&op->cmd.opcode,
+ NULL, 1);
if (ret)
goto done;
}
@@ -313,7 +348,7 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
addr_buf[i] = op->addr.val >>
(8 * (op->addr.nbytes - i - 1));
- ret = start_transfer(spi, (void *)addr_buf, NULL,
+ ret = start_transfer(spi->dev, (void *)addr_buf, NULL,
op->addr.nbytes);
if (ret)
goto done;
@@ -322,16 +357,16 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
dummy_len = (op->dummy.nbytes * op->data.buswidth) /
op->dummy.buswidth;
- ret = start_transfer(spi, NULL, NULL, dummy_len);
+ ret = start_transfer(spi->dev, NULL, NULL, dummy_len);
if (ret)
goto done;
}
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN) {
- ret = start_transfer(spi, NULL,
+ ret = start_transfer(spi->dev, NULL,
op->data.buf.in, op->data.nbytes);
} else {
- ret = start_transfer(spi, op->data.buf.out,
+ ret = start_transfer(spi->dev, op->data.buf.out,
NULL, op->data.nbytes);
}
if (ret)
@@ -427,6 +462,7 @@ static const struct spi_controller_mem_ops xilinx_spi_mem_ops = {
static const struct dm_spi_ops xilinx_spi_ops = {
.claim_bus = xilinx_spi_claim_bus,
.release_bus = xilinx_spi_release_bus,
+ .xfer = xilinx_spi_xfer,
.set_speed = xilinx_spi_set_speed,
.set_mode = xilinx_spi_set_mode,
.mem_ops = &xilinx_spi_mem_ops,
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-02 19:29:06 +0000