diff options
Diffstat (limited to 'drivers')
48 files changed, 1495 insertions, 1558 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 9ff4b8736c..b5a279862a 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -116,7 +116,7 @@ config SUNXI_AHCI config AHCI_MVEBU bool "Marvell EBU AHCI SATA support" - depends on ARCH_MVEBU + depends on ARCH_MVEBU || ARCH_OCTEON depends on AHCI select SCSI_AHCI select DM_SCSI diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 98b288254b..57c4e153ba 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -500,6 +500,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, { struct ahci_ioports *pp = &(uc_priv->port[port]); struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + phys_addr_t pa = virt_to_phys(buf); u32 sg_count; int i; @@ -510,9 +511,6 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, } for (i = 0; i < sg_count; i++) { - /* We assume virt=phys */ - phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT; - ahci_sg->addr = cpu_to_le32(lower_32_bits(pa)); ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa)); if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) { @@ -520,25 +518,26 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, return -1; } ahci_sg->flags_size = cpu_to_le32(0x3fffff & - (buf_len < MAX_DATA_BYTE_COUNT - ? (buf_len - 1) - : (MAX_DATA_BYTE_COUNT - 1))); + (buf_len < MAX_DATA_BYTE_COUNT ? + (buf_len - 1) : + (MAX_DATA_BYTE_COUNT - 1))); ahci_sg++; buf_len -= MAX_DATA_BYTE_COUNT; + pa += MAX_DATA_BYTE_COUNT; } return sg_count; } - static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) { + phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl); + pp->cmd_slot->opts = cpu_to_le32(opts); pp->cmd_slot->status = 0; - pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa)); #ifdef CONFIG_PHYS_64BIT - pp->cmd_slot->tbl_addr_hi = - cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); + pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa)); #endif } @@ -674,12 +673,12 @@ static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis, ahci_dcache_invalidate_range((unsigned long)buf, (unsigned long)buf_len); - debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); + debug("%s: %d byte transferred.\n", __func__, + le32_to_cpu(pp->cmd_slot->status)); return 0; } - static char *ata_id_strcpy(u16 *target, u16 *src, int len) { int i; diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c index 7d82d2ea3f..f05150d61d 100644 --- a/drivers/ata/ahci_mvebu.c +++ b/drivers/ata/ahci_mvebu.c @@ -39,7 +39,7 @@ static int mvebu_ahci_probe(struct udevice *dev) */ board_ahci_enable(); - ahci_probe_scsi(dev, dev_read_addr(dev)); + ahci_probe_scsi(dev, (ulong)dev_remap_addr(dev)); return 0; } @@ -48,6 +48,7 @@ static const struct udevice_id mvebu_ahci_ids[] = { { .compatible = "marvell,armada-380-ahci" }, { .compatible = "marvell,armada-3700-ahci" }, { .compatible = "marvell,armada-8k-ahci" }, + { .compatible = "cavium,octeon-7130-ahci" }, { } }; diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c index 09e7dbd3a3..d5079da3ff 100644 --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c @@ -239,11 +239,11 @@ static const struct mstp_stop_table r8a7790_mstp_table[] = { { 0x00640801, 0x400000, 0x00640801, 0x0 }, { 0xDB6E9BDF, 0x0, 0xDB6E9BDF, 0x0 }, { 0x300DA1FC, 0x2010, 0x300DA1FC, 0x0 }, - { 0xF08CF831, 0x0, 0xF08CF831, 0x0 }, + { 0xF08CFC31, 0x0, 0xF08CFC31, 0x0 }, { 0x80000184, 0x180, 0x80000184, 0x0 }, { 0x44C00046, 0x0, 0x44C00046, 0x0 }, { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ - { 0x07F30718, 0x200000, 0x07F30718, 0x0 }, + { 0x27F30718, 0x200000, 0x27F30718, 0x0 }, { 0x01F0FF84, 0x0, 0x01F0FF84, 0x0 }, { 0xF5979FCF, 0x0, 0xF5979FCF, 0x0 }, { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c index 675ac83a61..fa0e275afd 100644 --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c @@ -245,7 +245,7 @@ static const struct mstp_stop_table r8a7791_mstp_table[] = { { 0x800001C4, 0x180, 0x800001C4, 0x0 }, { 0x44C00046, 0x0, 0x44C00046, 0x0 }, { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ - { 0x05BFE618, 0x200000, 0x05BFE618, 0x0 }, + { 0x25BFE618, 0x200000, 0x25BFE618, 0x0 }, { 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 }, { 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 }, { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c index 1fcac9b59d..d05f89deb1 100644 --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c @@ -218,12 +218,12 @@ static const struct mstp_stop_table r8a7794_mstp_table[] = { { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 }, { 0xE084D810, 0x0, 0xE084D810, 0x0 }, { 0x800001C4, 0x180, 0x800001C4, 0x0 }, - { 0x40C00044, 0x0, 0x40C00044, 0x0 }, + { 0x40800044, 0x0, 0x40800044, 0x0 }, { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ - { 0x013FE618, 0x80000, 0x013FE618, 0x0 }, + { 0x21BFE618, 0x80000, 0x21BFE618, 0x0 }, { 0x40803C05, 0x0, 0x40803C05, 0x0 }, { 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, + { 0x7E3EFFE0, 0x0, 0x7E3EFFE0, 0x0 }, { 0x000001C0, 0x0, 0x000001C0, 0x0 }, }; diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 101f6583fa..b137564962 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -327,17 +327,17 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { }; static const struct mstp_stop_table r8a7795_mstp_table[] = { - { 0x00640800, 0x0, 0x00640800, 0 }, - { 0xF3EE9390, 0x0, 0xF3EE9390, 0 }, - { 0x340FAFDC, 0x2040, 0x340FAFDC, 0 }, - { 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 }, - { 0x80000184, 0x180, 0x80000184, 0 }, - { 0x40BFFF46, 0x0, 0x40BFFF46, 0 }, - { 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 }, - { 0x39FFFF0E, 0x0, 0x39FFFF0E, 0 }, - { 0x01F19FF4, 0x0, 0x01F19FF4, 0 }, - { 0xFFDFFFFF, 0x0, 0xFFDFFFFF, 0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, + { 0x00210000, 0x0, 0x00210000, 0 }, + { 0xc3ec13a0, 0x0, 0xc3ec13a0, 0 }, + { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 }, + { 0xf4cc7cdf, 0x400, 0xf4cc7cdf, 0 }, + { 0x80000004, 0x180, 0x80000004, 0 }, + { 0x40dfff46, 0x0, 0x40dfff46, 0 }, + { 0xc5e8ccce, 0x0, 0xc5e8ccce, 0 }, + { 0x39ffdf3f, 0x0, 0x39ffdf3f, 0 }, + { 0x01f09ff6, 0x0, 0x01f09ff6, 0 }, + { 0xfddfdffe, 0x0, 0xfddfdffe, 0 }, + { 0xfffeffe0, 0x0, 0xfffeffe0, 0 }, { 0x00000000, 0x0, 0x00000000, 0 }, }; diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 3c17bcbb18..6745305a59 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -306,17 +306,17 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { static const struct mstp_stop_table r8a7796_mstp_table[] = { { 0x00200000, 0x0, 0x00200000, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, - { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, - { 0x80000184, 0x180, 0x80000184, 0 }, - { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, - { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, - { 0x000000B7, 0x0, 0x000000B7, 0 }, + { 0xd3e813a0, 0x0, 0xd3e813a0, 0 }, + { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 }, + { 0xd00c7cdf, 0x400, 0xd00c7cdf, 0 }, + { 0x80000004, 0x180, 0x80000004, 0 }, + { 0x40dfff46, 0x0, 0x40dfff46, 0 }, + { 0x84ea888e, 0x0, 0x84ea888e, 0 }, + { 0x29df5e1c, 0x0, 0x29df5e1c, 0 }, + { 0x01c01ff7, 0x0, 0x01f01ff7, 0 }, + { 0xfddfdffe, 0x0, 0xfddfdffe, 0 }, + { 0xfffeffe0, 0x0, 0xfffeffe0, 0 }, + { 0x00000000, 0x0, 0x00000000, 0 }, }; static const void *r8a7796_get_pll_config(const u32 cpg_mode) diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 5f37f6285f..8d792bceee 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -303,18 +303,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { }; static const struct mstp_stop_table r8a77965_mstp_table[] = { - { 0x00200000, 0x0, 0x00200000, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, - { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, - { 0x80000184, 0x180, 0x80000184, 0 }, - { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, - { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, - { 0x000000B7, 0x0, 0x000000B7, 0 }, + { 0x00210000, 0x0, 0x00210000, 0 }, + { 0xc3e813a0, 0x0, 0xc3e813a0, 0 }, + { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 }, + { 0xd0cc7cdf, 0x400, 0xd0cc7cdf, 0 }, + { 0x80000004, 0x180, 0x80000004, 0 }, + { 0x40dfff46, 0x0, 0x40dfff46, 0 }, + { 0x84c8888c, 0x0, 0x84c8888c, 0 }, + { 0x29bf5d1c, 0x0, 0x29bf5d1c, 0 }, + { 0x00c09ff7, 0x0, 0x01c09ff7, 0 }, + { 0xfddfdffe, 0x0, 0xfddfdffe, 0 }, + { 0xfffeffe0, 0x0, 0xfffeffe0, 0 }, + { 0x00000000, 0x0, 0x00000000, 0 }, }; static const void *r8a77965_get_pll_config(const u32 cpg_mode) diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index bafe4bbb09..b2b32be946 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -181,17 +181,17 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = { static const struct mstp_stop_table r8a77970_mstp_table[] = { { 0x00230000, 0x0, 0x00230000, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x14062FD8, 0x2040, 0x14062FD8, 0 }, - { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, - { 0x80000184, 0x180, 0x80000184, 0 }, - { 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 }, - { 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, - { 0x000000B7, 0x0, 0x000000B7, 0 }, + { 0x0be00000, 0x0, 0x0be00000, 0 }, + { 0x04062fd8, 0x2080, 0x04062fd8, 0 }, + { 0x00c0c0df, 0x0, 0x00c0c0df, 0 }, + { 0x80000004, 0x180, 0x80000004, 0 }, + { 0x00de0028, 0x0, 0x00de0028, 0 }, + { 0x00800008, 0x0, 0x00800008, 0 }, + { 0x09010000, 0x0, 0x09010000, 0 }, + { 0x7ff21f00, 0x0, 0x7ff21f00, 0 }, + { 0xf8025f84, 0x0, 0xf8025f84, 0 }, + { 0x00000000, 0x0, 0x00000000, 0 }, + { 0x00000000, 0x0, 0x00000000, 0 }, }; static const void *r8a77970_get_pll_config(const u32 cpg_mode) diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index a202005121..cf96309d12 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -203,18 +203,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = { }; static const struct mstp_stop_table r8a77980_mstp_table[] = { - { 0x00230000, 0x0, 0x00230000, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x14062FD8, 0x2040, 0x14062FD8, 0 }, - { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, - { 0x80000184, 0x180, 0x80000184, 0 }, - { 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 }, - { 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, - { 0x000000B7, 0x0, 0x000000B7, 0 }, + { 0x00230010, 0x0, 0x00230010, 0 }, + { 0x0be06c06, 0x0, 0x0be06c06, 0 }, + { 0x0006afd8, 0x2080, 0x0006afd8, 0 }, + { 0x00c8c0df, 0x0, 0x00c8c0df, 0 }, + { 0x80008004, 0x180, 0x80008004, 0 }, + { 0xbffe0021, 0x0, 0xbffe0021, 0 }, + { 0x1a841138, 0x0, 0x1a841138, 0 }, + { 0x090180c0, 0x0, 0x090180c0, 0 }, + { 0xfff27ff0, 0x0, 0xfff27ff0, 0 }, + { 0xf80a5f84, 0x0, 0xf80a5f84, 0 }, + { 0x0000001f, 0x0, 0x0000001f, 0 }, + { 0x00030000, 0x0, 0x00030000, 0 }, }; static const void *r8a77980_get_pll_config(const u32 cpg_mode) diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 5cc9270869..e983296b3a 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -263,18 +263,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = { }; static const struct mstp_stop_table r8a77990_mstp_table[] = { - { 0x00200000, 0x0, 0x00200000, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, - { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, - { 0x80000184, 0x180, 0x80000184, 0 }, - { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, - { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, - { 0x000000B7, 0x0, 0x000000B7, 0 }, + { 0x00210000, 0x0, 0x00210000, 0 }, + { 0xc3e81000, 0x0, 0xc3e81000, 0 }, + { 0x000e2fdc, 0x2000, 0x000e2fd8, 0 }, + { 0xd0c86cd7, 0x400, 0xd0c86cd7, 0 }, + { 0x80000004, 0x180, 0x80000004, 0 }, + { 0x40dfff44, 0x0, 0x40dfff44, 0 }, + { 0x84c8888c, 0x0, 0x84c8888c, 0 }, + { 0x09951c18, 0x0, 0x09951c18, 0 }, + { 0x008010c7, 0x0, 0x008010c7, 0 }, + { 0xfddfdfdc, 0x0, 0xfddfdfdc, 0 }, + { 0xfffeffe8, 0x0, 0xfffeffe8, 0 }, + { 0x00000000, 0x0, 0x00000000, 0 }, }; static const void *r8a77990_get_pll_config(const u32 cpg_mode) diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index eef154bc82..fb1df6d10e 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -202,18 +202,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = { }; static const struct mstp_stop_table r8a77995_mstp_table[] = { - { 0x00200000, 0x0, 0x00200000, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, - { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, - { 0x80000184, 0x180, 0x80000184, 0 }, - { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, - { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, - { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, - { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, - { 0x000000B7, 0x0, 0x000000B7, 0 }, + { 0x00210000, 0x0, 0x00210000, 0 }, + { 0x03e01000, 0x0, 0x03e01000, 0 }, + { 0x000e2fdc, 0x2000, 0x000e2fd8, 0 }, + { 0xc00014df, 0x400, 0xc00014df, 0 }, + { 0x80000004, 0x180, 0x80000004, 0 }, + { 0x40d20004, 0x0, 0x40d20004, 0 }, + { 0x08c0008c, 0x0, 0x08c0008c, 0 }, + { 0x09941c18, 0x0, 0x09941c18, 0 }, + { 0x00801087, 0x0, 0x00801087, 0 }, + { 0xf143dfc0, 0x0, 0xf143dfc0, 0 }, + { 0x063e1820, 0x0, 0x063e1820, 0 }, + { 0x00000000, 0x0, 0x00000000, 0 }, }; static const void *r8a77995_get_pll_config(const u32 cpg_mode) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index d862d1e202..f4ad1db45d 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -317,13 +317,13 @@ config MMC_PCI If you have an MMC controller on a PCI bus, say Y here. config MMC_OCTEONTX - bool "Marvell OcteonTX Multimedia Card Interface support" - depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2) + bool "Marvell Octeon Multimedia Card Interface support" + depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) depends on DM_MMC help - This selects the OcteonTX Multimedia card Interface. - If you have an OcteonTX/TX2 board with a Multimedia Card slot, - say Y here. + This selects the Octeon Multimedia card Interface. + If you have an OcteonTX/TX2 or MIPS Octeon board with a + Multimedia Card slot, say Y here. If unsure, say N. diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c index 442ca493d7..2e569a9e0f 100644 --- a/drivers/mmc/octeontx_hsmmc.c +++ b/drivers/mmc/octeontx_hsmmc.c @@ -1,13 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Marvell International Ltd. - * - * https://spdx.org/licenses */ -//#define DEBUG +#include <clk.h> #include <cpu_func.h> #include <dm.h> +#include <dm/device-internal.h> #include <dm/lists.h> #include <env.h> #include <errno.h> @@ -19,23 +18,31 @@ #include <part.h> #include <pci.h> #include <pci_ids.h> +#include <power/regulator.h> #include <time.h> #include <watchdog.h> - +#include <asm/io.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/libfdt.h> +#if defined(CONFIG_ARCH_OCTEON) +#include <mach/octeon-model.h> +#include <mach/cvmx-regs.h> +#include <mach/cvmx-mio-emm-defs.h> +#else #include <asm/arch/board.h> #include <asm/arch/clock.h> #include <asm/arch/csrs/csrs-mio_emm.h> -#include <asm/io.h> -#include <dm/device-internal.h> - -#include <power/regulator.h> +#endif #include "octeontx_hsmmc.h" +/* Use dummy implementation for MIPS Octeon to always return false */ +#if defined(CONFIG_ARCH_OCTEON) +#define otx_is_soc(ver) 0 +#endif + #define MMC_TIMEOUT_SHORT 20 /* in ms */ #define MMC_TIMEOUT_LONG 1000 #define MMC_TIMEOUT_ERASE 10000 @@ -71,16 +78,18 @@ #define MMC_DEFAULT_TAP_DELAY 4 #define TOTAL_NO_OF_TAPS 512 static void octeontx_mmc_switch_to(struct mmc *mmc); -static int octeontx_mmc_configure_delay(struct mmc *mmc); -static void octeontx_mmc_set_timing(struct mmc *mmc); static void set_wdog(struct mmc *mmc, u64 us); static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch); static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); -static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay); +static int octeontx_mmc_configure_delay(struct mmc *mmc); static int octeontx_mmc_calibrate_delay(struct mmc *mmc); +#if !defined(CONFIG_ARCH_OCTEON) +static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay); +static void octeontx_mmc_set_timing(struct mmc *mmc); static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc); static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc); +#endif static bool host_probed; @@ -338,6 +347,7 @@ static void mmc_print_status(u32 status) } #endif +#if !defined(CONFIG_ARCH_OCTEON) /** * Print out all of the register values where mmc is optional * @@ -687,6 +697,12 @@ static void octeontx_mmc_print_registers(struct mmc *mmc) if (print) octeontx_mmc_print_registers2(mmc, mmc_to_host(mmc)); } +#else +static void octeontx_mmc_print_registers(struct mmc *mmc) +{ + return; +} +#endif static const struct octeontx_sd_mods octeontx_cr_types[] = { { {0, 0}, {0, 0}, {0, 0} }, /* CMD0 */ @@ -838,14 +854,17 @@ static void octeontx_mmc_track_switch(struct mmc *mmc, u32 cmd_arg) break; case EXT_CSD_HS_TIMING: slot->want_switch.s.hs_timing = 0; +#if !defined(CONFIG_ARCH_OCTEON) slot->want_switch.s.hs200_timing = 0; slot->want_switch.s.hs400_timing = 0; +#endif switch (val & 0xf) { case 0: break; case 1: slot->want_switch.s.hs_timing = 1; break; +#if !defined(CONFIG_ARCH_OCTEON) case 2: if (!slot->is_asim && !slot->is_emul) slot->want_switch.s.hs200_timing = 1; @@ -854,6 +873,7 @@ static void octeontx_mmc_track_switch(struct mmc *mmc, u32 cmd_arg) if (!slot->is_asim && !slot->is_emul) slot->want_switch.s.hs400_timing = 1; break; +#endif default: pr_err("%s(%s): Unsupported timing mode 0x%x\n", __func__, mmc->dev->name, val & 0xf); @@ -2413,7 +2433,10 @@ static u32 octeontx_mmc_calc_clk_period(struct mmc *mmc) struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); struct octeontx_mmc_host *host = slot->host; - return DIV_ROUND_UP(host->sys_freq, mmc->clock); + if (mmc->clock) + return DIV_ROUND_UP(host->sys_freq, mmc->clock); + + return 0; } static int octeontx_mmc_set_ios(struct udevice *dev) @@ -2489,14 +2512,18 @@ static int octeontx_mmc_set_ios(struct udevice *dev) case UHS_SDR25: case UHS_SDR50: case UHS_SDR104: +#if !defined(CONFIG_ARCH_OCTEON) emm_switch.s.hs200_timing = 1; +#endif break; case MMC_HS_400: is_hs400 = true; fallthrough; case UHS_DDR50: case MMC_DDR_52: +#if !defined(CONFIG_ARCH_OCTEON) emm_switch.s.hs400_timing = 1; +#endif break; default: pr_err("%s(%s): Unsupported mode 0x%x\n", __func__, dev->name, @@ -2522,17 +2549,21 @@ static int octeontx_mmc_set_ios(struct udevice *dev) mmc->selected_mode); } +#if !defined(CONFIG_ARCH_OCTEON) debug(" Trying switch 0x%llx w%d hs:%d hs200:%d hs400:%d\n", emm_switch.u, emm_switch.s.bus_width, emm_switch.s.hs_timing, emm_switch.s.hs200_timing, emm_switch.s.hs400_timing); +#endif set_wdog(mmc, 1000); do_switch(mmc, emm_switch); mdelay(100); mode.u = read_csr(mmc, MIO_EMM_MODEX(slot->bus_id)); +#if !defined(CONFIG_ARCH_OCTEON) debug("%s(%s): mode: 0x%llx w:%d, hs:%d, hs200:%d, hs400:%d\n", __func__, dev->name, mode.u, mode.s.bus_width, mode.s.hs_timing, mode.s.hs200_timing, mode.s.hs400_timing); +#endif err = octeontx_mmc_configure_delay(mmc); @@ -2578,6 +2609,26 @@ static int octeontx_mmc_get_wp(struct udevice *dev) return val; } +#if defined(CONFIG_ARCH_OCTEON) +static int octeontx_mmc_configure_delay(struct mmc *mmc) +{ + struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); + union mio_emm_sample emm_sample; + + debug("%s(%s)\n", __func__, mmc->dev->name); + + emm_sample.u = 0; + emm_sample.s.cmd_cnt = slot->cmd_cnt; + emm_sample.s.dat_cnt = slot->dat_cnt; + write_csr(mmc, MIO_EMM_SAMPLE(), emm_sample.u); + + return 0; +} + +static void octeontx_mmc_io_drive_setup(struct mmc *mmc) +{ +} +#else static void octeontx_mmc_set_timing(struct mmc *mmc) { union mio_emm_timing timing; @@ -2613,7 +2664,8 @@ static int octeontx_mmc_configure_delay(struct mmc *mmc) debug("%s(%s)\n", __func__, mmc->dev->name); - if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { + if (IS_ENABLED(CONFIG_ARCH_OCTEON) || + IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { union mio_emm_sample emm_sample; emm_sample.u = 0; @@ -2760,6 +2812,28 @@ static int octeontx_mmc_configure_delay(struct mmc *mmc) } /** + * Set the IO drive strength and slew + * + * @param mmc mmc device + */ +static void octeontx_mmc_io_drive_setup(struct mmc *mmc) +{ + if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { + struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); + union mio_emm_io_ctl io_ctl; + + if (slot->drive < 0 || slot->slew < 0) + return; + + io_ctl.u = 0; + io_ctl.s.drive = slot->drive; + io_ctl.s.slew = slot->slew; + write_csr(mmc, MIO_EMM_IO_CTL(), io_ctl.u); + } +} +#endif + +/** * Sets the MMC watchdog timer in microseconds * * @param mmc mmc device @@ -2785,27 +2859,6 @@ static void set_wdog(struct mmc *mmc, u64 us) } /** - * Set the IO drive strength and slew - * - * @param mmc mmc device - */ -static void octeontx_mmc_io_drive_setup(struct mmc *mmc) -{ - if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) { - struct octeontx_mmc_slot *slot = mmc_to_slot(mmc); - union mio_emm_io_ctl io_ctl; - - if (slot->drive < 0 || slot->slew < 0) - return; - - io_ctl.u = 0; - io_ctl.s.drive = slot->drive; - io_ctl.s.slew = slot->slew; - write_csr(mmc, MIO_EMM_IO_CTL(), io_ctl.u); - } -} - -/** * Print switch errors * * @param mmc mmc device @@ -2859,6 +2912,31 @@ static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch) } /** + * Calibrates the delay based on the internal clock + * + * @param mmc Pointer to mmc data structure + * + * @return 0 for success or -ETIMEDOUT on error + * + * NOTE: On error a default value will be calculated. + */ +#if defined(CONFIG_ARCH_OCTEON) +static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc) +{ + return 0; +} + +static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc) +{ + return 0; +} + +static int octeontx_mmc_calibrate_delay(struct mmc *mmc) +{ + return 0; +} +#else +/** * Given a delay in ps, return the tap delay count * * @param mmc mmc data structure @@ -2883,15 +2961,6 @@ static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay) return min_t(int, DIV_ROUND_UP(delay, host->timing_taps), 63); } -/** - * Calibrates the delay based on the internal clock - * - * @param mmc Pointer to mmc data structure - * - * @return 0 for success or -ETIMEDOUT on error - * - * NOTE: On error a default value will be calculated. - */ static int octeontx_mmc_calibrate_delay(struct mmc *mmc) { union mio_emm_calb emm_calb; @@ -3141,6 +3210,7 @@ static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc) return 0; } +#endif static void octeontx_mmc_set_clock(struct mmc *mmc) { @@ -3389,8 +3459,10 @@ static u32 xlate_voltage(u32 voltage) { u32 volt = 0; - /* Convert to millivolts */ - voltage /= 1000; + /* Convert to millivolts. Only necessary on ARM Octeon TX/TX2 */ + if (!IS_ENABLED(CONFIG_ARCH_OCTEON)) + voltage /= 1000; + if (voltage >= 1650 && voltage <= 1950) volt |= MMC_VDD_165_195; if (voltage >= 2000 && voltage <= 2100) @@ -3736,6 +3808,8 @@ static int octeontx_mmc_host_probe(struct udevice *dev) { struct octeontx_mmc_host *host = dev_get_priv(dev); union mio_emm_int emm_int; + struct clk clk; + int ret; u8 rev; debug("%s(%s): Entry host: %p\n", __func__, dev->name, host); @@ -3745,12 +3819,20 @@ static int octeontx_mmc_host_probe(struct udevice *dev) return -ENODEV; } memset(host, 0, sizeof(*host)); - host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); - if (!host->base_addr) { - pr_err("%s: Error: MMC base address not found\n", __func__); - return -1; + + /* Octeon TX & TX2 use PCI based probing */ + if (device_is_compatible(dev, "cavium,thunder-8890-mmc")) { + host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + if (!host->base_addr) { + pr_err("%s: Error: MMC base address not found\n", + __func__); + return -1; + } + } else { + host->base_addr = dev_remap_addr(dev); } + host->dev = dev; debug("%s(%s): Base address: %p\n", __func__, dev->name, host->base_addr); @@ -3760,10 +3842,12 @@ static int octeontx_mmc_host_probe(struct udevice *dev) } host->node = dev_ofnode(dev); host->last_slotid = -1; +#if !defined(CONFIG_ARCH_OCTEON) if (otx_is_platform(PLATFORM_ASIM)) host->is_asim = true; if (otx_is_platform(PLATFORM_EMULATOR)) host->is_emul = true; +#endif host->dma_wait_delay = ofnode_read_u32_default(dev_ofnode(dev), "marvell,dma-wait-delay", 1); @@ -3776,7 +3860,15 @@ static int octeontx_mmc_host_probe(struct udevice *dev) writeq(emm_int.u, host->base_addr + MIO_EMM_INT()); debug("%s(%s): Getting I/O clock\n", __func__, dev->name); - host->sys_freq = octeontx_get_io_clock(); + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + host->sys_freq = clk_get_rate(&clk); debug("%s(%s): I/O clock %llu\n", __func__, dev->name, host->sys_freq); if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { @@ -3882,6 +3974,7 @@ static int octeontx_mmc_host_child_pre_probe(struct udevice *dev) static const struct udevice_id octeontx_hsmmc_host_ids[] = { { .compatible = "cavium,thunder-8890-mmc" }, + { .compatible = "cavium,octeon-7360-mmc" }, { } }; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 9642d7c7dc..9c27fea5d8 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -2276,12 +2276,12 @@ ulong flash_get_size(phys_addr_t base, int banknum) flash_unlock_seq(info, 0); flash_write_cmd(info, 0, info->addr_unlock1, - FLASH_CMD_READ_ID); + AMD_CMD_SET_PPB_ENTRY); info->protect[sect_cnt] = - flash_isset( - info, sect_cnt, - FLASH_OFFSET_PROTECT, - FLASH_STATUS_PROTECT); + !flash_isset(info, sect_cnt, + 0, 0x01); + flash_write_cmd(info, 0, 0, + info->cmd_reset); break; default: /* default: not protected */ diff --git a/drivers/net/designware.c b/drivers/net/designware.c index b8ba00b7c0..5d92257e74 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -91,9 +91,8 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, } #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) -static int dw_mdio_reset(struct mii_dev *bus) +static int __dw_mdio_reset(struct udevice *dev) { - struct udevice *dev = bus->priv; struct dw_eth_dev *priv = dev_get_priv(dev); struct dw_eth_pdata *pdata = dev_get_plat(dev); int ret; @@ -122,6 +121,13 @@ static int dw_mdio_reset(struct mii_dev *bus) return 0; } + +static int dw_mdio_reset(struct mii_dev *bus) +{ + struct udevice *dev = bus->priv; + + return __dw_mdio_reset(dev); +} #endif #if IS_ENABLED(CONFIG_DM_MDIO) @@ -142,9 +148,10 @@ int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int #if CONFIG_IS_ENABLED(DM_GPIO) int designware_eth_mdio_reset(struct udevice *mdio_dev) { - struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); + struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev); + struct udevice *dev = mdio_pdata->mii_bus->priv; - return dw_mdio_reset(pdata->mii_bus); + return __dw_mdio_reset(dev->parent); } #endif diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c index 128d7f21ce..570d5a5109 100644 --- a/drivers/net/mscc_eswitch/jr2_switch.c +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -235,7 +235,7 @@ static const char * const regs_names[] = { "port36", "port37", "port38", "port39", "port40", "port41", "port42", "port43", "port44", "port45", "port46", "port47", "ana_ac", "ana_cl", "ana_l2", "asm", "hsio", "lrn", - "qfwd", "qs", "qsys", "rew", + "qfwd", "qs", "qsys", "rew", "gcb", "icpu", }; #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1 @@ -252,6 +252,8 @@ enum jr2_ctrl_regs { QS, QSYS, REW, + GCB, + ICPU, }; #define JR2_MIIM_BUS_COUNT 3 @@ -367,7 +369,6 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr, { u32 ib_if_mode = 0; u32 ib_qrate = 0; - u32 ib_cal_ena = 0; u32 ib1_tsdet = 0; u32 ob_lev = 0; u32 ob_ena_cas = 0; @@ -379,7 +380,6 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr, case PHY_INTERFACE_MODE_SGMII: ib_if_mode = 1; ib_qrate = 1; - ib_cal_ena = 1; ib1_tsdet = 3; ob_lev = 48; ob_ena_cas = 2; @@ -402,6 +402,12 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr, if (interface == PHY_INTERFACE_MODE_QSGMII) writel(0xfff, base + HSIO_HW_CFGSTAT_HW_CFG); + writel(HSIO_ANA_SERDES6G_OB_CFG_RESISTOR_CTRL(1) | + HSIO_ANA_SERDES6G_OB_CFG_SR(7) | + HSIO_ANA_SERDES6G_OB_CFG_SR_H | + HSIO_ANA_SERDES6G_OB_CFG_ENA1V_MODE(ob_ena1v_mode) | + HSIO_ANA_SERDES6G_OB_CFG_POL, base + HSIO_ANA_SERDES6G_OB_CFG); + writel(HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(3), base + HSIO_ANA_SERDES6G_COMMON_CFG); writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(120) | @@ -431,6 +437,21 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr, HSIO_ANA_SERDES6G_IB_CFG1_TSDET(3) | HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8), base + HSIO_ANA_SERDES6G_IB_CFG1); + + writel(HSIO_ANA_SERDES6G_IB_CFG2_UREG(4) | + HSIO_ANA_SERDES6G_IB_CFG2_UMAX(2) | + HSIO_ANA_SERDES6G_IB_CFG2_TCALV(12) | + HSIO_ANA_SERDES6G_IB_CFG2_OCALS(32) | + HSIO_ANA_SERDES6G_IB_CFG2_OINFS(7) | + HSIO_ANA_SERDES6G_IB_CFG2_OINFI(0x1f) | + HSIO_ANA_SERDES6G_IB_CFG2_TINFV(3), + base + HSIO_ANA_SERDES6G_IB_CFG2); + + writel(HSIO_ANA_SERDES6G_IB_CFG3_INI_OFFSET(0x1f) | + HSIO_ANA_SERDES6G_IB_CFG3_INI_LP(1) | + HSIO_ANA_SERDES6G_IB_CFG3_INI_MID(0x1f), + base + HSIO_ANA_SERDES6G_IB_CFG3); + writel(HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST, base + HSIO_DIG_SERDES6G_MISC_CFG); @@ -505,7 +526,7 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr, writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA | HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA | HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA | - HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(ib_cal_ena) | + HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(1) | HSIO_ANA_SERDES6G_IB_CFG_CONCUR | HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA | HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) | @@ -530,7 +551,7 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr, writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA | HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA | HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA | - HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(ib_cal_ena) | + HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(1) | HSIO_ANA_SERDES6G_IB_CFG_CONCUR | HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA | HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) | @@ -850,6 +871,7 @@ static int jr2_probe(struct udevice *dev) struct mii_dev *bus; struct ofnode_phandle_args phandle; struct phy_device *phy; + u32 val; if (!priv) return -EINVAL; @@ -865,6 +887,17 @@ static int jr2_probe(struct udevice *dev) } } + val = readl(priv->regs[ICPU] + ICPU_RESET); + val |= ICPU_RESET_CORE_RST_PROTECT; + writel(val, priv->regs[ICPU] + ICPU_RESET); + + val = readl(priv->regs[GCB] + PERF_SOFT_RST); + val |= PERF_SOFT_RST_SOFT_SWC_RST; + writel(val, priv->regs[GCB] + PERF_SOFT_RST); + + while (readl(priv->regs[GCB] + PERF_SOFT_RST) & PERF_SOFT_RST_SOFT_SWC_RST) + ; + /* Initialize miim buses */ memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT); diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a6cdda81a7..5a1b38bf80 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -554,7 +554,7 @@ static int parse_phy_pins(struct udevice *dev) * The GPIO pinmux value is an integration choice, so depends on the * SoC, not the EMAC variant. */ - if (IS_ENABLED(CONFIG_MACH_SUN8I_H3)) + if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) iomux = SUN8I_IOMUX_H3; else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) iomux = SUN8I_IOMUX_R40; @@ -562,8 +562,12 @@ static int parse_phy_pins(struct udevice *dev) iomux = SUN8I_IOMUX_H6; else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) iomux = SUN8I_IOMUX_H616; - else + else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T)) + iomux = SUN8I_IOMUX; + else if (IS_ENABLED(CONFIG_MACH_SUN50I)) iomux = SUN8I_IOMUX; + else + BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins"); for (i = 0; ; i++) { int pin; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index cdcdd8f456..d5b6018b3d 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -158,6 +158,12 @@ config PCI_OCTEONTX These controllers provide PCI configuration access to all on-board peripherals so it should only be disabled for testing purposes +config PCIE_OCTEON + bool "MIPS Octeon PCIe support" + depends on ARCH_OCTEON + help + Enable support for the MIPS Octeon SoC family PCIe controllers. + config PCI_XILINX bool "Xilinx AXI Bridge for PCI Express" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 96d61821fe..1f741786a0 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o +obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 3b9309f52c..c43d4f309b 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -132,8 +132,9 @@ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) /* PCIe Retries & Timeout definitions */ -#define MAX_RETRIES 10 -#define PIO_WAIT_TIMEOUT 100 +#define PIO_MAX_RETRIES 1500 +#define PIO_WAIT_TIMEOUT 1000 +#define LINK_MAX_RETRIES 10 #define LINK_WAIT_TIMEOUT 100000 #define CFG_RD_UR_VAL 0xFFFFFFFF @@ -192,7 +193,7 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno) * * @pcie: The PCI device to access * - * Wait up to 1 micro second for PIO access to be accomplished. + * Wait up to 1.5 seconds for PIO access to be accomplished. * * Return 1 (true) if PIO access is accomplished. * Return 0 (false) if PIO access is timed out. @@ -202,7 +203,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) uint start, isr; uint count; - for (count = 0; count < MAX_RETRIES; count++) { + for (count = 0; count < PIO_MAX_RETRIES; count++) { start = advk_readl(pcie, PIO_START); isr = advk_readl(pcie, PIO_ISR); if (!start && isr) @@ -214,7 +215,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) udelay(PIO_WAIT_TIMEOUT); } - dev_err(pcie->dev, "config read/write timed out\n"); + dev_err(pcie->dev, "PIO read/write transfer time out\n"); return 0; } @@ -323,9 +324,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - /* Start PIO */ - advk_writel(pcie, 0, PIO_START); - advk_writel(pcie, 1, PIO_ISR); + if (advk_readl(pcie, PIO_START)) { + dev_err(pcie->dev, + "Previous PIO read/write transfer is still running\n"); + if (offset != PCI_VENDOR_ID) + return -EINVAL; + *valuep = CFG_RD_CRS_VAL; + return 0; + } /* Program the control register */ reg = advk_readl(pcie, PIO_CTRL); @@ -342,10 +348,15 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, advk_writel(pcie, 0, PIO_ADDR_MS); /* Start the transfer */ + advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); - if (!pcie_advk_wait_pio(pcie)) - return -EINVAL; + if (!pcie_advk_wait_pio(pcie)) { + if (offset != PCI_VENDOR_ID) + return -EINVAL; + *valuep = CFG_RD_CRS_VAL; + return 0; + } /* Check PIO status and get the read result */ ret = pcie_advk_check_pio_status(pcie, true, ®); @@ -420,9 +431,11 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, return 0; } - /* Start PIO */ - advk_writel(pcie, 0, PIO_START); - advk_writel(pcie, 1, PIO_ISR); + if (advk_readl(pcie, PIO_START)) { + dev_err(pcie->dev, + "Previous PIO read/write transfer is still running\n"); + return -EINVAL; + } /* Program the control register */ reg = advk_readl(pcie, PIO_CTRL); @@ -450,6 +463,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg); /* Start the transfer */ + advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); if (!pcie_advk_wait_pio(pcie)) { @@ -494,7 +508,7 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie) int retries; /* check if the link is up or not */ - for (retries = 0; retries < MAX_RETRIES; retries++) { + for (retries = 0; retries < LINK_MAX_RETRIES; retries++) { if (pcie_advk_link_up(pcie)) { printf("PCIE-%d: Link up\n", pcie->first_busno); return 0; diff --git a/drivers/pci/pcie_octeon.c b/drivers/pci/pcie_octeon.c new file mode 100644 index 0000000000..3b28bd8143 --- /dev/null +++ b/drivers/pci/pcie_octeon.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Stefan Roese <sr@denx.de> + */ + +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <log.h> +#include <pci.h> +#include <linux/delay.h> + +#include <mach/octeon-model.h> +#include <mach/octeon_pci.h> +#include <mach/cvmx-regs.h> +#include <mach/cvmx-pcie.h> +#include <mach/cvmx-pemx-defs.h> + +struct octeon_pcie { + void *base; + int first_busno; + u32 port; + struct udevice *dev; + int pcie_port; +}; + +static bool octeon_bdf_invalid(pci_dev_t bdf, int first_busno) +{ + /* + * In PCIe only a single device (0) can exist on the local bus. + * Beyound the local bus, there might be a switch and everything + * is possible. + */ + if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0)) + return true; + + return false; +} + +static int pcie_octeon_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct octeon_pcie *pcie = dev_get_priv(bus); + struct pci_controller *hose = dev_get_uclass_priv(bus); + int busno; + int port; + + debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value); + + port = pcie->pcie_port; + busno = PCI_BUS(bdf) - hose->first_busno + 1; + + switch (size) { + case PCI_SIZE_8: + cvmx_pcie_config_write8(port, busno, PCI_DEV(bdf), + PCI_FUNC(bdf), offset, value); + break; + case PCI_SIZE_16: + cvmx_pcie_config_write16(port, busno, PCI_DEV(bdf), + PCI_FUNC(bdf), offset, value); + break; + case PCI_SIZE_32: + cvmx_pcie_config_write32(port, busno, PCI_DEV(bdf), + PCI_FUNC(bdf), offset, value); + break; + default: + printf("Invalid size\n"); + }; + + return 0; +} + +static int pcie_octeon_read_config(const struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct octeon_pcie *pcie = dev_get_priv(bus); + struct pci_controller *hose = dev_get_uclass_priv(bus); + int busno; + int port; + + port = pcie->pcie_port; + busno = PCI_BUS(bdf) - hose->first_busno + 1; + if (octeon_bdf_invalid(bdf, pcie->first_busno)) { + *valuep = pci_get_ff(size); + return 0; + } + + switch (size) { + case PCI_SIZE_8: + *valuep = cvmx_pcie_config_read8(port, busno, PCI_DEV(bdf), + PCI_FUNC(bdf), offset); + break; + case PCI_SIZE_16: + *valuep = cvmx_pcie_config_read16(port, busno, PCI_DEV(bdf), + PCI_FUNC(bdf), offset); + break; + case PCI_SIZE_32: + *valuep = cvmx_pcie_config_read32(port, busno, PCI_DEV(bdf), + PCI_FUNC(bdf), offset); + break; + default: + printf("Invalid size\n"); + }; + + debug("%02x.%02x.%02x: u%d %x -> %lx\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep); + + return 0; +} + +static int pcie_octeon_probe(struct udevice *dev) +{ + struct octeon_pcie *pcie = dev_get_priv(dev); + int node = cvmx_get_node_num(); + int pcie_port; + int ret = 0; + + /* Get port number, lane number and memory target / attr */ + if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port", + &pcie->port)) { + ret = -ENODEV; + goto err; + } + + pcie->first_busno = dev_seq(dev); + pcie_port = ((node << 4) | pcie->port); + ret = cvmx_pcie_rc_initialize(pcie_port); + if (ret != 0) + return ret; + + return 0; + +err: + return ret; +} + +static const struct dm_pci_ops pcie_octeon_ops = { + .read_config = pcie_octeon_read_config, + .write_config = pcie_octeon_write_config, +}; + +static const struct udevice_id pcie_octeon_ids[] = { + { .compatible = "marvell,pcie-host-octeon" }, + { } +}; + +U_BOOT_DRIVER(pcie_octeon) = { + .name = "pcie_octeon", + .id = UCLASS_PCI, + .of_match = pcie_octeon_ids, + .ops = &pcie_octeon_ops, + .probe = pcie_octeon_probe, + .priv_auto = sizeof(struct octeon_pcie), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 12523d18a8..06822d1d12 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -17,33 +17,33 @@ DECLARE_GLOBAL_DATA_PTR; struct comphy_mux_data a3700_comphy_mux_data[] = { -/* Lane 0 */ + /* Lane 0 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0 }, - { PHY_TYPE_SGMII1, 0x0 }, - { PHY_TYPE_USB3_HOST0, 0x1 }, - { PHY_TYPE_USB3_DEVICE, 0x1 } + { COMPHY_TYPE_UNCONNECTED, 0x0 }, + { COMPHY_TYPE_SGMII1, 0x0 }, + { COMPHY_TYPE_USB3_HOST0, 0x1 }, + { COMPHY_TYPE_USB3_DEVICE, 0x1 } } }, -/* Lane 1 */ + /* Lane 1 */ { 3, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SGMII0, 0x0}, - { PHY_TYPE_PEX0, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SGMII0, 0x0}, + { COMPHY_TYPE_PEX0, 0x1} } }, -/* Lane 2 */ + /* Lane 2 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SATA0, 0x0}, - { PHY_TYPE_USB3_HOST0, 0x1}, - { PHY_TYPE_USB3_DEVICE, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SATA0, 0x0}, + { COMPHY_TYPE_USB3_HOST0, 0x1}, + { COMPHY_TYPE_USB3_DEVICE, 0x1} } }, }; @@ -228,10 +228,10 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) /* * 10. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); /* @@ -284,10 +284,10 @@ static int comphy_sata_power_up(u32 invert) /* * 0. Check the Polarity invert bits */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) data |= bs_txd_inv; - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) data |= bs_rxd_inv; reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv); @@ -465,10 +465,10 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 9. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane); /* @@ -513,7 +513,7 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) * Set Soft ID for Host mode (Device mode works with Hard ID * detection) */ - if (type == PHY_TYPE_USB3_HOST0) { + if (type == COMPHY_TYPE_USB3_HOST0) { /* * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) * clear BIT1: set SOFT_ID = Host @@ -685,8 +685,8 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) * comparison to 3.125 Gbps values. These register values are * stored in "sgmii_phy_init_fix" array. */ - if ((speed != PHY_SPEED_1_25G) && - (sgmii_phy_init_fix[fix_idx].addr == addr)) { + if (speed != COMPHY_SPEED_1_25G && + sgmii_phy_init_fix[fix_idx].addr == addr) { /* Use new value */ val = sgmii_phy_init_fix[fix_idx].value; if (fix_idx < fix_arr_sz) @@ -737,13 +737,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide * COMPHY bit rate */ - if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ + if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x8 << rf_gen_rx_sel_shift) | (0x8 << rf_gen_tx_sel_shift), rf_gen_rx_select | rf_gen_tx_select); - } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ + } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x6 << rf_gen_rx_sel_shift) | (0x6 << rf_gen_tx_sel_shift), @@ -819,7 +819,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * registers are OK. */ debug("Running C-DPI phy init %s mode\n", - speed == PHY_SPEED_3_125G ? "2G5" : "1G"); + speed == COMPHY_SPEED_3_125G ? "2G5" : "1G"); if (get_ref_clk() == 40) comphy_sgmii_phy_init(lane, speed); @@ -837,10 +837,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 18. Check the PHY Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); /* @@ -976,30 +976,30 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, comphy_map->type, comphy_map->invert); switch (comphy_map->type) { - case PHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_UNCONNECTED: continue; break; - case PHY_TYPE_PEX0: + case COMPHY_TYPE_PEX0: ret = comphy_pcie_power_up(comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, comphy_map->type, comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: ret = comphy_sgmii_power_up(lane, comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_SATA0: + case COMPHY_TYPE_SATA0: ret = comphy_sata_power_up(comphy_map->invert); break; diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index b0941ffb37..8748c6c84a 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -7,7 +7,6 @@ #define _COMPHY_A3700_H_ #include "comphy_core.h" -#include "comphy_hpipe.h" #define MVEBU_REG(offs) \ ((void __iomem *)(ulong)MVEBU_REGISTER(offs)) diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index cd54e7f889..2c9d7b2288 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -24,12 +24,12 @@ DECLARE_GLOBAL_DATA_PTR; static const char *get_speed_string(u32 speed) { static const char * const speed_strings[] = { - "1.25 Gbps", "1.5 Gbps", "2.5 Gbps", - "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps", - "6.25 Gbps", "10.31 Gbps" + "1.25 Gbps", "2.5 Gbps", "3.125 Gbps", + "5 Gbps", "5.125 Gpbs", "6 Gbps", + "10.3125 Gbps" }; - if (speed < 0 || speed > PHY_SPEED_MAX) + if (speed < 0 || speed > COMPHY_SPEED_MAX) return "invalid"; return speed_strings[speed]; @@ -39,14 +39,13 @@ static const char *get_type_string(u32 type) { static const char * const type_strings[] = { "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", - "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0", - "SGMII1", "SGMII2", "SGMII3", "QSGMII", - "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", - "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "SFI", "IGNORE" + "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2", + "USB3", "USB3_HOST0", "USB3_HOST1", + "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP", + "IGNORE" }; - if (type < 0 || type > PHY_TYPE_MAX) + if (type < 0 || type > COMPHY_TYPE_MAX) return "invalid"; return type_strings[type]; @@ -59,7 +58,7 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg, for (lane = 0; lane < chip_cfg->comphy_lanes_count; lane++, comphy_map_data++) { - if (comphy_map_data->speed == PHY_SPEED_INVALID) { + if (comphy_map_data->speed == COMPHY_SPEED_INVALID) { printf("Comphy-%d: %-13s\n", lane, get_type_string(comphy_map_data->type)); } else { @@ -70,6 +69,16 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg, } } +int comphy_rx_training(struct udevice *dev, u32 lane) +{ + struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev); + + if (chip_cfg->rx_training) + return chip_cfg->rx_training(chip_cfg, lane); + + return 0; +} + __weak int comphy_update_map(struct comphy_map *serdes_map, int count) { return 0; @@ -80,7 +89,6 @@ static int comphy_probe(struct udevice *dev) const void *blob = gd->fdt_blob; int node = dev_of_offset(dev); struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev); - struct comphy_map comphy_map_data[MAX_LANE_OPTIONS]; int subnode; int lane; int last_idx = 0; @@ -114,11 +122,15 @@ static int comphy_probe(struct udevice *dev) fdtdec_locate_array(blob, node, "mux-lane-order", chip_cfg->comphy_lanes_count); - if (device_is_compatible(dev, "marvell,comphy-armada-3700")) + if (device_is_compatible(dev, "marvell,comphy-armada-3700")) { chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; + chip_cfg->rx_training = NULL; + } - if (device_is_compatible(dev, "marvell,comphy-cp110")) + if (device_is_compatible(dev, "marvell,comphy-cp110")) { chip_cfg->ptr_comphy_chip_init = comphy_cp110_init; + chip_cfg->rx_training = comphy_cp110_sfi_rx_training; + } /* * Bail out if no chip_init function is defined, e.g. no @@ -135,36 +147,45 @@ static int comphy_probe(struct udevice *dev) if (!fdtdec_get_is_enabled(blob, subnode)) continue; - comphy_map_data[lane].speed = fdtdec_get_int( - blob, subnode, "phy-speed", PHY_TYPE_INVALID); - comphy_map_data[lane].type = fdtdec_get_int( - blob, subnode, "phy-type", PHY_SPEED_INVALID); - comphy_map_data[lane].invert = fdtdec_get_int( - blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT); - comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, - "clk-src"); - comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode, - "end_point"); - if (comphy_map_data[lane].type == PHY_TYPE_INVALID) { + chip_cfg->comphy_map_data[lane].type = + fdtdec_get_int(blob, subnode, "phy-type", + COMPHY_TYPE_INVALID); + + if (chip_cfg->comphy_map_data[lane].type == + COMPHY_TYPE_INVALID) { printf("no phy type for lane %d, setting lane as unconnected\n", lane + 1); + continue; } + chip_cfg->comphy_map_data[lane].speed = + fdtdec_get_int(blob, subnode, "phy-speed", + COMPHY_SPEED_INVALID); + + chip_cfg->comphy_map_data[lane].invert = + fdtdec_get_int(blob, subnode, "phy-invert", + COMPHY_POLARITY_NO_INVERT); + + chip_cfg->comphy_map_data[lane].clk_src = + fdtdec_get_bool(blob, subnode, "clk-src"); + + chip_cfg->comphy_map_data[lane].end_point = + fdtdec_get_bool(blob, subnode, "end_point"); + lane++; } - res = comphy_update_map(comphy_map_data, chip_cfg->comphy_lanes_count); + res = comphy_update_map(chip_cfg->comphy_map_data, chip_cfg->comphy_lanes_count); if (res < 0) return res; /* Save CP index for MultiCP devices (A8K) */ chip_cfg->cp_index = current_idx++; /* PHY power UP sequence */ - chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data); + chip_cfg->ptr_comphy_chip_init(chip_cfg, chip_cfg->comphy_map_data); /* PHY print SerDes status */ - if (of_machine_is_compatible("marvell,armada8040")) - printf("Comphy chip #%d:\n", chip_cfg->cp_index); - comphy_print(chip_cfg, comphy_map_data); + printf("Comphy chip #%d:\n", chip_cfg->cp_index); + comphy_print(chip_cfg, chip_cfg->comphy_map_data); /* * Only run the dedicated PHY init code once, in the last PHY init call diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h index 12ab921d24..ba64491dfe 100644 --- a/drivers/phy/marvell/comphy_core.h +++ b/drivers/phy/marvell/comphy_core.h @@ -17,58 +17,8 @@ #define debug_exit() #endif -/* COMPHY registers */ -#define COMMON_PHY_CFG1_REG 0x0 -#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 -#define COMMON_PHY_CFG1_PWR_UP_MASK \ - (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) -#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 -#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ - (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) -#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13 -#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ - (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) -#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 -#define COMMON_PHY_CFG1_CORE_RSTN_MASK \ - (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) -#define COMMON_PHY_PHY_MODE_OFFSET 15 -#define COMMON_PHY_PHY_MODE_MASK \ - (0x1 << COMMON_PHY_PHY_MODE_OFFSET) - -#define COMMON_PHY_CFG6_REG 0x14 -#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 -#define COMMON_PHY_CFG6_IF_40_SEL_MASK \ - (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) - -#define COMMON_SELECTOR_PHY_OFFSET 0x140 -#define COMMON_SELECTOR_PIPE_OFFSET 0x144 - -#define COMMON_PHY_SD_CTRL1 0x148 -#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0 -#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ - (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ - (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) -#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 -#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \ - (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) -#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 -#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \ - (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET) - -/* ToDo: Get this address via DT */ -#define MVEBU_CP0_REGS_BASE 0xF2000000UL - -#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280) -#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 -#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ - (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) - #define MAX_LANE_OPTIONS 10 -#define MAX_UTMI_PHY_COUNT 3 +#define MAX_UTMI_PHY_COUNT 6 struct comphy_mux_options { u32 type; @@ -84,12 +34,14 @@ struct chip_serdes_phy_config { struct comphy_mux_data *mux_data; int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *, struct comphy_map *); + int (*rx_training)(struct chip_serdes_phy_config *, u32); void __iomem *comphy_base_addr; void __iomem *hpipe3_base_addr; u32 comphy_lanes_count; u32 comphy_mux_bitcount; const fdt32_t *comphy_mux_lane_order; u32 cp_index; + struct comphy_map comphy_map_data[MAX_LANE_OPTIONS]; }; /* Register helper functions */ @@ -150,6 +102,8 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg, #ifdef CONFIG_ARMADA_8K int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map); +int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane); #else static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map) @@ -160,6 +114,17 @@ static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, */ return -1; } + +static inline int comphy_cp110_sfi_rx_training( + struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane) +{ + /* + * This function should never be called in this configuration, so + * lets return an error here. + */ + return -1; +} #endif void comphy_dedicated_phys_init(void); diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index a323de7c76..418318d12f 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -14,20 +14,16 @@ #include <linux/delay.h> #include "comphy_core.h" -#include "comphy_hpipe.h" #include "sata.h" #include "utmi_phy.h" DECLARE_GLOBAL_DATA_PTR; -#define SD_ADDR(base, lane) (base + 0x1000 * lane) -#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) -#define COMPHY_ADDR(base, lane) (base + 0x28 * lane) - /* Firmware related definitions used for SMC calls */ #define MV_SIP_COMPHY_POWER_ON 0x82000001 #define MV_SIP_COMPHY_POWER_OFF 0x82000002 #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 +#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004 /* Used to distinguish between different possible callers (U-boot/Linux) */ #define COMPHY_CALLER_UBOOT (0x1 << 21) @@ -59,52 +55,13 @@ DECLARE_GLOBAL_DATA_PTR; #define COMPHY_UNIT_ID3 3 struct utmi_phy_data { + void __iomem *utmi_pll_addr; void __iomem *utmi_base_addr; void __iomem *usb_cfg_addr; void __iomem *utmi_cfg_addr; u32 utmi_phy_port; }; -/* - * For CP-110 we have 2 Selector registers "PHY Selectors", - * and "PIPE Selectors". - * PIPE selector include USB and PCIe options. - * PHY selector include the Ethernet and SATA options, every Ethernet - * option has different options, for example: serdes lane2 had option - * Eth_port_0 that include (SGMII0, RXAUI0, SFI) - */ -struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ - {PHY_TYPE_SATA1, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ - {PHY_TYPE_SATA0, 0x4} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ - {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, - {PHY_TYPE_SATA0, 0x4} } }, - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ - {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII1, 0x1} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ - {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, -}; - -struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, - {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ - {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ - {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ -}; - static u32 polling_with_timeout(void __iomem *addr, u32 val, u32 mask, unsigned long usec_timout) { @@ -121,128 +78,6 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val, return 0; } -static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) -{ - u32 mask, data, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; - - debug_enter(); - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - mask |= COMMON_PHY_PHY_MODE_MASK; - data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* release from hard reset */ - mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); - - /* Start comphy Configuration */ - debug("stage: Comphy configuration\n"); - /* Set PIPE soft reset */ - mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - /* Set PHY datapath width mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - /* Set Data bus width USB mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - /* Set CORE_CLK output frequency for 250Mhz */ - mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); - /* Set PLL ready delay for 0x2 */ - reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); - /* Set reference clock to come from group 1 - 25Mhz */ - reg_set(hpipe_addr + HPIPE_MISC_REG, - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - /* Set reference frequcency select - 0x2 */ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - /* Set PHY mode to USB - 0x5 */ - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - /* Set the amount of time spent in the LoZ state - set for 0x7 */ - reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - /* Set max PHY generation setting - 5Gbps */ - reg_set(hpipe_addr + HPIPE_INTERFACE_REG, - 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, - HPIPE_INTERFACE_GEN_MAX_MASK); - /* Set select data width 20Bit (SEL_BITS[2:0]) */ - reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, - HPIPE_LOOPBACK_SEL_MASK); - /* select de-emphasize 3.5db */ - reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, - 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, - HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); - /* override tx margining from the MAC */ - reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, - 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, - HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); - - /* Start analog paramters from ETP(HW) */ - debug("stage: Analog paramters from ETP(HW)\n"); - /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ - mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; - data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; - /* Set Override PHY DFE control pins for 0x1 */ - mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; - data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; - /* Set Spread Spectrum Clock Enable fot 0x1 */ - mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; - data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); - /* End of analog parameters */ - - debug("stage: Comphy power up\n"); - /* Release from PIPE soft reset */ - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* wait 15ms - for comphy calibration done */ - debug("stage: Check PLL\n"); - /* Read lane status */ - addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; - data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - hpipe_addr + HPIPE_LANE_STATUS1_REG, data); - pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); - ret = 0; - } - - debug_exit(); - return ret; -} - static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr, u32 lane, u32 mode) { @@ -263,6 +98,35 @@ static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr, return pregs.regs[0] ? 0 : 1; } +/* This function performs RX training for all FFE possible values. + * We get the result for each FFE and eventually the best FFE will + * be used and set to the HW. + * + * Return '1' on succsess. + * Return '0' on failure. + */ +int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane) +{ + int ret; + u32 type = ptr_chip_cfg->comphy_map_data[lane].type; + + debug_enter(); + + if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) { + pr_err("Comphy %d isn't configured to SFI\n", lane); + return 0; + } + + /* Mode is not relevant for xfi training */ + ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN, + ptr_chip_cfg->comphy_base_addr, lane, 0); + + debug_exit(); + + return ret; +} + static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, void __iomem *comphy_base_addr, int cp_index, u32 type) @@ -357,184 +221,6 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, return ret; } -static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) -{ - u32 mask, data, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; - - debug_enter(); - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - if (lane == 2) { - reg_set(comphy_base + COMMON_PHY_SD_CTRL1, - 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, - COMMON_PHY_SD_CTRL1_RXAUI0_MASK); - } - if (lane == 4) { - reg_set(comphy_base + COMMON_PHY_SD_CTRL1, - 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, - COMMON_PHY_SD_CTRL1_RXAUI1_MASK); - } - - /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ - mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; - data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; - data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); - - /* release from hard reset */ - mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; - data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); - - /* Start comphy Configuration */ - debug("stage: Comphy configuration\n"); - /* set reference clock */ - reg_set(hpipe_addr + HPIPE_MISC_REG, - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - /* Power and PLL Control */ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - /* Loopback register */ - reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); - /* rx control 1 */ - mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; - data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; - mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; - data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); - /* DTL Control */ - reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, - 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, - HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); - - /* Set analog paramters from ETP(HW) */ - debug("stage: Analog paramters from ETP(HW)\n"); - /* SERDES External Configuration 2 */ - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, - 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, - SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); - /* 0x7-DFE Resolution control */ - reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, - HPIPE_DFE_RES_FORCE_MASK); - /* 0xd-G1_Setting_0 */ - reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, - 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, - HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); - /* 0xE-G1_Setting_1 */ - mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; - data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); - /* 0xA-DFE_Reg3 */ - mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; - data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; - mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; - data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; - reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); - - /* 0x111-G1_Setting_4 */ - mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; - data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; - reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); - - debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); - /* SERDES External Configuration */ - mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; - data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; - mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); - - - /* check PLL rx & tx ready */ - addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | - SD_EXTERNAL_STATUS0_PLL_TX_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", - (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), - (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); - ret = 0; - } - - /* RX init */ - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, - 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, - SD_EXTERNAL_CONFIG1_RX_INIT_MASK); - - /* check that RX init done */ - addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 100); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); - ret = 0; - } - - debug("stage: RF Reset\n"); - /* RF Reset */ - mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; - data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; - mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; - data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; - reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); - - debug_exit(); - return ret; -} - static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, void __iomem *usb_cfg_addr, void __iomem *utmi_cfg_addr, @@ -580,7 +266,8 @@ static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, return; } -static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, +static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr, + void __iomem *utmi_base_addr, void __iomem *usb_cfg_addr, void __iomem *utmi_cfg_addr, u32 utmi_phy_port) @@ -598,27 +285,37 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; - reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); + reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask); /* Impedance Calibration Threshold Setting */ - reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, - UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); + mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; + data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; + reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask); + + /* Start Impedance and PLL Calibration */ + mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; + data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); + mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; + data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); + reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask); /* Set LS TX driver strength coarse control */ - mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; - data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; - /* Set LS TX driver fine adjustment */ + mask = UTMI_TX_CH_CTRL_AMP_MASK; + data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; + mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; + data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); /* Enable SQ */ mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; - data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; + data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; /* Enable analog squelch detect */ mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; - data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; + data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; + mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; + data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); /* Set External squelch calibration number */ @@ -641,7 +338,8 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, return; } -static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, +static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr, + void __iomem *utmi_base_addr, void __iomem *usb_cfg_addr, void __iomem *utmi_cfg_addr, u32 utmi_phy_port) { @@ -660,7 +358,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, UTMI_CTRL_STATUS0_TEST_SEL_MASK); debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); - addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; + addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG; data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; mask = data; data = polling_with_timeout(addr, data, mask, 100); @@ -679,7 +377,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, ret = 0; } - addr = utmi_base_addr + UTMI_PLL_CTRL_REG; + addr = utmi_pll_addr + UTMI_PLL_CTRL_REG; data = UTMI_PLL_CTRL_PLL_RDY_MASK; mask = data; data = polling_with_timeout(addr, data, mask, 100); @@ -703,7 +401,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, * the init split in 3 parts: * 1. Power down transceiver and PLL * 2. UTMI PHY configure - * 3. Powe up transceiver and PLL + * 3. Power up transceiver and PLL * Note: - Power down/up should be once for both UTMI PHYs * - comphy_dedicated_phys_init call this function if at least there is * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is @@ -730,14 +428,16 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count, } /* UTMI configure */ for (i = 0; i < utmi_phy_count; i++) { - comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, + comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr, + cp110_utmi_data[i].utmi_base_addr, cp110_utmi_data[i].usb_cfg_addr, cp110_utmi_data[i].utmi_cfg_addr, cp110_utmi_data[i].utmi_phy_port); } /* UTMI Power up */ for (i = 0; i < utmi_phy_count; i++) { - if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, + if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr, + cp110_utmi_data[i].utmi_base_addr, cp110_utmi_data[i].usb_cfg_addr, cp110_utmi_data[i].utmi_cfg_addr, cp110_utmi_data[i].utmi_phy_port)) { @@ -770,45 +470,61 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count, void comphy_dedicated_phys_init(void) { struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; - int node; - int i; + int node = -1; + int node_idx; + int parent = -1; debug_enter(); debug("Initialize USB UTMI PHYs\n"); - /* Find the UTMI phy node in device tree and go over them */ - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, - "marvell,mvebu-utmi-2.6.0"); + for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) { + /* Find the UTMI phy node in device tree */ + node = fdt_node_offset_by_compatible(gd->fdt_blob, node, + "marvell,mvebu-utmi-2.6.0"); + if (node <= 0) + break; + + /* check if node is enabled */ + if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) + continue; + + parent = fdt_parent_offset(gd->fdt_blob, node); + if (parent <= 0) + break; + + /* get base address of UTMI PLL */ + cp110_utmi_data[node_idx].utmi_pll_addr = + (void __iomem *)fdtdec_get_addr_size_auto_noparent( + gd->fdt_blob, parent, "reg", 0, NULL, true); + if (!cp110_utmi_data[node_idx].utmi_pll_addr) { + pr_err("UTMI PHY PLL address is invalid\n"); + continue; + } - i = 0; - while (node > 0) { /* get base address of UTMI phy */ - cp110_utmi_data[i].utmi_base_addr = + cp110_utmi_data[node_idx].utmi_base_addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( gd->fdt_blob, node, "reg", 0, NULL, true); - if (cp110_utmi_data[i].utmi_base_addr == NULL) { + if (!cp110_utmi_data[node_idx].utmi_base_addr) { pr_err("UTMI PHY base address is invalid\n"); - i++; continue; } /* get usb config address */ - cp110_utmi_data[i].usb_cfg_addr = + cp110_utmi_data[node_idx].usb_cfg_addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( gd->fdt_blob, node, "reg", 1, NULL, true); - if (cp110_utmi_data[i].usb_cfg_addr == NULL) { + if (!cp110_utmi_data[node_idx].usb_cfg_addr) { pr_err("UTMI PHY base address is invalid\n"); - i++; continue; } /* get UTMI config address */ - cp110_utmi_data[i].utmi_cfg_addr = + cp110_utmi_data[node_idx].utmi_cfg_addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( gd->fdt_blob, node, "reg", 2, NULL, true); - if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { + if (!cp110_utmi_data[node_idx].utmi_cfg_addr) { pr_err("UTMI PHY base address is invalid\n"); - i++; continue; } @@ -816,70 +532,30 @@ void comphy_dedicated_phys_init(void) * get the port number (to check if the utmi connected to * host/device) */ - cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( + cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int( gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); - if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { + if (cp110_utmi_data[node_idx].utmi_phy_port == + UTMI_PHY_INVALID) { pr_err("UTMI PHY port type is invalid\n"); - i++; continue; } - node = fdt_node_offset_by_compatible( - gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); - i++; + /* count valid UTMI unit */ + node_idx++; } - if (i > 0) - comphy_utmi_phy_init(i, cp110_utmi_data); + if (node_idx > 0) + comphy_utmi_phy_init(node_idx, cp110_utmi_data); debug_exit(); } -static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, - struct comphy_map *serdes_map) -{ - void __iomem *comphy_base_addr; - struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; - struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; - u32 lane, comphy_max_count; - - comphy_max_count = ptr_chip_cfg->comphy_lanes_count; - comphy_base_addr = ptr_chip_cfg->comphy_base_addr; - - /* - * Copy the SerDes map configuration for PIPE map and PHY map - * the comphy_mux_init modify the type of the lane if the type - * is not valid because we have 2 selectores run the - * comphy_mux_init twice and after that update the original - * serdes_map - */ - for (lane = 0; lane < comphy_max_count; lane++) { - comphy_map_pipe_data[lane].type = serdes_map[lane].type; - comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; - comphy_map_phy_data[lane].type = serdes_map[lane].type; - comphy_map_phy_data[lane].speed = serdes_map[lane].speed; - } - ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; - comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, - comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); - - ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; - comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, - comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); - /* Fix the type after check the PHY and PIPE configuration */ - for (lane = 0; lane < comphy_max_count; lane++) { - if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && - (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) - serdes_map[lane].type = PHY_TYPE_UNCONNECTED; - } -} - int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map) { struct comphy_map *ptr_comphy_map; void __iomem *comphy_base_addr, *hpipe_base_addr; - u32 comphy_max_count, lane, ret = 0; + u32 comphy_max_count, lane, id, ret = 0; u32 pcie_width = 0; u32 mode; @@ -889,13 +565,10 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, comphy_base_addr = ptr_chip_cfg->comphy_base_addr; hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; - /* Config Comphy mux configuration */ - comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); - /* Check if the first 4 lanes configured as By-4 */ for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; lane++, ptr_comphy_map++) { - if (ptr_comphy_map->type != PHY_TYPE_PEX0) + if (ptr_comphy_map->type != COMPHY_TYPE_PEX0) break; pcie_width++; } @@ -912,14 +585,18 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, pcie_width = 1; } switch (ptr_comphy_map->type) { - case PHY_TYPE_UNCONNECTED: - case PHY_TYPE_IGNORE: + case COMPHY_TYPE_UNCONNECTED: + mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT; + ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF, + ptr_chip_cfg->comphy_base_addr, + lane, mode); + case COMPHY_TYPE_IGNORE: continue; break; - case PHY_TYPE_PEX0: - case PHY_TYPE_PEX1: - case PHY_TYPE_PEX2: - case PHY_TYPE_PEX3: + case COMPHY_TYPE_PEX0: + case COMPHY_TYPE_PEX1: + case COMPHY_TYPE_PEX2: + case COMPHY_TYPE_PEX3: mode = COMPHY_FW_PCIE_FORMAT(pcie_width, ptr_comphy_map->clk_src, COMPHY_PCIE_MODE, @@ -928,71 +605,61 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SATA0: - case PHY_TYPE_SATA1: - case PHY_TYPE_SATA2: - case PHY_TYPE_SATA3: + case COMPHY_TYPE_SATA0: + case COMPHY_TYPE_SATA1: mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, mode); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_HOST1: - case PHY_TYPE_USB3_DEVICE: - ret = comphy_usb3_power_up(lane, hpipe_base_addr, - comphy_base_addr); + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_HOST1: + mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { - debug("Warning: "); - debug("SGMII PHY speed in lane %d is invalid,", - lane); - debug(" set PHY speed to 1.25G\n"); - ptr_comphy_map->speed = PHY_SPEED_1_25G; - } - - /* - * UINIT_ID not relevant for SGMII0 and SGMII1 - will be - * ignored by firmware - */ - mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, - COMPHY_UNIT_ID0, - ptr_comphy_map->speed); + case COMPHY_TYPE_USB3_DEVICE: + mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE); ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SGMII2: - case PHY_TYPE_SGMII3: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII2: + /* Calculate SGMII ID */ + id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0; + + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; } - mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, - COMPHY_UNIT_ID2, + mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id, ptr_comphy_map->speed); ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SFI: - mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, - COMPHY_UNIT_ID0, + case COMPHY_TYPE_SFI0: + case COMPHY_TYPE_SFI1: + /* Calculate SFI id */ + id = ptr_comphy_map->type - COMPHY_TYPE_SFI0; + mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id, ptr_comphy_map->speed); ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, mode); + break; + case COMPHY_TYPE_RXAUI0: + case COMPHY_TYPE_RXAUI1: + mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_RXAUI0: - case PHY_TYPE_RXAUI1: - ret = comphy_rxauii_power_up(lane, hpipe_base_addr, - comphy_base_addr); - break; default: debug("Unknown SerDes type, skip initialize SerDes %d\n", lane); @@ -1001,9 +668,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, if (ret == 0) { /* * If interface wans't initialized, set the lane to - * PHY_TYPE_UNCONNECTED state. + * COMPHY_TYPE_UNCONNECTED state. */ - ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; + ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED; pr_err("PLL is not locked - Failed to initialize lane %d\n", lane); } diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h deleted file mode 100644 index a692035c94..0000000000 --- a/drivers/phy/marvell/comphy_hpipe.h +++ /dev/null @@ -1,660 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Marvell International Ltd. - */ - -#ifndef _COMPHY_HPIPE_H_ -#define _COMPHY_HPIPE_H_ - -/* SerDes IP register */ -#define SD_EXTERNAL_CONFIG0_REG 0 -#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 -#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ - (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ - (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ - (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) -#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 -#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ - (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) -#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 -#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ - (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) -#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 -#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ - (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) -#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 -#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ - (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) - -#define SD_EXTERNAL_CONFIG1_REG 0x4 -#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 -#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ - (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) -#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 -#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ - (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) -#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 -#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ - (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) -#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 -#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ - (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) - -#define SD_EXTERNAL_CONFIG2_REG 0x8 -#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 -#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ - (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) -#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 -#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ - (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) - -#define SD_EXTERNAL_STATUS0_REG 0x18 -#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 -#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ - (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) -#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 -#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ - (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) -#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 -#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ - (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) -#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 -#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ - (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) - -/* HPIPE register */ -#define HPIPE_PWR_PLL_REG 0x4 -#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 -#define HPIPE_PWR_PLL_REF_FREQ_MASK \ - (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) -#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 -#define HPIPE_PWR_PLL_PHY_MODE_MASK \ - (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) - -#define HPIPE_KVCO_CALIB_CTRL_REG 0x8 -#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 -#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ - (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) - -#define HPIPE_CAL_REG1_REG 0xc -#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 -#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ - (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) -#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 -#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ - (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) - -#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 - -#define HPIPE_DFE_REG0 0x01C -#define HPIPE_DFE_RES_FORCE_OFFSET 15 -#define HPIPE_DFE_RES_FORCE_MASK \ - (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) - -#define HPIPE_DFE_F3_F5_REG 0x028 -#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 -#define HPIPE_DFE_F3_F5_DFE_EN_MASK \ - (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) -#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 -#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ - (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) - -#define HPIPE_G1_SET_0_REG 0x034 -#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 -#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ - (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) -#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ - (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) -#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ - (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) -#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ - (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) - -#define HPIPE_G1_SET_1_REG 0x038 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ - (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ - (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 -#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ - (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 -#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ - (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ - (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) - -#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ - (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) - -#define HPIPE_G2_SET_0_REG 0x3c -#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 -#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ - (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) -#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ - (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) -#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 -#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ - (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) -#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ - (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) - -#define HPIPE_G2_SET_1_REG 0x040 -#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 -#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ - (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ - (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) -#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 -#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ - (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) -#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 -#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ - (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) -#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 -#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ - (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) -#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ - (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) - -#define HPIPE_G3_SET_0_REG 0x44 -#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 -#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ - (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) -#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ - (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) -#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 -#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ - (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) -#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ - (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) -#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 -#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ - (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) -#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 -#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ - (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) - -#define HPIPE_G3_SET_1_REG 0x048 -#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 -#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ - (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) -#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 -#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ - (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) -#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 -#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ - (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) -#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 -#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ - (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) -#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 -#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ - (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) -#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ - (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) -#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 -#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ - (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) - -#define HPIPE_LOOPBACK_REG 0x08c -#define HPIPE_LOOPBACK_SEL_OFFSET 1 -#define HPIPE_LOOPBACK_SEL_MASK \ - (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) - -#define HPIPE_SYNC_PATTERN_REG 0x090 -#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10 -#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \ - (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET) -#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11 -#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \ - (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET) - -#define HPIPE_INTERFACE_REG 0x94 -#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 -#define HPIPE_INTERFACE_GEN_MAX_MASK \ - (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) -#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 -#define HPIPE_INTERFACE_DET_BYPASS_MASK \ - (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) -#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 -#define HPIPE_INTERFACE_LINK_TRAIN_MASK \ - (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) - -#define HPIPE_ISOLATE_MODE_REG 0x98 -#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 -#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ - (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) -#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 -#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ - (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) - -#define HPIPE_G1_SET_2_REG 0xf4 -#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 -#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ - (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) -#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 -#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ - (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK) - -#define HPIPE_VTHIMPCAL_CTRL_REG 0x104 - -#define HPIPE_VDD_CAL_CTRL_REG 0x114 -#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 -#define HPIPE_EXT_SELLV_RXSAMPL_MASK \ - (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) - -#define HPIPE_VDD_CAL_0_REG 0x108 -#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 -#define HPIPE_CAL_VDD_CONT_MODE_MASK \ - (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) - -#define HPIPE_PCIE_REG0 0x120 -#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 -#define HPIPE_PCIE_IDLE_SYNC_MASK \ - (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) -#define HPIPE_PCIE_SEL_BITS_OFFSET 13 -#define HPIPE_PCIE_SEL_BITS_MASK \ - (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) - -#define HPIPE_LANE_ALIGN_REG 0x124 -#define HPIPE_LANE_ALIGN_OFF_OFFSET 12 -#define HPIPE_LANE_ALIGN_OFF_MASK \ - (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) - -#define HPIPE_MISC_REG 0x13C -#define HPIPE_MISC_CLK100M_125M_OFFSET 4 -#define HPIPE_MISC_CLK100M_125M_MASK \ - (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) -#define HPIPE_MISC_ICP_FORCE_OFFSET 5 -#define HPIPE_MISC_ICP_FORCE_MASK \ - (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) -#define HPIPE_MISC_TXDCLK_2X_OFFSET 6 -#define HPIPE_MISC_TXDCLK_2X_MASK \ - (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) -#define HPIPE_MISC_CLK500_EN_OFFSET 7 -#define HPIPE_MISC_CLK500_EN_MASK \ - (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) -#define HPIPE_MISC_REFCLK_SEL_OFFSET 10 -#define HPIPE_MISC_REFCLK_SEL_MASK \ - (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) - -#define HPIPE_RX_CONTROL_1_REG 0x140 -#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 -#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ - (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) -#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 -#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ - (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) - -#define HPIPE_PWR_CTR_REG 0x148 -#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 -#define HPIPE_PWR_CTR_RST_DFE_MASK \ - (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) -#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 -#define HPIPE_PWR_CTR_SFT_RST_MASK \ - (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) - -#define HPIPE_SPD_DIV_FORCE_REG 0x154 -#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 -#define HPIPE_TXDIGCK_DIV_FORCE_MASK \ - (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ - (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ - (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ - (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ - (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) - -#define HPIPE_PLLINTP_REG1 0x150 - -#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C -#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 -#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ - (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) -#define HPIPE_SMAPLER_OFFSET 12 -#define HPIPE_SMAPLER_MASK \ - (0x1 << HPIPE_SMAPLER_OFFSET) - -#define HPIPE_TX_REG1_REG 0x174 -#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 -#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ - (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) -#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 -#define HPIPE_TX_REG1_SLC_EN_MASK \ - (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) - -#define HPIPE_PWR_CTR_DTL_REG 0x184 -#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 -#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ - (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) -#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 -#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ - (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ - (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) -#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 -#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ - (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) -#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 -#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ - (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) -#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 -#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ - (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) -#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 -#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ - (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) - -#define HPIPE_PHASE_CONTROL_REG 0x188 -#define HPIPE_OS_PH_OFFSET_OFFSET 0 -#define HPIPE_OS_PH_OFFSET_MASK \ - (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) -#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 -#define HPIPE_OS_PH_OFFSET_FORCE_MASK \ - (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) -#define HPIPE_OS_PH_VALID_OFFSET 8 -#define HPIPE_OS_PH_VALID_MASK \ - (0x1 << HPIPE_OS_PH_VALID_OFFSET) - -#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 -#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 -#define HPIPE_TRAIN_PAT_NUM_MASK \ - (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) - -#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 -#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 -#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ - (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) - -#define HPIPE_DME_REG 0x228 -#define HPIPE_DME_ETHERNET_MODE_OFFSET 7 -#define HPIPE_DME_ETHERNET_MODE_MASK \ - (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) - -#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 -#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 -#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ - (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) - -#define HPIPE_TX_TRAIN_CTRL_REG 0x26C -#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 -#define HPIPE_TX_TRAIN_CTRL_G1_MASK \ - (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) -#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 -#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ - (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) -#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 -#define HPIPE_TX_TRAIN_CTRL_G0_MASK \ - (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) - -#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 -#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_TRX_TRAIN_TIMER_MASK \ - (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) - -#define HPIPE_PCIE_REG1 0x288 -#define HPIPE_PCIE_REG3 0x290 - -#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 -#define HPIPE_RX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_RX_TRAIN_TIMER_MASK \ - (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) -#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 -#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ - (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) -#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 -#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ - (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) -#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 -#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ - (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) -#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 -#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ - (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) - -#define HPIPE_TX_TRAIN_REG 0x31C -#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 -#define HPIPE_TX_TRAIN_CHK_INIT_MASK \ - (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) -#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 -#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ - (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) -#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 -#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ - (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) -#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 -#define HPIPE_TX_TRAIN_PAT_SEL_MASK \ - (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) - -#define HPIPE_CDR_CONTROL_REG 0x418 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ - (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) -#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 -#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ - (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) -#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 -#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ - (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) - -#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 -#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 -#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ - (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) -#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 -#define HPIPE_TX_NUM_OF_PRESET_MASK \ - (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) -#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 -#define HPIPE_TX_SWEEP_PRESET_EN_MASK \ - (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) - -#define HPIPE_G1_SETTINGS_3_REG 0x440 -#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ - (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) -#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ - (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) -#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ - (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) -#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 -#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ - (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) -#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ - (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) -#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ - (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) - -#define HPIPE_G1_SETTINGS_4_REG 0x444 -#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 -#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ - (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) - -#define HPIPE_G2_SETTINGS_3_REG 0x448 - -#define HPIPE_G2_SETTINGS_4_REG 0x44c -#define HPIPE_G2_DFE_RES_OFFSET 8 -#define HPIPE_G2_DFE_RES_MASK \ - (0x3 << HPIPE_G2_DFE_RES_OFFSET) - -#define HPIPE_G3_SETTING_3_REG 0x450 -#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G3_FFE_CAP_SEL_MASK \ - (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) -#define HPIPE_G3_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G3_FFE_RES_SEL_MASK \ - (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) -#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G3_FFE_SETTING_FORCE_MASK \ - (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) -#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ - (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) -#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ - (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) - -#define HPIPE_G3_SETTING_4_REG 0x454 -#define HPIPE_G3_DFE_RES_OFFSET 8 -#define HPIPE_G3_DFE_RES_MASK \ - (0x3 << HPIPE_G3_DFE_RES_OFFSET) - -#define HPIPE_TX_PRESET_INDEX_REG 0x468 -#define HPIPE_TX_PRESET_INDEX_OFFSET 0 -#define HPIPE_TX_PRESET_INDEX_MASK \ - (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) - -#define HPIPE_DFE_CONTROL_REG 0x470 -#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 -#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ - (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) - -#define HPIPE_DFE_CTRL_28_REG 0x49C -#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 -#define HPIPE_DFE_CTRL_28_PIPE4_MASK \ - (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) - -#define HPIPE_G1_SETTING_5_REG 0x538 -#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 -#define HPIPE_G1_SETTING_5_G1_ICP_MASK \ - (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) - -#define HPIPE_G3_SETTING_5_REG 0x548 -#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 -#define HPIPE_G3_SETTING_5_G3_ICP_MASK \ - (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) - -#define HPIPE_LANE_CONFIG0_REG 0x600 -#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 -#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ - (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) - -#define HPIPE_LANE_CONFIG1_REG 0x604 -#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 -#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ - (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) -#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 -#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ - (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) - -#define HPIPE_LANE_STATUS1_REG 0x60C -#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 -#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ - (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) - -#define HPIPE_LANE_CFG4_REG 0x620 -#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 -#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ - (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) -#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 -#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ - (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) -#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 -#define HPIPE_LANE_CFG4_DFE_OVER_MASK \ - (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) -#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 -#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ - (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) - -#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C -#define HPIPE_CFG_PHY_RC_EP_OFFSET 12 -#define HPIPE_CFG_PHY_RC_EP_MASK \ - (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) - -#define HPIPE_LANE_EQ_CFG1_REG 0x6a0 -#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 -#define HPIPE_CFG_UPDATE_POLARITY_MASK \ - (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) - -#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 -#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 -#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ - (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) -#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 -#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ - (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) -#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 -#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ - (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) - -#define HPIPE_RST_CLK_CTRL_REG 0x704 -#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 -#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ - (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) -#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 -#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ - (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) -#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 -#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ - (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) -#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 -#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ - (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) - -#define HPIPE_TST_MODE_CTRL_REG 0x708 -#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 -#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ - (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) - -#define HPIPE_CLK_SRC_LO_REG 0x70c -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ - (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ - (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ - (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) - -#define HPIPE_CLK_SRC_HI_REG 0x710 -#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 -#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ - (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) -#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 -#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ - (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) -#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 -#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ - (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) -#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 -#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ - (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) - -#define HPIPE_GLOBAL_MISC_CTRL 0x718 -#define HPIPE_GLOBAL_PM_CTRL 0x740 -#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 -#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ - (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) - -#endif /* _COMPHY_HPIPE_H_ */ - diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 98327557a8..10981d25ec 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -8,14 +8,13 @@ #include <asm/io.h> #include "comphy_core.h" -#include "comphy_hpipe.h" /* * comphy_mux_check_config() * description: this function passes over the COMPHY lanes and check if the type * is valid for specific lane. If the type is not valid, * the function update the struct and set the type of the lane as - * PHY_TYPE_UNCONNECTED + * COMPHY_TYPE_UNCONNECTED */ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes) @@ -28,7 +27,7 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { /* Don't check ignored COMPHYs */ - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue; mux_opt = mux_data->mux_values; @@ -43,8 +42,8 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, debug("lane number %d, had invalid type %d\n", lane, comphy_map_data->type); debug("set lane %d as type %d\n", lane, - PHY_TYPE_UNCONNECTED); - comphy_map_data->type = PHY_TYPE_UNCONNECTED; + COMPHY_TYPE_UNCONNECTED); + comphy_map_data->type = COMPHY_TYPE_UNCONNECTED; } else { debug("lane number %d, has type %d\n", lane, comphy_map_data->type); @@ -88,7 +87,7 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue; /* diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h index 682a3acc40..8a570bae73 100644 --- a/drivers/phy/marvell/utmi_phy.h +++ b/drivers/phy/marvell/utmi_phy.h @@ -38,6 +38,12 @@ #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \ (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK \ + (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK \ + (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \ (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) @@ -45,15 +51,21 @@ #define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \ (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET) -#define UTMI_TX_CH_CTRL_REG 0xC +#define UTMI_TX_CH_CTRL_REG 0x0 #define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12 #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \ (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \ (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 +#define UTMI_TX_CH_CTRL_AMP_MASK \ + (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) -#define UTMI_RX_CH_CTRL0_REG 0x14 +#define UTMI_RX_CH_CTRL0_REG 0x8 +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK \ + (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 #define UTMI_RX_CH_CTRL0_SQ_DET_MASK \ (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) @@ -61,15 +73,15 @@ #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \ (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET) -#define UTMI_RX_CH_CTRL1_REG 0x18 +#define UTMI_RX_CH_CTRL1_REG 0xc #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \ - (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) + (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \ (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) -#define UTMI_CTRL_STATUS0_REG 0x24 +#define UTMI_CTRL_STATUS0_REG 0x18 #define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22 #define UTMI_CTRL_STATUS0_SUSPENDM_MASK \ (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET) @@ -77,7 +89,7 @@ #define UTMI_CTRL_STATUS0_TEST_SEL_MASK \ (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET) -#define UTMI_CHGDTC_CTRL_REG 0x38 +#define UTMI_CHGDTC_CTRL_REG 0x2c #define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8 #define UTMI_CHGDTC_CTRL_VDAT_MASK \ (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 48bdd0f6f5..ebb7602dde 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -295,7 +295,7 @@ static int single_configure_pins(struct udevice *dev, func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); - if (offset < 0 || offset > pdata->offset) { + if (offset > pdata->offset) { dev_err(dev, " invalid register offset 0x%x\n", offset); continue; @@ -335,6 +335,10 @@ static int single_configure_bits(struct udevice *dev, phys_addr_t reg; u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask; + /* If function mask is null, needn't enable it. */ + if (!pdata->mask) + return 0; + npins_in_reg = pdata->width / priv->bits_per_pin; func = single_allocate_function(dev, count * npins_in_reg); if (IS_ERR(func)) @@ -344,7 +348,7 @@ static int single_configure_bits(struct udevice *dev, func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); - if (offset < 0 || offset > pdata->offset) { + if (offset > pdata->offset) { dev_dbg(dev, " invalid register offset 0x%x\n", offset); continue; @@ -469,6 +473,11 @@ static int single_probe(struct udevice *dev) priv->npins = size / (pdata->width / BITS_PER_BYTE); if (pdata->bits_per_mux) { + if (!pdata->mask) { + dev_err(dev, "function mask needs to be non-zero\n"); + return -EINVAL; + } + priv->bits_per_pin = fls(pdata->mask); priv->npins *= (pdata->width / priv->bits_per_pin); } diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4d2e730271..fac9606823 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev) return ret; } +int regulator_unset(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + if (uc_pdata && uc_pdata->force_off) + return regulator_set_enable(dev, false); + + return -EMEDIUMTYPE; +} + static void regulator_show(struct udevice *dev, int ret) { struct dm_regulator_uclass_plat *uc_pdata; @@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev) uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", 0); + uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off"); node = dev_read_subnode(dev, "regulator-state-mem"); if (ofnode_valid(node)) { @@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose) return ret; } +int regulators_enable_boot_off(bool verbose) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_REGULATOR, &uc); + if (ret) + return ret; + for (uclass_first_device(UCLASS_REGULATOR, &dev); + dev; + uclass_next_device(&dev)) { + ret = regulator_unset(dev); + if (ret == -EMEDIUMTYPE) { + ret = 0; + continue; + } + if (verbose) + regulator_show(dev, ret); + if (ret == -ENOSYS) + ret = 0; + } + + return ret; +} + UCLASS_DRIVER(regulator) = { .id = UCLASS_REGULATOR, .name = "regulator", diff --git a/drivers/ram/octeon/octeon3_lmc.c b/drivers/ram/octeon/octeon3_lmc.c index 327cdc5873..349abc179f 100644 --- a/drivers/ram/octeon/octeon3_lmc.c +++ b/drivers/ram/octeon/octeon3_lmc.c @@ -17,14 +17,8 @@ /* Random number generator stuff */ -#define CVMX_RNM_CTL_STATUS 0x0001180040000000 #define CVMX_OCT_DID_RNG 8ULL -static u64 cvmx_build_io_address(u64 major_did, u64 sub_did) -{ - return ((0x1ull << 48) | (major_did << 43) | (sub_did << 40)); -} - static u64 cvmx_rng_get_random64(void) { return csr_rd(cvmx_build_io_address(CVMX_OCT_DID_RNG, 0)); @@ -285,10 +279,10 @@ static int test_dram_byte64(struct ddr_priv *priv, int lmc, u64 p, int node = 0; // Force full cacheline write-backs to boost traffic - l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); saved_dissblkdty = l2c_ctl.cn78xx.dissblkdty; l2c_ctl.cn78xx.dissblkdty = 1; - l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64); if (octeon_is_cpuid(OCTEON_CN73XX) || octeon_is_cpuid(OCTEON_CNF75XX)) kbitno = 18; @@ -489,9 +483,9 @@ static int test_dram_byte64(struct ddr_priv *priv, int lmc, u64 p, } // Restore original setting that could enable partial cacheline writes - l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); l2c_ctl.cn78xx.dissblkdty = saved_dissblkdty; - l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64); return errors; } @@ -6315,17 +6309,17 @@ static void lmc_final(struct ddr_priv *priv) lmc_rd(priv, CVMX_LMCX_INT(if_num)); for (tad = 0; tad < num_tads; tad++) { - l2c_wr(priv, CVMX_L2C_TADX_INT(tad), - l2c_rd(priv, CVMX_L2C_TADX_INT(tad))); + l2c_wr(priv, CVMX_L2C_TADX_INT_REL(tad), + l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad))); debug("%-45s : (%d) 0x%08llx\n", "CVMX_L2C_TAD_INT", tad, - l2c_rd(priv, CVMX_L2C_TADX_INT(tad))); + l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad))); } for (mci = 0; mci < num_mcis; mci++) { - l2c_wr(priv, CVMX_L2C_MCIX_INT(mci), - l2c_rd(priv, CVMX_L2C_MCIX_INT(mci))); + l2c_wr(priv, CVMX_L2C_MCIX_INT_REL(mci), + l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci))); debug("%-45s : (%d) 0x%08llx\n", "L2C_MCI_INT", mci, - l2c_rd(priv, CVMX_L2C_MCIX_INT(mci))); + l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci))); } debug("%-45s : 0x%08llx\n", "LMC_INT", @@ -9827,7 +9821,7 @@ static void cvmx_dram_address_extract_info(struct ddr_priv *priv, u64 address, address -= ADDRESS_HOLE; /* Determine the LMC controllers */ - l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); /* xbits depends on number of LMCs */ xbits = cvmx_dram_get_num_lmc(priv) >> 1; // 4->2, 2->1, 1->0 diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c index 1f75dc15fa..e7b61d39f5 100644 --- a/drivers/ram/octeon/octeon_ddr.c +++ b/drivers/ram/octeon/octeon_ddr.c @@ -145,7 +145,7 @@ static void cvmx_l2c_set_big_size(struct ddr_priv *priv, u64 mem_size, int mode) big_ctl.u64 = 0; big_ctl.s.maxdram = bits - 9; big_ctl.cn61xx.disable = mode; - l2c_wr(priv, CVMX_L2C_BIG_CTL, big_ctl.u64); + l2c_wr(priv, CVMX_L2C_BIG_CTL_REL, big_ctl.u64); } } @@ -2274,15 +2274,15 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz, printf("Disabling L2 ECC based on disable_l2_ecc environment variable\n"); union cvmx_l2c_ctl l2c_val; - l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); l2c_val.s.disecc = 1; - l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); } else { union cvmx_l2c_ctl l2c_val; - l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); l2c_val.s.disecc = 0; - l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); } /* @@ -2295,17 +2295,17 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz, puts("L2 index aliasing disabled.\n"); - l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); l2c_val.s.disidxalias = 1; - l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); } else { union cvmx_l2c_ctl l2c_val; /* Enable L2C index aliasing */ - l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); l2c_val.s.disidxalias = 0; - l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); } if (OCTEON_IS_OCTEON3()) { @@ -2321,7 +2321,7 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz, u64 rdf_cnt; char *s; - l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL); + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); /* * It is more convenient to compute the ratio using clock @@ -2338,7 +2338,7 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz, debug("%-45s : %d, cpu_hertz:%d, ddr_hertz:%d\n", "EARLY FILL COUNT ", l2c_ctl.cn78xx.rdf_cnt, cpu_hertz, ddr_hertz); - l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64); } /* Check for lower DIMM socket populated */ diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 071c389ca0..ac89eaf098 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -95,7 +95,7 @@ int reset_get_by_index_nodev(ofnode node, int index, int ret; ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0, - index > 0, &args); + index, &args); return reset_get_by_index_tail(ret, node, &args, "resets", index > 0, reset_ctl); diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 7389484490..ce69750c7f 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -9,6 +9,7 @@ #include <bootstage.h> #include <dm.h> #include <env.h> +#include <libata.h> #include <log.h> #include <part.h> #include <pci.h> @@ -594,6 +595,11 @@ static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose) memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor)); memcpy(&bdesc->product, &bd.product, sizeof(bd.product)); memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision)); + if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN)) { + ata_swap_buf_le16((u16 *)&bdesc->vendor, sizeof(bd.vendor) / 2); + ata_swap_buf_le16((u16 *)&bdesc->product, sizeof(bd.product) / 2); + ata_swap_buf_le16((u16 *)&bdesc->revision, sizeof(bd.revision) / 2); + } if (verbose) { printf(" Device %d: ", bdesc->devnum); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index af83e9673a..6d1c4530dd 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -788,6 +788,30 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config OCTEON_SERIAL_BOOTCMD + bool "MIPS Octeon PCI remote bootcmd input" + depends on ARCH_OCTEON + depends on DM_SERIAL + select SYS_IS_IN_ENV + select CONSOLE_MUX + help + This driver supports remote input over the PCIe bus from a host + to U-Boot for entering commands. It is utilized by the host + commands 'oct-remote-load' and 'oct-remote-bootcmd'. + +config OCTEON_SERIAL_PCIE_CONSOLE + bool "MIPS Octeon PCIe remote console" + depends on ARCH_OCTEON + depends on (DM_SERIAL && DM_STDIO) + select SYS_STDIO_DEREGISTER + select SYS_CONSOLE_IS_IN_ENV + select CONSOLE_MUX + help + This driver supports remote console over the PCIe bus when the + Octeon is running in PCIe target mode. The host program + 'oct-remote-console' can be used to connect to this console. + The console number will likely be 0 or 1. + config OMAP_SERIAL bool "Support for OMAP specific UART" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 92bcb30b85..6c0fdca586 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -66,6 +66,8 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o +obj-$(CONFIG_OCTEON_SERIAL_BOOTCMD) += serial_octeon_bootcmd.o +obj-$(CONFIG_OCTEON_SERIAL_PCIE_CONSOLE) += serial_octeon_pcie_console.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o diff --git a/drivers/serial/serial_octeon_bootcmd.c b/drivers/serial/serial_octeon_bootcmd.c new file mode 100644 index 0000000000..4bcff77eb8 --- /dev/null +++ b/drivers/serial/serial_octeon_bootcmd.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marvell International Ltd. + * Copyright (C) 2021 Stefan Roese <sr@denx.de> + */ + +#include <dm.h> +#include <dm/uclass.h> +#include <errno.h> +#include <input.h> +#include <iomux.h> +#include <log.h> +#include <serial.h> +#include <stdio_dev.h> +#include <string.h> +#include <watchdog.h> +#include <linux/delay.h> +#include <asm/addrspace.h> +#include <asm/io.h> +#include <mach/cvmx-regs.h> +#include <mach/cvmx-bootmem.h> + +#define DRIVER_NAME "pci-bootcmd" + +/* + * Important: + * This address cannot be changed as the PCI console tool relies on exactly + * this value! + */ +#define BOOTLOADER_PCI_READ_BUFFER_BASE 0x6c000 +#define BOOTLOADER_PCI_READ_BUFFER_SIZE 256 +#define BOOTLOADER_PCI_WRITE_BUFFER_SIZE 256 + +#define BOOTLOADER_PCI_READ_BUFFER_STR_LEN \ + (BOOTLOADER_PCI_READ_BUFFER_SIZE - 8) +#define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN \ + (BOOTLOADER_PCI_WRITE_BUFFER_SIZE - 8) + +#define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR \ + (BOOTLOADER_PCI_READ_BUFFER_BASE + 0) +#define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR \ + (BOOTLOADER_PCI_READ_BUFFER_BASE + 4) +#define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR \ + (BOOTLOADER_PCI_READ_BUFFER_BASE + 8) + +enum octeon_pci_io_buf_owner { + /* Must be zero, set when memory cleared */ + OCTEON_PCI_IO_BUF_OWNER_INVALID = 0, + OCTEON_PCI_IO_BUF_OWNER_OCTEON = 1, + OCTEON_PCI_IO_BUF_OWNER_HOST = 2, +}; + +/* Structure for bootloader PCI IO buffers */ +struct octeon_pci_io_buf { + u32 owner; + u32 len; + char data[0]; +}; + +struct octeon_bootcmd_priv { + bool started; + int copy_offset; + bool eol; + bool unlocked; + struct octeon_pci_io_buf *buf; +}; + +static int octeon_bootcmd_pending(struct udevice *dev, bool input) +{ + struct octeon_bootcmd_priv *priv = dev_get_priv(dev); + + if (!input) + return 0; + + if (priv->eol) + return 1; + + CVMX_SYNC; + if (priv->buf->owner != OCTEON_PCI_IO_BUF_OWNER_OCTEON) + return 0; + + if (priv->buf->len > priv->copy_offset && + (priv->buf->data[priv->copy_offset] != '\0')) + return 1; + + return 0; +} + +static int octeon_bootcmd_getc(struct udevice *dev) +{ + struct octeon_bootcmd_priv *priv = dev_get_priv(dev); + char c; + + /* There's no EOL for boot commands so we fake it. */ + if (priv->eol) { + priv->eol = false; + return '\n'; + } + + while (!octeon_bootcmd_pending(dev, true)) { + WATCHDOG_RESET(); + /* + * ToDo: + * The original code calls octeon_board_poll() here. We may + * need to implement something similar here. + */ + udelay(100); + } + + c = priv->buf->data[priv->copy_offset]; + priv->buf->data[priv->copy_offset++] = '\0'; + + if (priv->copy_offset >= min_t(int, CONFIG_SYS_CBSIZE - 1, + BOOTLOADER_PCI_READ_BUFFER_STR_LEN - 1) || + (priv->buf->data[priv->copy_offset] == '\0')) { + priv->copy_offset = 0; + priv->buf->len = 0; + priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST; + priv->eol = true; + CVMX_SYNC; + } + + return c; +} + +static const struct dm_serial_ops octeon_bootcmd_ops = { + .getc = octeon_bootcmd_getc, + .pending = octeon_bootcmd_pending, +}; + +static int octeon_bootcmd_probe(struct udevice *dev) +{ + struct octeon_bootcmd_priv *priv = dev_get_priv(dev); + + priv->buf = (void *)CKSEG0ADDR(BOOTLOADER_PCI_READ_BUFFER_BASE); + memset(priv->buf, 0, BOOTLOADER_PCI_READ_BUFFER_SIZE); + priv->eol = false; + + /* + * When the bootcmd console is first started it is started as locked to + * block any calls sending a command until U-Boot is ready to accept + * commands. Just before the main loop starts to accept commands the + * bootcmd console is unlocked. + */ + if (priv->unlocked) + priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST; + else + priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_OCTEON; + + debug("%s called, buffer ptr: 0x%p, owner: %s\n", __func__, + priv->buf, + priv->buf->owner == OCTEON_PCI_IO_BUF_OWNER_HOST ? + "host" : "octeon"); + debug("&priv->copy_offset: 0x%p\n", &priv->copy_offset); + CVMX_SYNC; + + /* + * Perhaps reinvestige this: In the original code, "unlocked" etc + * is set in the octeon_pci_bootcmd_unlock() function called very + * late. + */ + priv->buf->owner = OCTEON_PCI_IO_BUF_OWNER_HOST; + priv->unlocked = true; + priv->started = true; + CVMX_SYNC; + + return 0; +} + +static const struct udevice_id octeon_bootcmd_serial_id[] = { + { .compatible = "marvell,pci-bootcmd", }, + { }, +}; + +U_BOOT_DRIVER(octeon_bootcmd) = { + .name = DRIVER_NAME, + .id = UCLASS_SERIAL, + .ops = &octeon_bootcmd_ops, + .of_match = of_match_ptr(octeon_bootcmd_serial_id), + .probe = octeon_bootcmd_probe, + .priv_auto = sizeof(struct octeon_bootcmd_priv), +}; diff --git a/drivers/serial/serial_octeon_pcie_console.c b/drivers/serial/serial_octeon_pcie_console.c new file mode 100644 index 0000000000..c76e787d03 --- /dev/null +++ b/drivers/serial/serial_octeon_pcie_console.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marvell International Ltd. + * Copyright (C) 2021 Stefan Roese <sr@denx.de> + */ + +#include <dm.h> +#include <dm/uclass.h> +#include <errno.h> +#include <input.h> +#include <iomux.h> +#include <log.h> +#include <serial.h> +#include <stdio_dev.h> +#include <string.h> +#include <watchdog.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <mach/cvmx-regs.h> +#include <mach/cvmx-bootmem.h> + +#define DRIVER_NAME "pci-console" +#define OCTEONTX_PCIE_CONSOLE_NAME_LEN 16 + +/* Current versions */ +#define OCTEON_PCIE_CONSOLE_MAJOR_VERSION 1 +#define OCTEON_PCIE_CONSOLE_MINOR_VERSION 0 + +#define OCTEON_PCIE_CONSOLE_BLOCK_NAME "__pci_console" + +/* + * Structure that defines a single console. + * Note: when read_index == write_index, the buffer is empty. + * The actual usable size of each console is console_buf_size -1; + */ +struct octeon_pcie_console { + u64 input_base_addr; + u32 input_read_index; + u32 input_write_index; + u64 output_base_addr; + u32 output_read_index; + u32 output_write_index; + u32 lock; + u32 buf_size; +}; + +/* + * This is the main container structure that contains all the information + * about all PCI consoles. The address of this structure is passed to various + * routines that operation on PCI consoles. + */ +struct octeon_pcie_console_desc { + u32 major_version; + u32 minor_version; + u32 lock; + u32 flags; + u32 num_consoles; + u32 pad; + /* must be 64 bit aligned here... */ + /* Array of addresses of octeon_pcie_console_t structures */ + u64 console_addr_array[0]; + /* Implicit storage for console_addr_array */ +}; + +struct octeon_pcie_console_priv { + struct octeon_pcie_console *console; + int console_num; + bool console_active; +}; + +/* Flag definitions for read/write functions */ +enum { + /* + * If set, read/write functions won't block waiting for space or data. + * For reads, 0 bytes may be read, and for writes not all of the + * supplied data may be written. + */ + OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0, +}; + +static int buffer_free_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx) +{ + if (rd_idx >= buffer_size || wr_idx >= buffer_size) + return -1; + + return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size; +} + +static int buffer_avail_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx) +{ + if (rd_idx >= buffer_size || wr_idx >= buffer_size) + return -1; + + return buffer_size - 1 - buffer_free_bytes(buffer_size, wr_idx, rd_idx); +} + +static int buffer_read_avail(struct udevice *dev, unsigned int console_num) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console *cons_ptr = priv->console; + int avail; + + avail = buffer_avail_bytes(cons_ptr->buf_size, + cons_ptr->input_write_index, + cons_ptr->input_read_index); + if (avail >= 0) + return avail; + + return 0; +} + +static int octeon_pcie_console_read(struct udevice *dev, + unsigned int console_num, char *buffer, + int buffer_size, u32 flags) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console *cons_ptr = priv->console; + int avail; + char *buf_ptr; + int bytes_read; + int read_size; + + buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->input_base_addr); + + avail = buffer_avail_bytes(cons_ptr->buf_size, + cons_ptr->input_write_index, + cons_ptr->input_read_index); + if (avail < 0) + return avail; + + if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) { + /* Wait for some data to be available */ + while (0 == (avail = buffer_avail_bytes(cons_ptr->buf_size, + cons_ptr->input_write_index, + cons_ptr->input_read_index))) { + mdelay(10); + WATCHDOG_RESET(); + } + } + + bytes_read = 0; + + /* Don't overflow the buffer passed to us */ + read_size = min_t(int, avail, buffer_size); + + /* Limit ourselves to what we can input in a contiguous block */ + if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size) + read_size = cons_ptr->buf_size - cons_ptr->input_read_index; + + memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size); + cons_ptr->input_read_index = + (cons_ptr->input_read_index + read_size) % cons_ptr->buf_size; + bytes_read += read_size; + + /* Mark the PCIe console to be active from now on */ + if (bytes_read) + priv->console_active = true; + + return bytes_read; +} + +static int octeon_pcie_console_write(struct udevice *dev, + unsigned int console_num, + const char *buffer, + int bytes_to_write, u32 flags) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console *cons_ptr = priv->console; + int avail; + char *buf_ptr; + int bytes_written; + + buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->output_base_addr); + bytes_written = 0; + while (bytes_to_write > 0) { + avail = buffer_free_bytes(cons_ptr->buf_size, + cons_ptr->output_write_index, + cons_ptr->output_read_index); + + if (avail > 0) { + int write_size = min_t(int, avail, bytes_to_write); + + /* + * Limit ourselves to what we can output in a contiguous + * block + */ + if (cons_ptr->output_write_index + write_size >= + cons_ptr->buf_size) { + write_size = cons_ptr->buf_size - + cons_ptr->output_write_index; + } + + memcpy(buf_ptr + cons_ptr->output_write_index, + buffer + bytes_written, write_size); + /* + * Make sure data is visible before changing write + * index + */ + CVMX_SYNCW; + cons_ptr->output_write_index = + (cons_ptr->output_write_index + write_size) % + cons_ptr->buf_size; + bytes_to_write -= write_size; + bytes_written += write_size; + } else if (avail == 0) { + /* + * Check to see if we should wait for room, or return + * after a partial write + */ + if (flags & OCT_PCI_CON_FLAG_NONBLOCK) + goto done; + + WATCHDOG_RESET(); + mdelay(10); /* Delay if we are spinning */ + } else { + bytes_written = -1; + goto done; + } + } + +done: + return bytes_written; +} + +static struct octeon_pcie_console_desc *octeon_pcie_console_init(int num_consoles, + int buffer_size) +{ + struct octeon_pcie_console_desc *cons_desc_ptr; + struct octeon_pcie_console *cons_ptr; + s64 addr; + u64 avail_addr; + int alloc_size; + int i; + + /* Compute size required for pci console structure */ + alloc_size = num_consoles * + (buffer_size * 2 + sizeof(struct octeon_pcie_console) + + sizeof(u64)) + sizeof(struct octeon_pcie_console_desc); + + /* + * Allocate memory for the consoles. This must be in the range + * addresssible by the bootloader. + * Try to do so in a manner which minimizes fragmentation. We try to + * put it at the top of DDR0 or bottom of DDR2 first, and only do + * generic allocation if those fail + */ + addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, + OCTEON_DDR0_SIZE - alloc_size - 128, + OCTEON_DDR0_SIZE, 128, + OCTEON_PCIE_CONSOLE_BLOCK_NAME, + CVMX_BOOTMEM_FLAG_END_ALLOC); + if (addr < 0) { + addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, + 0x1fffffff, 128, + OCTEON_PCIE_CONSOLE_BLOCK_NAME, + CVMX_BOOTMEM_FLAG_END_ALLOC); + } + if (addr < 0) + return 0; + + cons_desc_ptr = cvmx_phys_to_ptr(addr); + + /* Clear entire alloc'ed memory */ + memset(cons_desc_ptr, 0, alloc_size); + + /* Initialize as locked until we are done */ + cons_desc_ptr->lock = 1; + CVMX_SYNCW; + cons_desc_ptr->num_consoles = num_consoles; + cons_desc_ptr->flags = 0; + cons_desc_ptr->major_version = OCTEON_PCIE_CONSOLE_MAJOR_VERSION; + cons_desc_ptr->minor_version = OCTEON_PCIE_CONSOLE_MINOR_VERSION; + + avail_addr = addr + sizeof(struct octeon_pcie_console_desc) + + num_consoles * sizeof(u64); + + for (i = 0; i < num_consoles; i++) { + cons_desc_ptr->console_addr_array[i] = avail_addr; + cons_ptr = (void *)cons_desc_ptr->console_addr_array[i]; + avail_addr += sizeof(struct octeon_pcie_console); + cons_ptr->input_base_addr = avail_addr; + avail_addr += buffer_size; + cons_ptr->output_base_addr = avail_addr; + avail_addr += buffer_size; + cons_ptr->buf_size = buffer_size; + } + CVMX_SYNCW; + cons_desc_ptr->lock = 0; + + return cvmx_phys_to_ptr(addr); +} + +static int octeon_pcie_console_getc(struct udevice *dev) +{ + char c; + + octeon_pcie_console_read(dev, 0, &c, 1, 0); + return c; +} + +static int octeon_pcie_console_putc(struct udevice *dev, const char c) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + + if (priv->console_active) + octeon_pcie_console_write(dev, 0, (char *)&c, 1, 0); + + return 0; +} + +static int octeon_pcie_console_pending(struct udevice *dev, bool input) +{ + if (input) { + udelay(100); + return buffer_read_avail(dev, 0) > 0; + } + + return 0; +} + +static const struct dm_serial_ops octeon_pcie_console_ops = { + .getc = octeon_pcie_console_getc, + .putc = octeon_pcie_console_putc, + .pending = octeon_pcie_console_pending, +}; + +static int octeon_pcie_console_probe(struct udevice *dev) +{ + struct octeon_pcie_console_priv *priv = dev_get_priv(dev); + struct octeon_pcie_console_desc *cons_desc; + int console_count; + int console_size; + int console_num; + + /* + * Currently only 1 console is supported. Perhaps we need to add + * a console nexus if more than one needs to be supported. + */ + console_count = 1; + console_size = 1024; + console_num = 0; + + cons_desc = octeon_pcie_console_init(console_count, console_size); + priv->console = + cvmx_phys_to_ptr(cons_desc->console_addr_array[console_num]); + + debug("PCI console init succeeded, %d consoles, %d bytes each\n", + console_count, console_size); + + return 0; +} + +static const struct udevice_id octeon_pcie_console_serial_id[] = { + { .compatible = "marvell,pci-console", }, + { }, +}; + +U_BOOT_DRIVER(octeon_pcie_console) = { + .name = DRIVER_NAME, + .id = UCLASS_SERIAL, + .ops = &octeon_pcie_console_ops, + .of_match = of_match_ptr(octeon_pcie_console_serial_id), + .probe = octeon_pcie_console_probe, + .priv_auto = sizeof(struct octeon_pcie_console_priv), +}; diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index f4f6e90387..952293195f 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -20,6 +20,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SYS_WATCHDOG_FREQ +#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) +#endif + /** * struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver * @decrementer_count: Value to which the decrementer register should be re-set @@ -171,7 +175,7 @@ void timer_interrupt(struct pt_regs *regs) priv->timestamp++; #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) - if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) + if (CONFIG_SYS_WATCHDOG_FREQ && (priv->timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) WATCHDOG_RESET(); #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 8933f60843..ba75c27d04 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -346,6 +346,28 @@ static int ehci_disable_async(struct ehci_ctrl *ctrl) return ret; } +static int ehci_iaa_cycle(struct ehci_ctrl *ctrl) +{ + u32 cmd, status; + int ret; + + /* Enable Interrupt on Async Advance Doorbell. */ + cmd = ehci_readl(&ctrl->hcor->or_usbcmd); + cmd |= CMD_IAAD; + ehci_writel(&ctrl->hcor->or_usbcmd, cmd); + + ret = handshake(&ctrl->hcor->or_usbsts, STS_IAA, STS_IAA, + 10 * 1000); /* 10ms timeout */ + if (ret < 0) + printf("EHCI fail timeout STS_IAA set\n"); + + status = ehci_readl(&ctrl->hcor->or_usbsts); + if (status & STS_IAA) + ehci_writel(&ctrl->hcor->or_usbsts, STS_IAA); + + return ret; +} + static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) @@ -631,6 +653,11 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, flush_dcache_range((unsigned long)&ctrl->qh_list, ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); + /* Set IAAD, poll IAA */ + ret = ehci_iaa_cycle(ctrl); + if (ret) + goto fail; + /* * Invalidate the memory area occupied by buffer * Don't try to fix the buffer alignment, if it isn't properly diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 7642a31b65..06be9deaaa 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -265,6 +265,8 @@ int usb_phy_mode(int port) } #endif +#if !defined(CONFIG_PHY) +/* Should be done in the MXS PHY driver */ static void usb_oc_config(struct usbnc_regs *usbnc, int index) { void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); @@ -285,6 +287,7 @@ static void usb_oc_config(struct usbnc_regs *usbnc, int index) clrbits_le32(ctrl, UCTRL_PWR_POL); #endif } +#endif #if !CONFIG_IS_ENABLED(DM_USB) /** @@ -432,10 +435,12 @@ struct ehci_mx6_priv_data { struct clk clk; struct phy phy; enum usb_init_type init_type; +#if !defined(CONFIG_PHY) int portnr; void __iomem *phy_addr; void __iomem *misc_addr; void __iomem *anatop_addr; +#endif }; static int mx6_init_after_reset(struct ehci_ctrl *dev) @@ -448,14 +453,14 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) usb_power_config_mx6(priv->anatop_addr, priv->portnr); usb_power_config_mx7(priv->misc_addr); usb_power_config_mx7ulp(priv->phy_addr); -#endif usb_oc_config(priv->misc_addr, priv->portnr); -#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) usb_internal_phy_clock_gate(priv->phy_addr, 1); usb_phy_enable(ehci, priv->phy_addr); #endif +#endif #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { @@ -558,6 +563,7 @@ static int ehci_usb_of_to_plat(struct udevice *dev) static int mx6_parse_dt_addrs(struct udevice *dev) { +#if !defined(CONFIG_PHY) struct ehci_mx6_priv_data *priv = dev_get_priv(dev); int phy_off, misc_off; const void *blob = gd->fdt_blob; @@ -594,7 +600,7 @@ static int mx6_parse_dt_addrs(struct udevice *dev) priv->misc_addr = addr; -#if !defined(CONFIG_PHY) && defined(CONFIG_MX6) +#if defined(CONFIG_MX6) int anatop_off; /* Resolve ANATOP offset through USB PHY node */ @@ -608,6 +614,7 @@ static int mx6_parse_dt_addrs(struct udevice *dev) priv->anatop_addr = addr; #endif +#endif return 0; } @@ -661,14 +668,14 @@ static int ehci_usb_probe(struct udevice *dev) usb_power_config_mx6(priv->anatop_addr, priv->portnr); usb_power_config_mx7(priv->misc_addr); usb_power_config_mx7ulp(priv->phy_addr); -#endif usb_oc_config(priv->misc_addr, priv->portnr); -#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) usb_internal_phy_clock_gate(priv->phy_addr, 1); usb_phy_enable(ehci, priv->phy_addr); #endif +#endif #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 8e0755423a..e9e6f2a551 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -44,6 +44,7 @@ struct ehci_hcor { #define STS_ASS (1 << 15) #define STS_PSS (1 << 14) #define STS_HALT (1 << 12) +#define STS_IAA (1 << 5) uint32_t or_usbintr; #define INTR_UE (1 << 0) /* USB interrupt enable */ #define INTR_UEE (1 << 1) /* USB error interrupt enable */ diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index a3e21aa5f1..e02d359cd2 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -19,8 +19,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/display2.h> -#include <dm/device-internal.h> -#include <dm/uclass-internal.h> #include <linux/bitops.h> #include "simplefb_common.h" @@ -198,13 +196,6 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, disp_uc_plat->source_id = mux; - ret = device_probe(disp); - if (ret) { - debug("%s: device '%s' display won't probe (ret=%d)\n", - __func__, dev->name, ret); - return ret; - } - ret = display_read_timing(disp, &timing); if (ret) { debug("%s: Failed to read timings\n", __func__); @@ -245,8 +236,8 @@ static int sunxi_de2_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) return 0; - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_lcd", &disp); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_lcd), &disp); if (!ret) { int mux; @@ -262,8 +253,8 @@ static int sunxi_de2_probe(struct udevice *dev) debug("%s: lcd display not found (ret=%d)\n", __func__, ret); - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_dw_hdmi", &disp); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_dw_hdmi), &disp); if (!ret) { int mux; if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) @@ -281,20 +272,7 @@ static int sunxi_de2_probe(struct udevice *dev) debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_tve", &disp); - if (ret) { - debug("%s: tv not found (ret=%d)\n", __func__, ret); - return ret; - } - - ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true); - if (ret) - return ret; - - video_set_flush_dcache(dev, 1); - - return 0; + return -ENODEV; } static int sunxi_de2_bind(struct udevice *dev) @@ -345,8 +323,8 @@ int sunxi_simplefb_setup(void *blob) mux = 1; /* Skip simplefb setting if DE2 / HDMI is not present */ - ret = uclass_find_device_by_name(UCLASS_VIDEO, - "sunxi_de2", &de2); + ret = uclass_get_device_by_driver(UCLASS_VIDEO, + DM_DRIVER_GET(sunxi_de2), &de2); if (ret) { debug("DE2 not present\n"); return 0; @@ -355,8 +333,8 @@ int sunxi_simplefb_setup(void *blob) return 0; } - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_dw_hdmi", &hdmi); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_dw_hdmi), &hdmi); if (ret) { debug("HDMI not present\n"); } else if (device_active(hdmi)) { @@ -368,8 +346,8 @@ int sunxi_simplefb_setup(void *blob) debug("HDMI present but not probed\n"); } - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_lcd", &lcd); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_lcd), &lcd); if (ret) debug("LCD not present\n"); else if (device_active(lcd)) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0b8cefc311..19ed80b48a 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -20,7 +20,6 @@ struct sunxi_dw_hdmi_priv { struct dw_hdmi hdmi; - int mux; }; struct sunxi_hdmi_phy { @@ -114,28 +113,6 @@ static void sunxi_dw_hdmi_phy_init(void) writel(0x42494E47, &phy->unscramble); } -static int sunxi_dw_hdmi_get_plug_in_status(void) -{ - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); - - return !!(readl(&phy->status) & (1 << 19)); -} - -static int sunxi_dw_hdmi_wait_for_hpd(void) -{ - ulong start; - - start = get_timer(0); - do { - if (sunxi_dw_hdmi_get_plug_in_status()) - return 0; - udelay(100); - } while (get_timer(start) < 300); - - return -1; -} - static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) { struct sunxi_hdmi_phy * const phy = @@ -305,11 +282,18 @@ static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); } +static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev, + const struct display_timing *timing) +{ + return timing->pixelclock.typ <= 297000000; +} + static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { struct sunxi_hdmi_phy * const phy = (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); + struct display_plat *uc_plat = dev_get_uclass_plat(dev); struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); int ret; @@ -317,7 +301,7 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, if (ret) return ret; - sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp); + sunxi_dw_hdmi_lcdc_init(uc_plat->source_id, edid, panel_bpp); if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) setbits_le32(&phy->pol, 0x200); @@ -340,7 +324,6 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, static int sunxi_dw_hdmi_probe(struct udevice *dev) { - struct display_plat *uc_plat = dev_get_uclass_plat(dev); struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; @@ -364,21 +347,17 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) sunxi_dw_hdmi_phy_init(); - ret = sunxi_dw_hdmi_wait_for_hpd(); - if (ret < 0) { - debug("hdmi can not get hpd signal\n"); - return -1; - } - priv->hdmi.ioaddr = SUNXI_HDMI_BASE; priv->hdmi.i2c_clk_high = 0xd8; priv->hdmi.i2c_clk_low = 0xfe; priv->hdmi.reg_io_width = 1; priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; - priv->mux = uc_plat->source_id; - uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", - &priv->hdmi.ddc_bus); + ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); + if (ret < 0) { + debug("hdmi can not get hpd signal\n"); + return -1; + } dw_hdmi_init(&priv->hdmi); @@ -388,6 +367,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) static const struct dm_display_ops sunxi_dw_hdmi_ops = { .read_edid = sunxi_dw_hdmi_read_edid, .enable = sunxi_dw_hdmi_enable, + .mode_valid = sunxi_dw_hdmi_mode_valid, }; U_BOOT_DRIVER(sunxi_dw_hdmi) = { diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 0603ffbd36..2687135296 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -148,7 +148,7 @@ void watchdog_reset(void) /* Do not reset the watchdog too often */ now = get_timer(0); - if (time_after(now, next_reset)) { + if (time_after_eq(now, next_reset)) { next_reset = now + reset_period; wdt_reset(gd->watchdog_dev); } |