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-rw-r--r--drivers/pci/pci_auto.c8
-rw-r--r--drivers/pci/pcie_fsl.c16
-rw-r--r--drivers/pci/pcie_fsl.h12
-rw-r--r--drivers/pci/pcie_layerscape.h16
-rw-r--r--drivers/pci/pcie_layerscape_ep.c6
-rw-r--r--drivers/pci/pcie_layerscape_gen4.c6
-rw-r--r--drivers/pci/pcie_layerscape_gen4.h8
7 files changed, 36 insertions, 36 deletions
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index c7968926a1..14fd3bbf67 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -16,9 +16,9 @@
#include <time.h>
#include "pci_internal.h"
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+/* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CFG_SYS_PCI_CACHE_LINE_SIZE
+#define CFG_SYS_PCI_CACHE_LINE_SIZE 8
#endif
static void dm_pciauto_setup_device(struct udevice *dev,
@@ -178,7 +178,7 @@ static void dm_pciauto_setup_device(struct udevice *dev,
dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
- CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+ CFG_SYS_PCI_CACHE_LINE_SIZE);
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
}
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index a8f8c31bef..4600652f2b 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -343,8 +343,8 @@ static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
{
- phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
- pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
+ phys_addr_t phys_start = CFG_SYS_PCI_MEMORY_PHYS;
+ pci_addr_t bus_start = CFG_SYS_PCI_MEMORY_BUS;
u64 sz = min((u64)gd->ram_size, (1ull << 32));
pci_size_t pci_sz;
int idx;
@@ -367,8 +367,8 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
sz = 2ull << __ilog2_u64(sz);
fsl_pcie_setup_inbound_win(pcie, idx--, true,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_BUS, sz);
+ CFG_SYS_PCI_MEMORY_PHYS,
+ CFG_SYS_PCI_MEMORY_BUS, sz);
#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
/*
* On 64-bit capable systems, set up a mapping for all of DRAM
@@ -380,12 +380,12 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
- (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
- (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
+ (u64)CFG_SYS_PCI64_MEMORY_BUS,
+ (u64)CFG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
fsl_pcie_setup_inbound_win(pcie, idx--, true,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
+ CFG_SYS_PCI_MEMORY_PHYS,
+ CFG_SYS_PCI64_MEMORY_BUS, pci_sz);
#endif
return 0;
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index 70c5f4e4cf..ba84a232b8 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -28,16 +28,16 @@
#define DBI_RO_WR_EN 0x8bc
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS
-#define CONFIG_SYS_PCI_MEMORY_BUS 0
+#ifndef CFG_SYS_PCI_MEMORY_BUS
+#define CFG_SYS_PCI_MEMORY_BUS 0
#endif
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0
+#ifndef CFG_SYS_PCI_MEMORY_PHYS
+#define CFG_SYS_PCI_MEMORY_PHYS 0
#endif
-#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
-#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS)
+#define CFG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
#endif
#define PEX_CSR0_LTSSM_MASK 0xFC
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 8cdf516d9f..a52774179e 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -13,20 +13,20 @@
#include <asm/arch-fsl-layerscape/svr.h>
#include <asm/arch-ls102xa/svr.h>
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS
-#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#ifndef CFG_SYS_PCI_MEMORY_BUS
+#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
#endif
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
-#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
+#ifndef CFG_SYS_PCI_MEMORY_PHYS
+#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
#endif
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
+#ifndef CFG_SYS_PCI_MEMORY_SIZE
+#define CFG_SYS_PCI_MEMORY_SIZE SZ_4G
#endif
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
-#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
+#ifndef CFG_SYS_PCI_EP_MEMORY_BASE
+#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
#endif
#define PCIE_PHYS_SIZE 0x200000000
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index f2813aeef6..ff26a5cd9b 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -72,7 +72,7 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
u32 vf_flag = 0;
u64 phys = 0;
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+ phys = CFG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
phys = ALIGN(phys, PCIE_BAR0_SIZE);
/* ATU 0 : INBOUND : map BAR0 */
@@ -117,8 +117,8 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
/* ATU: OUTBOUND : map MEM */
ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
(u64)pcie_ep->addr_res.start +
- pf * CONFIG_SYS_PCI_MEMORY_SIZE,
- 0, CONFIG_SYS_PCI_MEMORY_SIZE);
+ pf * CFG_SYS_PCI_MEMORY_SIZE,
+ 0, CFG_SYS_PCI_MEMORY_SIZE);
}
/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 6ecdd6af40..021c975869 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -333,7 +333,7 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
return;
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
+ phys = CFG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
for (bar = 0; bar < PF_BAR_NUM; bar++) {
ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
phys += PCIE_BAR_SIZE;
@@ -342,8 +342,8 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
/* OUTBOUND: map MEM */
ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
pcie->cfg_res.start +
- CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
- CONFIG_SYS_PCI_MEMORY_SIZE);
+ CFG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
+ CFG_SYS_PCI_MEMORY_SIZE);
val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
val &= ~FUNC_NUM_PCIE_MASK;
diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h
index 483eb538b5..805c23a7da 100644
--- a/drivers/pci/pcie_layerscape_gen4.h
+++ b/drivers/pci/pcie_layerscape_gen4.h
@@ -11,12 +11,12 @@
#include <pci.h>
#include <linux/bitops.h>
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL)
+#ifndef CFG_SYS_PCI_MEMORY_SIZE
+#define CFG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL)
#endif
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
-#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
+#ifndef CFG_SYS_PCI_EP_MEMORY_BASE
+#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
#endif
#define PCIE_PF_NUM 2
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 14:30:15 +0000