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-rw-r--r--drivers/ata/sata_ceva.c2
-rw-r--r--drivers/clk/clk_versal.c2
-rw-r--r--drivers/clk/clk_zynqmp.c8
-rw-r--r--drivers/fpga/fpga.c20
-rw-r--r--drivers/fpga/versalpl.c2
-rw-r--r--drivers/fpga/zynqmppl.c4
-rw-r--r--drivers/mmc/zynq_sdhci.c7
-rw-r--r--drivers/mtd/Kconfig2
-rw-r--r--drivers/mtd/nand/raw/zynq_nand.c4
-rw-r--r--drivers/net/xilinx_axi_emac.c2
-rw-r--r--drivers/net/xilinx_axi_mrmac.c2
-rw-r--r--drivers/net/xilinx_axi_mrmac.h2
-rw-r--r--drivers/net/zynq_gem.c57
-rw-r--r--drivers/pinctrl/pinctrl-zynqmp.c2
-rw-r--r--drivers/soc/soc_xilinx_zynqmp.c2
-rw-r--r--drivers/spi/cadence_ospi_versal.c3
-rw-r--r--drivers/spi/cadence_qspi.c13
-rw-r--r--drivers/spi/xilinx_spi.c4
-rw-r--r--drivers/spi/zynq_qspi.c4
-rw-r--r--drivers/watchdog/xilinx_tb_wdt.c2
-rw-r--r--drivers/watchdog/xilinx_wwdt.c5
21 files changed, 109 insertions, 40 deletions
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 43bcc59cd2..47366438fd 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015 - 2016 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*/
#include <common.h>
#include <dm.h>
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index faebbab1c6..b3b3333123 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#include <common.h>
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index be0ee50e0e..1cfe0e25b1 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -12,6 +12,7 @@
#include <linux/bitops.h>
#include <clk-uclass.h>
#include <clk.h>
+#include <zynqmp_firmware.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <linux/err.h>
@@ -269,17 +270,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
case usb3_dual_ref:
return CRL_APB_USB3_DUAL_REF_CTRL;
case gem_tsu_ref:
+ case gem_tsu:
return CRL_APB_GEM_TSU_REF_CTRL;
case gem0_tx:
+ case gem0_rx:
case gem0_ref:
return CRL_APB_GEM0_REF_CTRL;
case gem1_tx:
+ case gem1_rx:
case gem1_ref:
return CRL_APB_GEM1_REF_CTRL;
case gem2_tx:
+ case gem2_rx:
case gem2_ref:
return CRL_APB_GEM2_REF_CTRL;
case gem3_tx:
+ case gem3_rx:
case gem3_ref:
return CRL_APB_GEM3_REF_CTRL;
case usb0_bus_ref:
@@ -718,6 +724,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
switch (id) {
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
+ case gem0_rx ... gem3_rx:
+ case gem_tsu:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 7f6b6bc73a..81e6d8ffc0 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size,
}
#endif
+static int fpga_load_event_notify(const void *buf, size_t bsize, int result)
+{
+ if (CONFIG_IS_ENABLED(EVENT)) {
+ struct event_fpga_load load = {
+ .buf = buf,
+ .bsize = bsize,
+ .result = result
+ };
+
+ return event_notify(EVT_FPGA_LOAD, &load, sizeof(load));
+ }
+
+ return 0;
+}
+
/*
* Generic multiplexing code
*/
@@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
int flags)
{
int ret_val = FPGA_FAIL; /* assume failure */
+ int ret_notify;
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
(char *)__func__);
@@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
}
}
+ ret_notify = fpga_load_event_notify(buf, bsize, ret_val);
+ if (ret_notify)
+ return ret_notify;
+
return ret_val;
}
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index d3876a8f54..be58db5427 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2019, Xilinx, Inc,
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#include <common.h>
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 7b5128fe27..b1f201fb18 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2015 - 2016, Xilinx, Inc,
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/
#include <console.h>
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index e779251ce3..935540d171 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
mdelay(1);
- arasan_zynqmp_dll_reset(host, priv->node_id);
+ if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a"))
+ arasan_zynqmp_dll_reset(host, priv->node_id);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
@@ -468,7 +469,9 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
}
udelay(1);
- arasan_zynqmp_dll_reset(host, priv->node_id);
+
+ if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a"))
+ arasan_zynqmp_dll_reset(host, priv->node_id);
/* Enable only interrupts served by the SD controller */
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fa88dae5f..c56840c849 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -128,7 +128,7 @@ config FLASH_SPANSION_S29WS_N
config FLASH_CFI_MTD
bool "Enable CFI MTD driver"
- depends on FLASH_CFI_DRIVER
+ depends on FLASH_CFI_DRIVER && MTD
help
This option enables the building of the cfi_mtd driver
in the drivers directory. The driver exports CFI flash
diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index 9e3ee7412d..545fdd7b69 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -285,7 +285,7 @@ static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option)
{
struct nand_chip *nand_chip = mtd_to_nand(mtd);
struct nand_drv *smc = nand_get_controller_data(nand_chip);
- u32 status;
+ int status;
/* disable interrupts */
writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr);
@@ -332,7 +332,7 @@ static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
struct nand_drv *smc = nand_get_controller_data(nand_chip);
u32 ecc_value = 0;
u8 ecc_reg, ecc_byte;
- u32 ecc_status;
+ int ecc_status;
/* Wait till the ECC operation is complete */
ecc_status = zynq_nand_waitfor_ecc_completion(mtd);
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 3e9919993d..39cb3cc260 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -748,7 +748,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
/* Wait for an incoming packet */
if (!isrxready(priv))
- return -1;
+ return -EAGAIN;
debug("axiemac: RX data ready\n");
diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c
index 6d15386c66..410fb25dde 100644
--- a/drivers/net/xilinx_axi_mrmac.c
+++ b/drivers/net/xilinx_axi_mrmac.c
@@ -3,7 +3,7 @@
* Xilinx Multirate Ethernet MAC(MRMAC) driver
*
* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* Copyright (C) 2021 Xilinx, Inc. All rights reserved.
*/
diff --git a/drivers/net/xilinx_axi_mrmac.h b/drivers/net/xilinx_axi_mrmac.h
index 4f875857cf..e2c2105450 100644
--- a/drivers/net/xilinx_axi_mrmac.h
+++ b/drivers/net/xilinx_axi_mrmac.h
@@ -3,7 +3,7 @@
* Xilinx Multirate Ethernet MAC(MRMAC) driver
*
* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* Copyright (C) 2021 Xilinx, Inc. All rights reserved.
*/
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 211b2c6e55..f3cdfb0275 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -30,6 +30,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <dm/device_compat.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
@@ -67,11 +68,6 @@
#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
-#ifdef CONFIG_ARM64
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
-#else
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
-#endif
#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
@@ -81,8 +77,7 @@
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
ZYNQ_GEM_NWCFG_FDEN | \
- ZYNQ_GEM_NWCFG_FSREM | \
- ZYNQ_GEM_NWCFG_MDCCLKDIV)
+ ZYNQ_GEM_NWCFG_FSREM)
#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
@@ -141,6 +136,18 @@
#define RXCLK_EN BIT(0)
+/* GEM specific constants for CLK. */
+#define GEM_CLK_DIV8 0
+#define GEM_CLK_DIV16 1
+#define GEM_CLK_DIV32 2
+#define GEM_CLK_DIV48 3
+#define GEM_CLK_DIV64 4
+#define GEM_CLK_DIV96 5
+#define GEM_CLK_DIV128 6
+#define GEM_CLK_DIV224 7
+
+#define GEM_MDC_SET(val) FIELD_PREP(GENMASK(20, 18), val)
+
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* 0x0 - Network Control reg */
@@ -220,6 +227,7 @@ struct zynq_gem_priv {
struct mii_dev *bus;
struct clk rx_clk;
struct clk tx_clk;
+ struct clk pclk;
u32 max_speed;
bool int_pcs;
bool dma_64bit;
@@ -352,6 +360,32 @@ static int zynq_phy_init(struct udevice *dev)
return phy_config(priv->phydev);
}
+static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv)
+{
+ u32 config;
+ unsigned long pclk_hz;
+
+ pclk_hz = clk_get_rate(&priv->pclk);
+ if (pclk_hz <= 20000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV8);
+ else if (pclk_hz <= 40000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV16);
+ else if (pclk_hz <= 80000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV32);
+ else if (pclk_hz <= 120000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV48);
+ else if (pclk_hz <= 160000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV64);
+ else if (pclk_hz <= 240000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV96);
+ else if (pclk_hz <= 320000000)
+ config = GEM_MDC_SET(GEM_CLK_DIV128);
+ else
+ config = GEM_MDC_SET(GEM_CLK_DIV224);
+
+ return config;
+}
+
static int zynq_gem_init(struct udevice *dev)
{
u32 i, nwconfig;
@@ -460,7 +494,8 @@ static int zynq_gem_init(struct udevice *dev)
return -1;
}
- nwconfig = ZYNQ_GEM_NWCFG_INIT;
+ nwconfig = gem_mdc_clk_div(priv);
+ nwconfig |= ZYNQ_GEM_NWCFG_INIT;
/*
* Set SGMII enable PCS selection only if internal PCS/PMA
@@ -828,6 +863,12 @@ static int zynq_gem_probe(struct udevice *dev)
}
}
+ ret = clk_get_by_name(dev, "pclk", &priv->pclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get pclk clock\n");
+ goto err2;
+ }
+
if (IS_ENABLED(CONFIG_DM_ETH_PHY))
priv->bus = eth_phy_get_mdio_bus(dev);
diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index ee6529b3c2..02626a7561 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -3,7 +3,7 @@
* Xilinx pinctrl driver for ZynqMP
*
* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* Copyright (C) 2021 Xilinx, Inc. All rights reserved.
*/
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index afa277f604..d9a5944965 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -3,7 +3,7 @@
* Xilinx ZynqMP SOC driver
*
* Copyright (C) 2021 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 434c6038f3..a7685a2f51 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -130,7 +130,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv)
#if defined(CONFIG_DM_GPIO)
int cadence_qspi_versal_flash_reset(struct udevice *dev)
{
-#ifndef CONFIG_ARCH_VERSAL_NET
struct gpio_desc gpio;
u32 reset_gpio;
int ret;
@@ -166,7 +165,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev)
/* Set value 1 to pin */
dm_gpio_set_value(&gpio, 1);
udelay(1);
-#endif
+
return 0;
}
#else
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 2d715e478c..cc3a54f295 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -249,17 +249,14 @@ static int cadence_spi_probe(struct udevice *bus)
priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
- if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
- /* Versal platform uses spi calibration to set read delay */
+ /* Versal and Versal-NET use spi calibration to set read delay */
+ if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
+ CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
if (priv->read_delay >= 0)
priv->read_delay = -1;
- /* Reset ospi flash device */
- ret = cadence_qspi_versal_flash_reset(bus);
- if (ret)
- return ret;
- }
- return 0;
+ /* Reset ospi flash device */
+ return cadence_qspi_versal_flash_reset(bus);
}
static int cadence_spi_remove(struct udevice *dev)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 33575fe757..b58a3f632a 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -363,8 +363,8 @@ static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width)
return -EOPNOTSUPP;
}
-bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
- const struct spi_mem_op *op)
+static bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth))
return false;
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index d1d4048966..cb52c0f307 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -747,8 +747,8 @@ static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width)
return -EOPNOTSUPP;
}
-bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
- const struct spi_mem_op *op)
+static bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth))
return false;
diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c
index 0f9fb02002..b38c400016 100644
--- a/drivers/watchdog/xilinx_tb_wdt.c
+++ b/drivers/watchdog/xilinx_tb_wdt.c
@@ -2,7 +2,7 @@
/*
* Xilinx AXI platforms watchdog timer driver.
*
- * Author(s): Michal Simek <michal.simek@xilinx.com>
+ * Author(s): Michal Simek <michal.simek@amd.com>
* Shreenidhi Shedi <yesshedi@gmail.com>
*
* Copyright (c) 2011-2018 Xilinx Inc.
diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c
index d582e3cc8f..963ab22fb4 100644
--- a/drivers/watchdog/xilinx_wwdt.c
+++ b/drivers/watchdog/xilinx_wwdt.c
@@ -2,7 +2,7 @@
/*
* Xilinx window watchdog timer driver.
*
- * Author(s): Michal Simek <michal.simek@xilinx.com>
+ * Author(s): Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
*
* Copyright (c) 2020, Xilinx Inc.
@@ -191,7 +191,8 @@ static const struct wdt_ops xlnx_wwdt_ops = {
};
static const struct udevice_id xlnx_wwdt_ids[] = {
- { .compatible = "xlnx,versal-wwdt-1.0", },
+ { .compatible = "xlnx,versal-wwdt", },
+ { .compatible = "xlnx,versal-wwdt-1.0", }, /* deprecated */
{},
};
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-28 13:30:05 +0000