diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/Makefile | 1 | ||||
| -rw-r--r-- | drivers/bus/Kconfig | 16 | ||||
| -rw-r--r-- | drivers/bus/Makefile | 6 | ||||
| -rw-r--r-- | drivers/bus/uniphier-system-bus.c | 100 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/denali.c | 11 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/denali.h | 1 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/denali_dt.c | 8 | ||||
| -rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 7 | ||||
| -rw-r--r-- | drivers/serial/serial_uniphier.c | 90 | ||||
| -rw-r--r-- | drivers/spi/Kconfig | 26 | ||||
| -rw-r--r-- | drivers/spi/kirkwood_spi.c | 136 | ||||
| -rw-r--r-- | drivers/spi/omap3_spi.c | 136 | ||||
| -rw-r--r-- | drivers/spi/soft_spi.c | 48 |
14 files changed, 258 insertions, 330 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig index e34a22708c..7a839fa1aa 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -10,6 +10,8 @@ source "drivers/ata/Kconfig" source "drivers/axi/Kconfig" +source "drivers/bus/Kconfig" + source "drivers/block/Kconfig" source "drivers/bootcount/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 94e8c5da17..afd159e903 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -74,6 +74,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += adc/ obj-y += ata/ +obj-y += bus/ obj-$(CONFIG_DM_DEMO) += demo/ obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig new file mode 100644 index 0000000000..07a33c6287 --- /dev/null +++ b/drivers/bus/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Bus Devices +# + +menu "Bus devices" + +config UNIPHIER_SYSTEM_BUS + bool "UniPhier System Bus driver" + depends on ARCH_UNIPHIER + default y + help + Support for UniPhier System Bus, a simple external bus. This is + needed to use on-board devices connected to UniPhier SoCs. + +endmenu diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile new file mode 100644 index 0000000000..0b97fc1f8b --- /dev/null +++ b/drivers/bus/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the bus drivers. +# + +obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o diff --git a/drivers/bus/uniphier-system-bus.c b/drivers/bus/uniphier-system-bus.c new file mode 100644 index 0000000000..ea08d66a07 --- /dev/null +++ b/drivers/bus/uniphier-system-bus.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <linux/bitops.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <linux/types.h> +#include <dm.h> + +/* System Bus Controller registers */ +#define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */ +#define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */ +#define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */ +#define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */ +#define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */ +#define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */ +#define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */ + +#define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */ + +#if 1 +/* slower but LED works */ +#define SBCTRL0_VALUE 0x55450000 +#define SBCTRL1_VALUE 0x07168d00 +#define SBCTRL2_VALUE 0x34000009 +#define SBCTRL4_VALUE 0x02110110 + +#else +/* faster but LED does not work */ +#define SBCTRL0_VALUE 0x55450000 +#define SBCTRL1_VALUE 0x06057700 +/* NOR flash needs more wait counts than SRAM */ +#define SBCTRL2_VALUE 0x34000009 +#define SBCTRL4_VALUE 0x02110210 +#endif + +void uniphier_system_bus_set_reg(void __iomem *membase) +{ + void __iomem *bank0_base = membase; + void __iomem *bank1_base = membase + UNIPHIER_SBC_STRIDE; + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_VALUE, bank1_base + UNIPHIER_SBC_CTRL0); + writel(SBCTRL1_VALUE, bank1_base + UNIPHIER_SBC_CTRL1); + writel(SBCTRL2_VALUE, bank1_base + UNIPHIER_SBC_CTRL2); + writel(SBCTRL4_VALUE, bank1_base + UNIPHIER_SBC_CTRL4); + + if (readl(bank1_base + UNIPHIER_SBC_BASE) & UNIPHIER_SBC_BASE_BE) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, bank0_base + UNIPHIER_SBC_BASE); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, bank0_base + UNIPHIER_SBC_BASE); /* dummy */ + writel(0x0200be01, bank0_base + UNIPHIER_SBC_BASE); + } +} + +static int uniphier_system_bus_probe(struct udevice *dev) +{ + fdt_addr_t base; + void __iomem *membase; + + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + membase = devm_ioremap(dev, base, SZ_1K); + if (!membase) + return -ENOMEM; + + uniphier_system_bus_set_reg(membase); + + return 0; +} + +static const struct udevice_id uniphier_system_bus_match[] = { + { .compatible = "socionext,uniphier-system-bus" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_system_bus_driver) = { + .name = "uniphier-system-bus", + .id = UCLASS_SIMPLE_BUS, + .of_match = uniphier_system_bus_match, + .probe = uniphier_system_bus_probe, +}; diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 15e90291de..ab91db8546 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -1220,6 +1220,17 @@ static int denali_multidev_fixup(struct denali_nand_info *denali) return 0; } +int denali_wait_reset_complete(struct denali_nand_info *denali) +{ + u32 irq_status; + + irq_status = denali_wait_for_irq(denali, INTR__RST_COMP); + if (!(irq_status & INTR__RST_COMP)) + return -EIO; + + return 0; +} + int denali_init(struct denali_nand_info *denali) { struct nand_chip *chip = &denali->nand; diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 019deda094..6cd02b2e26 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -321,6 +321,7 @@ struct denali_nand_info { #define DENALI_CAP_DMA_64BIT BIT(1) int denali_calc_ecc_bytes(int step_size, int strength); +int denali_wait_reset_complete(struct denali_nand_info *denali); int denali_init(struct denali_nand_info *denali); #endif /* __DENALI_H__ */ diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 2728e8098f..8318ff507f 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -148,6 +148,8 @@ static int denali_dt_probe(struct udevice *dev) if (ret) { dev_warn(dev, "Can't get reset: %d\n", ret); } else { + reset_assert_bulk(&resets); + udelay(2); reset_deassert_bulk(&resets); /* @@ -155,7 +157,11 @@ static int denali_dt_probe(struct udevice *dev) * kicked (bootstrap process). The driver must wait until it is * finished. Otherwise, it will result in unpredictable behavior. */ - udelay(200); + ret = denali_wait_reset_complete(denali); + if (ret) { + dev_err(denali->dev, "reset not completed.\n"); + return ret; + } } return denali_init(denali); diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 1e3f51d2ac..fdcd830ce4 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1291,7 +1291,7 @@ write_err: return ret; } -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) /** * macronix_quad_enable() - set QE bit in Status Register. * @nor: pointer to a 'struct spi_nor' @@ -1969,7 +1969,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, params->quad_enable = spansion_no_read_cr_quad_enable; break; #endif -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) case BFPT_DWORD15_QER_SR1_BIT6: params->quad_enable = macronix_quad_enable; break; @@ -2206,8 +2206,9 @@ static int spi_nor_init_params(struct spi_nor *nor, if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | SNOR_HWCAPS_PP_QUAD)) { switch (JEDEC_MFR(info)) { -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) case SNOR_MFR_MACRONIX: + case SNOR_MFR_ISSI: params->quad_enable = macronix_quad_enable; break; #endif diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index c7f46e5598..ad691b66da 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -7,6 +7,8 @@ #include <common.h> #include <dm.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> #include <linux/bug.h> #include <linux/io.h> #include <linux/serial_reg.h> @@ -15,77 +17,72 @@ #include <serial.h> #include <fdtdec.h> -/* - * Note: Register map is slightly different from that of 16550. - */ -struct uniphier_serial { - u32 rx; /* In: Receive buffer */ -#define tx rx /* Out: Transmit buffer */ - u32 ier; /* Interrupt Enable Register */ - u32 iir; /* In: Interrupt ID Register */ - u32 char_fcr; /* Charactor / FIFO Control Register */ - u32 lcr_mcr; /* Line/Modem Control Register */ -#define LCR_SHIFT 8 -#define LCR_MASK (0xff << (LCR_SHIFT)) - u32 lsr; /* In: Line Status Register */ - u32 msr; /* In: Modem Status Register */ - u32 __rsv0; - u32 __rsv1; - u32 dlr; /* Divisor Latch Register */ -}; +#define UNIPHIER_UART_REGSHIFT 2 + +#define UNIPHIER_UART_RX (0 << (UNIPHIER_UART_REGSHIFT)) +#define UNIPHIER_UART_TX UNIPHIER_UART_RX +/* bit[15:8] = CHAR, bit[7:0] = FCR */ +#define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT)) +#define UNIPHIER_UART_FCR_MASK GENMASK(7, 0) +/* bit[15:8] = LCR, bit[7:0] = MCR */ +#define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT)) +#define UNIPHIER_UART_LCR_MASK GENMASK(15, 8) +#define UNIPHIER_UART_LSR (5 << (UNIPHIER_UART_REGSHIFT)) +/* Divisor Latch Register */ +#define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) struct uniphier_serial_priv { - struct uniphier_serial __iomem *membase; + void __iomem *membase; unsigned int uartclk; }; -#define uniphier_serial_port(dev) \ - ((struct uniphier_serial_priv *)dev_get_priv(dev))->membase - static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) { struct uniphier_serial_priv *priv = dev_get_priv(dev); - struct uniphier_serial __iomem *port = uniphier_serial_port(dev); - const unsigned int mode_x_div = 16; + static const unsigned int mode_x_div = 16; unsigned int divisor; divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate); - writel(divisor, &port->dlr); + /* flush the trasmitter before changing hw setting */ + while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT)) + ; + + writel(divisor, priv->membase + UNIPHIER_UART_DLR); return 0; } static int uniphier_serial_getc(struct udevice *dev) { - struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + struct uniphier_serial_priv *priv = dev_get_priv(dev); - if (!(readl(&port->lsr) & UART_LSR_DR)) + if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR)) return -EAGAIN; - return readl(&port->rx); + return readl(priv->membase + UNIPHIER_UART_RX); } static int uniphier_serial_putc(struct udevice *dev, const char c) { - struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + struct uniphier_serial_priv *priv = dev_get_priv(dev); - if (!(readl(&port->lsr) & UART_LSR_THRE)) + if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_THRE)) return -EAGAIN; - writel(c, &port->tx); + writel(c, priv->membase + UNIPHIER_UART_TX); return 0; } static int uniphier_serial_pending(struct udevice *dev, bool input) { - struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + struct uniphier_serial_priv *priv = dev_get_priv(dev); if (input) - return readl(&port->lsr) & UART_LSR_DR; + return readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR; else - return !(readl(&port->lsr) & UART_LSR_THRE); + return !(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_THRE); } /* @@ -113,7 +110,6 @@ static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = { static int uniphier_serial_probe(struct udevice *dev) { struct uniphier_serial_priv *priv = dev_get_priv(dev); - struct uniphier_serial __iomem *port; const struct uniphier_serial_clk_data *clk_data; ofnode root_node; fdt_addr_t base; @@ -123,12 +119,10 @@ static int uniphier_serial_probe(struct udevice *dev) if (base == FDT_ADDR_T_NONE) return -EINVAL; - port = devm_ioremap(dev, base, SZ_64); - if (!port) + priv->membase = devm_ioremap(dev, base, SZ_64); + if (!priv->membase) return -ENOMEM; - priv->membase = port; - root_node = ofnode_path("/"); clk_data = uniphier_serial_clk_data; while (clk_data->compatible) { @@ -143,10 +137,20 @@ static int uniphier_serial_probe(struct udevice *dev) priv->uartclk = clk_data->clk_rate; - tmp = readl(&port->lcr_mcr); - tmp &= ~LCR_MASK; - tmp |= UART_LCR_WLEN8 << LCR_SHIFT; - writel(tmp, &port->lcr_mcr); + /* flush the trasmitter empty before changing hw setting */ + while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT)) + ; + + /* enable FIFO */ + tmp = readl(priv->membase + UNIPHIER_UART_CHAR_FCR); + tmp &= ~UNIPHIER_UART_FCR_MASK; + tmp |= FIELD_PREP(UNIPHIER_UART_FCR_MASK, UART_FCR_ENABLE_FIFO); + writel(tmp, priv->membase + UNIPHIER_UART_CHAR_FCR); + + tmp = readl(priv->membase + UNIPHIER_UART_LCR_MCR); + tmp &= ~UNIPHIER_UART_LCR_MASK; + tmp |= FIELD_PREP(UNIPHIER_UART_LCR_MASK, UART_LCR_WLEN8); + writel(tmp, priv->membase + UNIPHIER_UART_LCR_MCR); return 0; } diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 09b9cb17d8..3a8add98f7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -162,6 +162,12 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config KIRKWOOD_SPI + bool "Marvell Kirkwood SPI Driver" + help + Enable support for SPI on various Marvell SoCs, such as + Kirkwood and Armada 375. + config MESON_SPIFC bool "Amlogic Meson SPI Flash Controller driver" depends on ARCH_MESON @@ -226,6 +232,13 @@ config NXP_FSPI Enable the NXP FlexSPI (FSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this NXP IP core. +config OMAP3_SPI + bool "McSPI driver for OMAP" + help + SPI master controller for OMAP24XX and later Multichannel SPI + (McSPI). This driver be used to access SPI chips on platforms + embedding this OMAP3 McSPI IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32 @@ -417,23 +430,10 @@ config SH_QSPI Enable the Renesas Quad SPI controller driver. This driver can be used on Renesas SoCs. -config KIRKWOOD_SPI - bool "Marvell Kirkwood SPI Driver" - help - Enable support for SPI on various Marvell SoCs, such as - Kirkwood and Armada 375. - config MXC_SPI bool "MXC SPI Driver" help Enable the MXC SPI controller driver. This driver can be used on various i.MX SoCs such as i.MX31/35/51/6/7. -config OMAP3_SPI - bool "McSPI driver for OMAP" - help - SPI master controller for OMAP24XX and later Multichannel SPI - (McSPI). This driver be used to access SPI chips on platforms - embedding this OMAP3 McSPI IP core. - endif # menu "SPI Support" diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index c03923f874..92dc2e13c5 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -19,6 +19,19 @@ #endif #include <asm/arch-mvebu/spi.h> +struct mvebu_spi_dev { + bool is_errata_50mhz_ac; +}; + +struct mvebu_spi_platdata { + struct kwspi_registers *spireg; + bool is_errata_50mhz_ac; +}; + +struct mvebu_spi_priv { + struct kwspi_registers *spireg; +}; + static void _spi_cs_activate(struct kwspi_registers *reg) { setbits_le32(®->ctrl, KWSPI_CSN_ACT); @@ -94,128 +107,6 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, return 0; } -#if !CONFIG_IS_ENABLED(DM_SPI) - -static struct kwspi_registers *spireg = - (struct kwspi_registers *)MVEBU_SPI_BASE; - -#ifdef CONFIG_ARCH_KIRKWOOD -static u32 cs_spi_mpp_back[2]; -#endif - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct spi_slave *slave; - u32 data; -#ifdef CONFIG_ARCH_KIRKWOOD - static const u32 kwspi_mpp_config[2][2] = { - { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ - { MPP7_SPI_SCn, 0 } /* if cs != 0 */ - }; -#endif - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - slave = spi_alloc_slave_base(bus, cs); - if (!slave) - return NULL; - - writel(KWSPI_SMEMRDY, &spireg->ctrl); - - /* calculate spi clock prescaller using max_hz */ - data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10; - data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; - data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; - - /* program spi clock prescaller using max_hz */ - writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg); - debug("data = 0x%08x\n", data); - - writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); - writel(KWSPI_IRQMASK, &spireg->irq_mask); - -#ifdef CONFIG_ARCH_KIRKWOOD - /* program mpp registers to select SPI_CSn */ - kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); -#endif - - return slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ -#ifdef CONFIG_ARCH_KIRKWOOD - kirkwood_mpp_conf(cs_spi_mpp_back, NULL); -#endif - free(slave); -} - -__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - -int spi_claim_bus(struct spi_slave *slave) -{ - return board_spi_claim_bus(slave); -} - -__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave) -{ -} - -void spi_release_bus(struct spi_slave *slave) -{ - board_spi_release_bus(slave); -} - -#ifndef CONFIG_SPI_CS_IS_VALID -/* - * you can define this function board specific - * define above CONFIG in board specific config file and - * provide the function in board specific src file - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && (cs == 0 || cs == 1); -} -#endif - -void spi_cs_activate(struct spi_slave *slave) -{ - _spi_cs_activate(spireg); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - _spi_cs_deactivate(spireg); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - return _spi_xfer(spireg, bitlen, dout, din, flags); -} - -#else - -/* Here now the DM part */ - -struct mvebu_spi_dev { - bool is_errata_50mhz_ac; -}; - -struct mvebu_spi_platdata { - struct kwspi_registers *spireg; - bool is_errata_50mhz_ac; -}; - -struct mvebu_spi_priv { - struct kwspi_registers *spireg; -}; - static int mvebu_spi_set_speed(struct udevice *bus, uint hz) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); @@ -409,4 +300,3 @@ U_BOOT_DRIVER(mvebu_spi) = { .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv), .probe = mvebu_spi_probe, }; -#endif diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index ae08531f1e..39e6813469 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -25,16 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) -#define OMAP3_MCSPI1_BASE 0x48030100 -#define OMAP3_MCSPI2_BASE 0x481A0100 -#else -#define OMAP3_MCSPI1_BASE 0x48098000 -#define OMAP3_MCSPI2_BASE 0x4809A000 -#define OMAP3_MCSPI3_BASE 0x480B8000 -#define OMAP3_MCSPI4_BASE 0x480BA000 -#endif - #define OMAP4_MCSPI_REG_OFFSET 0x100 struct omap2_mcspi_platform_config { @@ -109,9 +99,6 @@ struct mcspi { }; struct omap3_spi_priv { -#if !CONFIG_IS_ENABLED(DM_SPI) - struct spi_slave slave; -#endif struct mcspi *regs; unsigned int cs; unsigned int freq; @@ -455,128 +442,6 @@ static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) writel(conf, &priv->regs->modulctrl); } -#if !CONFIG_IS_ENABLED(DM_SPI) - -static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave) -{ - return container_of(slave, struct omap3_spi_priv, slave); -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - free(priv); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - spi_reset(priv->regs); - - _omap3_spi_claim_bus(priv); - _omap3_spi_set_wordlen(priv); - _omap3_spi_set_mode(priv); - _omap3_spi_set_speed(priv); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct omap3_spi_priv *priv; - struct mcspi *regs; - - /* - * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules) - * with different number of chip selects (CS, channels): - * McSPI1 has 4 CS (bus 0, cs 0 - 3) - * McSPI2 has 2 CS (bus 1, cs 0 - 1) - * McSPI3 has 2 CS (bus 2, cs 0 - 1) - * McSPI4 has 1 CS (bus 3, cs 0) - */ - - switch (bus) { - case 0: - regs = (struct mcspi *)OMAP3_MCSPI1_BASE; - break; -#ifdef OMAP3_MCSPI2_BASE - case 1: - regs = (struct mcspi *)OMAP3_MCSPI2_BASE; - break; -#endif -#ifdef OMAP3_MCSPI3_BASE - case 2: - regs = (struct mcspi *)OMAP3_MCSPI3_BASE; - break; -#endif -#ifdef OMAP3_MCSPI4_BASE - case 3: - regs = (struct mcspi *)OMAP3_MCSPI4_BASE; - break; -#endif - default: - printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus); - return NULL; - } - - if (((bus == 0) && (cs > 3)) || - ((bus == 1) && (cs > 1)) || - ((bus == 2) && (cs > 1)) || - ((bus == 3) && (cs > 0))) { - printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus); - return NULL; - } - - if (max_hz > OMAP3_MCSPI_MAX_FREQ) { - printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n", - max_hz); - return NULL; - } - - if (mode > SPI_MODE_3) { - printf("SPI error: unsupported SPI mode %i\n", mode); - return NULL; - } - - priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs); - if (!priv) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } - - priv->regs = regs; - priv->cs = cs; - priv->freq = max_hz; - priv->mode = mode; - priv->wordlen = priv->slave.wordlen; -#if 0 - /* Please migrate to DM_SPI support for this feature. */ - priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; -#endif - - return &priv->slave; -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct omap3_spi_priv *priv = to_omap3_spi(slave); - - return _spi_xfer(priv, bitlen, dout, din, flags); -} - -#else - static int omap3_spi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -701,4 +566,3 @@ U_BOOT_DRIVER(omap3_spi) = { .ops = &omap3_spi_ops, .priv_auto_alloc_size = sizeof(struct omap3_spi_priv), }; -#endif diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index e8d7758da0..153bbf8b25 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -61,10 +61,12 @@ static int soft_spi_sda(struct udevice *dev, int bit) static int soft_spi_cs_activate(struct udevice *dev) { struct udevice *bus = dev_get_parent(dev); + struct soft_spi_priv *priv = dev_get_priv(bus); struct soft_spi_platdata *plat = dev_get_platdata(bus); + int cidle = !!(priv->mode & SPI_CPOL); dm_gpio_set_value(&plat->cs, 0); - dm_gpio_set_value(&plat->sclk, 0); + dm_gpio_set_value(&plat->sclk, cidle); /* to idle */ dm_gpio_set_value(&plat->cs, 1); return 0; @@ -82,11 +84,14 @@ static int soft_spi_cs_deactivate(struct udevice *dev) static int soft_spi_claim_bus(struct udevice *dev) { + struct udevice *bus = dev_get_parent(dev); + struct soft_spi_priv *priv = dev_get_priv(bus); + int cidle = !!(priv->mode & SPI_CPOL); /* * Make sure the SPI clock is in idle state as defined for * this slave. */ - return soft_spi_scl(dev, 0); + return soft_spi_scl(dev, cidle); } static int soft_spi_release_bus(struct udevice *dev) @@ -117,7 +122,8 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, uchar tmpdout = 0; const u8 *txd = dout; u8 *rxd = din; - int cpha = priv->mode & SPI_CPHA; + int cpha = !!(priv->mode & SPI_CPHA); + int cidle = !!(priv->mode & SPI_CPOL); unsigned int j; debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n", @@ -143,22 +149,42 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, tmpdin = 0; } - if (!cpha) - soft_spi_scl(dev, 0); + /* + * CPOL 0: idle is low (0), active is high (1) + * CPOL 1: idle is high (1), active is low (0) + */ + + /* + * drive bit + * CPHA 1: CLK from idle to active + */ + if (cpha) + soft_spi_scl(dev, !cidle); if ((plat->flags & SPI_MASTER_NO_TX) == 0) soft_spi_sda(dev, !!(tmpdout & 0x80)); udelay(plat->spi_delay_us); - if (cpha) - soft_spi_scl(dev, 0); + + /* + * sample bit + * CPHA 0: CLK from idle to active + * CPHA 1: CLK from active to idle + */ + if (!cpha) + soft_spi_scl(dev, !cidle); else - soft_spi_scl(dev, 1); + soft_spi_scl(dev, cidle); tmpdin <<= 1; if ((plat->flags & SPI_MASTER_NO_RX) == 0) tmpdin |= dm_gpio_get_value(&plat->miso); tmpdout <<= 1; udelay(plat->spi_delay_us); - if (cpha) - soft_spi_scl(dev, 1); + + /* + * drive bit + * CPHA 0: CLK from active to idle + */ + if (!cpha) + soft_spi_scl(dev, cidle); } /* * If the number of bits isn't a multiple of 8, shift the last @@ -179,7 +205,7 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, static int soft_spi_set_speed(struct udevice *dev, unsigned int speed) { - /* Accept any speed */ + /* Ignore any speed settings. Speed is implemented via "spi-delay-us" */ return 0; } |