diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/misc/mxc_ocotp.c | 17 | ||||
| -rw-r--r-- | drivers/pci/pcie_imx.c | 15 | ||||
| -rw-r--r-- | drivers/spi/fsl_qspi.c | 18 |
3 files changed, 48 insertions, 2 deletions
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 8986bb4ad0..18a2730909 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -342,6 +342,23 @@ int fuse_sense(u32 bank, u32 word, u32 *val) static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, const char *caller) { +#ifdef CONFIG_MX7ULP + u32 val; + int ret; + + /* Only bank 0 and 1 are redundancy mode, others are ECC mode */ + if (bank != 0 && bank != 1) { + ret = fuse_sense(bank, word, &val); + if (ret) + return ret; + + if (val != 0) { + printf("mxc_ocotp: The word has been programmed, no more write\n"); + return -EPERM; + } + } +#endif + return prepare_access(regs, bank, word, true, caller); } diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 2900c8d9d1..ef66a1d3f4 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -517,10 +517,12 @@ static int imx6_pcie_init_phy(void) __weak int imx6_pcie_toggle_power(void) { #ifdef CONFIG_PCIE_IMX_POWER_GPIO + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power"); gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); mdelay(20); gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); mdelay(20); + gpio_free(CONFIG_PCIE_IMX_POWER_GPIO); #endif return 0; } @@ -556,10 +558,12 @@ __weak int imx6_pcie_toggle_reset(void) * state due to being previously used in U-Boot. */ #ifdef CONFIG_PCIE_IMX_PERST_GPIO + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset"); gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); mdelay(20); gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); mdelay(20); + gpio_free(CONFIG_PCIE_IMX_PERST_GPIO); #else puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); #endif @@ -612,6 +616,17 @@ static int imx_pcie_link_up(void) imx_pcie_regions_setup(); /* + * By default, the subordinate is set equally to the secondary + * bus (0x01) when the RC boots. + * This means that theoretically, only bus 1 is reachable from the RC. + * Force the PCIe RC subordinate to 0xff, otherwise no downstream + * devices will be detected if the enumeration is applied strictly. + */ + tmp = readl(MX6_DBI_ADDR + 0x18); + tmp |= (0xff << 16); + writel(tmp, MX6_DBI_ADDR + 0x18); + + /* * FIXME: Force the PCIe RC to Gen1 operation * The RC must be forced into Gen1 mode before bringing the link * up, otherwise no downstream devices are detected. After the diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 0f3f7d97f0..2f5345f1cf 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; #define RX_BUFFER_SIZE 0x80 -#ifdef CONFIG_MX6SX +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ + defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) #define TX_BUFFER_SIZE 0x200 #else #define TX_BUFFER_SIZE 0x40 @@ -268,7 +269,8 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif -#ifdef CONFIG_MX6SX +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ + defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) /* * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. * So, Use IDATSZ in IPCR to determine the size and here set 0. @@ -905,6 +907,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, qspi->slave.max_write_size = TX_BUFFER_SIZE; mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr); + + /* Set endianness to LE for i.mx */ + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) + mcr_val = QSPI_MCR_END_CFD_LE; + qspi_write32(qspi->priv.flags, ®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | (mcr_val & QSPI_MCR_END_CFD_MASK)); @@ -1023,6 +1030,11 @@ static int fsl_qspi_probe(struct udevice *bus) } mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); + + /* Set endianness to LE for i.mx */ + if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) + mcr_val = QSPI_MCR_END_CFD_LE; + qspi_write32(priv->flags, &priv->regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | (mcr_val & QSPI_MCR_END_CFD_MASK)); @@ -1227,6 +1239,8 @@ static const struct dm_spi_ops fsl_qspi_ops = { static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,vf610-qspi" }, { .compatible = "fsl,imx6sx-qspi" }, + { .compatible = "fsl,imx6ul-qspi" }, + { .compatible = "fsl,imx7d-qspi" }, { } }; |