diff options
Diffstat (limited to 'drivers')
56 files changed, 1726 insertions, 507 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 7ebee75c0a..4e95a68a2d 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -66,6 +66,14 @@ config DWC_AHSATA Enable this driver to support the DWC AHSATA SATA controller found in i.MX5 and i.MX6 SoCs. +config DWC_AHSATA_AHCI + bool "Enable DWC AHSATA AHCI driver support" + depends on DWC_AHSATA + depends on AHCI + default y + help + Enable this option unless you need your private ahci implementation + config FSL_SATA bool "Enable Freescale SATA controller driver support" select LIBATA @@ -101,6 +109,14 @@ config SATA_SIL3114 help Enable this driver to support the SIL3114 SATA controllers. +config SUNXI_AHCI + bool "Enable Allwinner SATA driver support" + depends on AHCI + default y if ARCH_SUNXI + help + Enable this driver to support the SATA controllers found in the + Allwinner A10, A20 and R40 SoCs. + config AHCI_MVEBU bool "Marvell EBU AHCI SATA support" depends on ARCH_MVEBU diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 10bed53bb3..a69edb10f7 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o obj-$(CONFIG_SATA_SIL) += sata_sil.o obj-$(CONFIG_SANDBOX) += sata_sandbox.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o +obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c new file mode 100644 index 0000000000..77b932aa03 --- /dev/null +++ b/drivers/ata/ahci_sunxi.c @@ -0,0 +1,125 @@ +#include <common.h> +#include <ahci.h> +#include <dm.h> +#include <scsi.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/gpio.h> + +#define AHCI_PHYCS0R 0x00c0 +#define AHCI_PHYCS1R 0x00c4 +#define AHCI_PHYCS2R 0x00c8 +#define AHCI_RWCR 0x00fc + +/* This magic PHY initialisation was taken from the Allwinner releases + * and Linux driver, but is completely undocumented. + */ +static int sunxi_ahci_phy_init(u8 *reg_base) +{ + u32 reg_val; + int timeout; + + writel(0, reg_base + AHCI_RWCR); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, + (0x7 << 24), + (0x5 << 24) | (0x1 << 23) | (0x1 << 18)); + clrsetbits_le32(reg_base + AHCI_PHYCS1R, + (0x3 << 16) | (0x1f << 8) | (0x3 << 6), + (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); + setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); + clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); + clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); + + timeout = 250; /* Power up takes approx 50 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); + if (reg_val == (0x2 << 28)) + break; + if (--timeout == 0) { + printf("AHCI PHY power up failed.\n"); + return -EIO; + } + udelay(1); + }; + + setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); + + timeout = 100; /* Calibration takes approx 10 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); + if (reg_val == 0x0) + break; + if (--timeout == 0) { + printf("AHCI PHY calibration failed.\n"); + return -EIO; + } + udelay(1); + } + + mdelay(15); + + writel(0x7, reg_base + AHCI_RWCR); + + return 0; +} + +static int sunxi_sata_probe(struct udevice *dev) +{ + ulong base; + u8 *reg; + int ret; + + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) { + debug("%s: Failed to find address (err=%d\n)", __func__, ret); + return -EINVAL; + } + reg = (u8 *)base; + ret = sunxi_ahci_phy_init(reg); + if (ret) { + debug("%s: Failed to init phy (err=%d\n)", __func__, ret); + return ret; + } + ret = ahci_probe_scsi(dev, base); + if (ret) { + debug("%s: Failed to probe (err=%d\n)", __func__, ret); + return ret; + } + + return 0; +} + +static int sunxi_sata_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + int ret; + + ret = ahci_bind_scsi(dev, &scsi_dev); + if (ret) { + debug("%s: Failed to bind (err=%d\n)", __func__, ret); + return ret; + } + + return 0; +} + +static const struct udevice_id sunxi_ahci_ids[] = { + { .compatible = "allwinner,sun4i-a10-ahci" }, + { .compatible = "allwinner,sun8i-r40-ahci" }, + { } +}; + +U_BOOT_DRIVER(ahci_sunxi_drv) = { + .name = "ahci_sunxi", + .id = UCLASS_AHCI, + .of_match = sunxi_ahci_ids, + .bind = sunxi_sata_bind, + .probe = sunxi_sata_probe, +}; diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index 4c5b98482f..afced8e7e3 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -16,6 +16,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/mach-imx/sata.h> #include <linux/bitops.h> #include <linux/ctype.h> #include <linux/errno.h> @@ -511,15 +512,9 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) static void dwc_ahsata_print_info(struct blk_desc *pdev) { printf("SATA Device Info:\n\r"); -#ifdef CONFIG_SYS_64BIT_LBA printf("S/N: %s\n\rProduct model number: %s\n\r" - "Firmware version: %s\n\rCapacity: %lld sectors\n\r", + "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r", pdev->product, pdev->vendor, pdev->revision, pdev->lba); -#else - printf("S/N: %s\n\rProduct model number: %s\n\r" - "Firmware version: %s\n\rCapacity: %ld sectors\n\r", - pdev->product, pdev->vendor, pdev->revision, pdev->lba); -#endif } static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) @@ -754,7 +749,6 @@ static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; - u64 n_sectors; u8 port = uc_priv->hard_port_no; ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS); @@ -773,9 +767,8 @@ static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); memcpy(pdev->vendor, product, sizeof(product)); - /* Totoal sectors */ - n_sectors = ata_id_n_sectors(id); - pdev->lba = (u32)n_sectors; + /* Total sectors */ + pdev->lba = ata_id_n_sectors(id); pdev->type = DEV_TYPE_HARDDISK; pdev->blksz = ATA_SECT_SIZE; @@ -1028,6 +1021,9 @@ int dwc_ahsata_probe(struct udevice *dev) struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); int ret; +#if defined(CONFIG_MX6) + setup_sata(); +#endif uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); @@ -1075,4 +1071,24 @@ U_BOOT_DRIVER(dwc_ahsata_blk) = { .ops = &dwc_ahsata_blk_ops, }; +#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI) +struct ahci_ops dwc_ahsata_ahci_ops = { + .port_status = dwc_ahsata_port_status, + .reset = dwc_ahsata_bus_reset, + .scan = dwc_ahsata_scan, +}; + +static const struct udevice_id dwc_ahsata_ahci_ids[] = { + { .compatible = "fsl,imx6q-ahci" }, + { } +}; + +U_BOOT_DRIVER(dwc_ahsata_ahci) = { + .name = "dwc_ahsata_ahci", + .id = UCLASS_AHCI, + .of_match = dwc_ahsata_ahci_ids, + .ops = &dwc_ahsata_ahci_ops, + .probe = dwc_ahsata_probe, +}; +#endif #endif diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index 482f0937cb..b09c37db40 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -434,6 +434,8 @@ static ulong zynq_clk_get_rate(struct clk *clk) case lqspi_clk ... pcap_clk: case sdio0_clk ... spi1_clk: return zynq_clk_get_peripheral_rate(priv, id, 0); + case i2c0_aper_clk ... i2c1_aper_clk: + return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); default: return -ENXIO; } diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 30beac98bb..44abc4f536 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -62,7 +62,6 @@ static struct ccu_reset r40_resets[] = { [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), - [RST_BUS_GMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)), @@ -75,6 +74,8 @@ static struct ccu_reset r40_resets[] = { [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)), + [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 2b28a97f6e..8f60b56eb8 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,5 +1,7 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select RAM if TARGET_SOCFPGA_GEN5 + select SPL_RAM if TARGET_SOCFPGA_GEN5 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 821060459c..fcd89b619d 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -3,14 +3,30 @@ * Copyright Altera Corporation (C) 2014-2015 */ #include <common.h> +#include <dm.h> #include <errno.h> #include <div64.h> +#include <ram.h> +#include <reset.h> #include <watchdog.h> #include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> #include <asm/arch/sdram.h> #include <asm/arch/system_manager.h> #include <asm/io.h> +#include "sequencer.h" + +#ifdef CONFIG_SPL_BUILD + +struct altera_gen5_sdram_priv { + struct ram_info info; +}; + +struct altera_gen5_sdram_platdata { + struct socfpga_sdr *sdr; +}; + struct sdram_prot_rule { u32 sdram_start; /* SDRAM start address */ u32 sdram_end; /* SDRAM end address */ @@ -26,8 +42,8 @@ struct sdram_prot_rule { static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl); /** * get_errata_rows() - Up the number of DRAM rows to cover entire address space @@ -104,7 +120,8 @@ static int get_errata_rows(const struct socfpga_sdram_config *cfg) } /* SDRAM protection rules vary from 0-19, a total of 20 rules. */ -static void sdram_set_rule(struct sdram_prot_rule *prule) +static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 lo_addr_bits; u32 hi_addr_bits; @@ -141,7 +158,8 @@ static void sdram_set_rule(struct sdram_prot_rule *prule) writel(0, &sdr_ctrl->prot_rule_rdwr); } -static void sdram_get_rule(struct sdram_prot_rule *prule) +static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 addr; u32 id; @@ -172,7 +190,8 @@ static void sdram_get_rule(struct sdram_prot_rule *prule) } static void -sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) +sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl, + const u32 sdram_start, const u32 sdram_end) { struct sdram_prot_rule rule; int rules; @@ -185,7 +204,7 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule); } /* new rule: accept SDRAM */ @@ -200,13 +219,13 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) rule.rule = 0; /* set new rule */ - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule); /* default rule: reject everything */ writel(0x3ff, &sdr_ctrl->protport_default); } -static void sdram_dump_protection_config(void) +static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl) { struct sdram_prot_rule rule; int rules; @@ -216,7 +235,7 @@ static void sdram_dump_protection_config(void) for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_get_rule(&rule); + sdram_get_rule(sdr_ctrl, &rule); debug("Rule %d, rules ...\n", rules); debug(" sdram start %x\n", rule.sdram_start); debug(" sdram end %x\n", rule.sdram_end); @@ -322,7 +341,8 @@ static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) * * This function loads the register values into the SDRAM controller block. */ -static void sdr_load_regs(const struct socfpga_sdram_config *cfg) +static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl, + const struct socfpga_sdram_config *cfg) { const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); const u32 dram_addrw = sdr_get_addr_rw(cfg); @@ -426,7 +446,8 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg) * * Initialize the SDRAM MMR. */ -int sdram_mmr_init_full(unsigned int sdr_phy_reg) +int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, + unsigned int sdr_phy_reg) { const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); const unsigned int rows = @@ -436,7 +457,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) writel(rows, &sysmgr_regs->iswgrp_handoff[4]); - sdr_load_regs(cfg); + sdr_load_regs(sdr_ctrl, cfg); /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); @@ -459,9 +480,10 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); - sdram_set_protection_config(0, sdram_calculate_size() - 1); + sdram_set_protection_config(sdr_ctrl, 0, + sdram_calculate_size(sdr_ctrl) - 1); - sdram_dump_protection_config(); + sdram_dump_protection_config(sdr_ctrl); return 0; } @@ -472,7 +494,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) * Calculate SDRAM device size based on SDRAM controller parameters. * Size is specified in bytes. */ -unsigned long sdram_calculate_size(void) +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) { unsigned long temp; unsigned long row, bank, col, cs, width; @@ -534,3 +556,94 @@ unsigned long sdram_calculate_size(void) return temp; } + +static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_gen5_sdram_platdata *plat = dev->platdata; + + plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0); + if (!plat->sdr) + return -ENODEV; + + return 0; +} + +static int altera_gen5_sdram_probe(struct udevice *dev) +{ + int ret; + unsigned long sdram_size; + struct altera_gen5_sdram_platdata *plat = dev->platdata; + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl; + struct reset_ctl_bulk resets; + + ret = reset_get_bulk(dev, &resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + reset_deassert_bulk(&resets); + + if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) { + puts("SDRAM init failed.\n"); + goto failed; + } + + debug("SDRAM: Calibrating PHY\n"); + /* SDRAM calibration */ + if (sdram_calibration_full(plat->sdr) == 0) { + puts("SDRAM calibration failed.\n"); + goto failed; + } + + sdram_size = sdram_calculate_size(sdr_ctrl); + debug("SDRAM: %ld MiB\n", sdram_size >> 20); + + /* Sanity check ensure correct SDRAM size specified */ + if (get_ram_size(0, sdram_size) != sdram_size) { + puts("SDRAM size check failed!\n"); + goto failed; + } + + priv->info.base = 0; + priv->info.size = sdram_size; + + return 0; + +failed: + reset_release_bulk(&resets); + return -ENODEV; +} + +static int altera_gen5_sdram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + + info->base = priv->info.base; + info->size = priv->info.size; + + return 0; +} + +static struct ram_ops altera_gen5_sdram_ops = { + .get_info = altera_gen5_sdram_get_info, +}; + +static const struct udevice_id altera_gen5_sdram_ids[] = { + { .compatible = "altr,sdr-ctl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(altera_gen5_sdram) = { + .name = "altr_sdr_ctl", + .id = UCLASS_RAM, + .of_match = altera_gen5_sdram_ids, + .ops = &altera_gen5_sdram_ops, + .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata), + .probe = altera_gen5_sdram_probe, + .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv), +}; + +#endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index a48567c109..e4d4a02ca2 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -7,12 +7,14 @@ #include <common.h> #include <errno.h> #include <div64.h> +#include <fdtdec.h> #include <asm/io.h> #include <wait_bit.h> #include <asm/arch/firewall_s10.h> #include <asm/arch/sdram_s10.h> #include <asm/arch/system_manager.h> #include <asm/arch/reset_manager.h> +#include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; @@ -21,6 +23,8 @@ static const struct socfpga_system_manager *sysmgr_regs = #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) +#define PGTABLE_OFF 0x4000 + /* The followring are the supported configurations */ u32 ddr_config[] = { /* DDR_CONFIG(Address order,Bank,Column,Row) */ @@ -134,6 +138,108 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size) +{ + phys_size_t i; + + if (addr % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: address 0x%llx is not cacheline size aligned.\n", + addr); + hang(); + } + + if (size % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: size 0x%llx is not multiple of cacheline size\n", + size); + hang(); + } + + /* Use DC ZVA instruction to clear memory to zeros by a cache line */ + for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) { + asm volatile("dc zva, %0" + : + : "r"(addr) + : "memory"); + addr += CONFIG_SYS_CACHELINE_SIZE; + } +} + +static void sdram_init_ecc_bits(bd_t *bd) +{ + phys_size_t size, size_init; + phys_addr_t start_addr; + int bank = 0; + unsigned int start = get_timer(0); + + icache_enable(); + + start_addr = bd->bi_dram[0].start; + size = bd->bi_dram[0].size; + + /* Initialize small block for page table */ + memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); + gd->arch.tlb_addr = start_addr + PGTABLE_OFF; + gd->arch.tlb_size = PGTABLE_SIZE; + start_addr += PGTABLE_SIZE + PGTABLE_OFF; + size -= (PGTABLE_OFF + PGTABLE_SIZE); + dcache_enable(); + + while (1) { + while (size) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + sdram_clear_mem(start_addr, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + + bank++; + if (bank >= CONFIG_NR_DRAM_BANKS) + break; + + start_addr = bd->bi_dram[bank].start; + size = bd->bi_dram[bank].size; + } + + dcache_disable(); + icache_disable(); + + printf("SDRAM-ECC: Initialized success with %d ms\n", + (unsigned int)get_timer(start)); +} + +static void sdram_size_check(bd_t *bd) +{ + phys_size_t total_ram_check = 0; + phys_size_t ram_check = 0; + phys_addr_t start = 0; + int bank; + + /* Sanity check ensure correct SDRAM size specified */ + debug("DDR: Running SDRAM size sanity check\n"); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start = bd->bi_dram[bank].start; + while (ram_check < bd->bi_dram[bank].size) { + ram_check += get_ram_size((void *)(start + ram_check), + (phys_size_t)SZ_1G); + } + total_ram_check += ram_check; + ram_check = 0; + } + + /* If the ram_size is 2GB smaller, we can assume the IO space is + * not mapped in. gd->ram_size is the actual size of the dram + * not the accessible size. + */ + if (total_ram_check != gd->ram_size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + + debug("DDR: SDRAM size check passed!\n"); +} + /** * sdram_mmr_init_full() - Function to initialize SDRAM MMR * @@ -144,6 +250,8 @@ int sdram_mmr_init_full(unsigned int unused) u32 update_value, io48_value, ddrioctl; u32 i; int ret; + phys_size_t hw_size; + bd_t bd = {0}; /* Enable access to DDR from CPU master */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG), @@ -335,9 +443,22 @@ int sdram_mmr_init_full(unsigned int unused) unsigned long long size = sdram_calculate_size(); /* If the size is invalid, use default Config size */ if (size <= 0) - gd->ram_size = PHYS_SDRAM_1_SIZE; + hw_size = PHYS_SDRAM_1_SIZE; else - gd->ram_size = size; + hw_size = size; + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + puts("DDR: Failed to decode memory node\n"); + return -1; + } + + if (gd->ram_size != hw_size) + printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n"); + + printf("DDR: %lld MiB\n", gd->ram_size >> 20); /* Enable or disable the SDRAM ECC */ if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { @@ -351,6 +472,15 @@ int sdram_mmr_init_full(unsigned int unused) setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + writel(DDR_HMC_ERRINTEN_INTMASK, + SOCFPGA_SDR_ADDRESS + ERRINTENS); + + /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + + /* Initialize memory content if not from warm reset */ + if (!cpu_has_been_warmreset()) + sdram_init_ecc_bits(&bd); } else { clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | @@ -361,6 +491,8 @@ int sdram_mmr_init_full(unsigned int unused) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } + sdram_size_check(&bd); + debug("DDR: HMC init success\n"); return 0; } diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 5e7a943b68..0e4526288e 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3705,12 +3705,19 @@ static void initialize_tracking(void) &sdr_reg_file->trk_rfsh); } -int sdram_calibration_full(void) +int sdram_calibration_full(struct socfpga_sdr *sdr) { struct param_type my_param; struct gbl_type my_gbl; u32 pass; + /* + * For size reasons, this file uses hard coded addresses. + * Check if we are called with the correct address. + */ + if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) + return -ENODEV; + memset(&my_param, 0, sizeof(my_param)); memset(&my_gbl, 0, sizeof(my_gbl)); diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index a5760b03a5..d7f6935201 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -223,4 +223,39 @@ struct socfpga_data_mgr { u32 mem_t_add; u32 t_rl_add; }; + +/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */ +struct socfpga_sdr { + /* SDR_PHYGRP_SCCGRP_ADDRESS */ + u8 _align1[0xe00]; + /* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */ + struct socfpga_sdr_scc_mgr sdr_scc_mgr; + u8 _align2[0x1bc]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS */ + struct socfpga_phy_mgr_cmd phy_mgr_cmd; + u8 _align3[0x2c]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */ + struct socfpga_phy_mgr_cfg phy_mgr_cfg; + u8 _align4[0xfa0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS */ + u8 rwmgr_grp[0x800]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */ + struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs; + u8 _align5[0x3f0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */ + struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs; + u8 _align6[0x13f0]; + /* SDR_PHYGRP_DATAMGRGRP_ADDRESS */ + struct socfpga_data_mgr data_mgr; + u8 _align7[0x7f0]; + /* SDR_PHYGRP_REGFILEGRP_ADDRESS */ + struct socfpga_sdr_reg_file sdr_reg_file; + u8 _align8[0x7c8]; + /* SDR_CTRLGRP_ADDRESS */ + struct socfpga_sdr_ctrl sdr_ctrl; + u8 _align9[0xea4]; +}; + +int sdram_calibration_full(struct socfpga_sdr *sdr); + #endif /* _SEQUENCER_H_ */ diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 4d264c985d..4268628f5e 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -17,6 +17,7 @@ static void getvar_downloadsize(char *var_parameter, char *response); static void getvar_serialno(char *var_parameter, char *response); static void getvar_version_baseband(char *var_parameter, char *response); static void getvar_product(char *var_parameter, char *response); +static void getvar_platform(char *var_parameter, char *response); static void getvar_current_slot(char *var_parameter, char *response); static void getvar_slot_suffixes(char *var_parameter, char *response); static void getvar_has_slot(char *var_parameter, char *response); @@ -56,13 +57,16 @@ static const struct { .variable = "product", .dispatch = getvar_product }, { + .variable = "platform", + .dispatch = getvar_platform + }, { .variable = "current-slot", .dispatch = getvar_current_slot }, { .variable = "slot-suffixes", .dispatch = getvar_slot_suffixes }, { - .variable = "has_slot", + .variable = "has-slot", .dispatch = getvar_has_slot #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) }, { @@ -117,6 +121,16 @@ static void getvar_product(char *var_parameter, char *response) fastboot_fail("Board not set", response); } +static void getvar_platform(char *var_parameter, char *response) +{ + const char *p = env_get("platform"); + + if (p) + fastboot_okay(p, response); + else + fastboot_fail("platform not set", response); +} + static void getvar_current_slot(char *var_parameter, char *response) { /* A/B not implemented, for now always return _a */ diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 4c1c7fd2cd..90ca81da9b 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -31,13 +31,13 @@ static int part_get_info_by_name_or_alias(struct blk_desc *dev_desc, ret = part_get_info_by_name(dev_desc, name, info); if (ret < 0) { - /* strlen("fastboot_partition_alias_") + 32(part_name) + 1 */ - char env_alias_name[25 + 32 + 1]; + /* strlen("fastboot_partition_alias_") + PART_NAME_LEN + 1 */ + char env_alias_name[25 + PART_NAME_LEN + 1]; char *aliased_part_name; /* check for alias */ strcpy(env_alias_name, "fastboot_partition_alias_"); - strncat(env_alias_name, name, 32); + strncat(env_alias_name, name, PART_NAME_LEN); aliased_part_name = env_get(env_alias_name); if (aliased_part_name != NULL) ret = part_get_info_by_name(dev_desc, @@ -308,8 +308,8 @@ int fastboot_mmc_get_part_info(char *part_name, struct blk_desc **dev_desc, fastboot_fail("block device not found", response); return -ENOENT; } - if (!part_name) { - fastboot_fail("partition not found", response); + if (!part_name || !strcmp(part_name, "")) { + fastboot_fail("partition not given", response); return -ENOENT; } diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 499310d0c0..069c63ba45 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -408,6 +408,8 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, if (bstype != BIT_PARTIAL) zynq_slcr_devcfg_enable(); + puts("INFO:post config was not run, please run manually if needed\n"); + return FPGA_SUCCESS; } @@ -421,7 +423,8 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, loff_t blocksize, actread; loff_t pos = 0; int fstype; - char *interface, *dev_part, *filename; + char *interface, *dev_part; + const char *filename; blocksize = fsinfo->blocksize; interface = fsinfo->interface; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d6e677fba8..0e645f58be 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -128,6 +128,8 @@ config JZ4780_EFUSE config MXC_OCOTP bool "Enable MXC OCOTP Driver" + depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610 + default y help If you say Y here, you will get support for the One Time Programmable memory pages that are stored on the some diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 04a4e7716f..c34dd5d187 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -222,6 +222,16 @@ config MMC_DW_SOCFPGA Synopsys DesignWare Memory Card Interface driver. Select this option for platforms based on Altera SOCFPGA. +config MMC_DW_SNPS + bool "Extensions for DW Memory Card Interface used in Synopsys ARC devboards" + depends on MMC_DW + depends on DM_MMC + depends on OF_CONTROL + depends on CLK + help + This selects support for Synopsys DesignWare Memory Card Interface driver + extensions used in various Synopsys ARC devboards. + config MMC_MESON_GX bool "Meson GX EMMC controller support" depends on DM_MMC && BLK && ARCH_MESON diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 7892c468f0..0076fc393b 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o +obj-$(CONFIG_MMC_DW_SNPS) += snps_dw_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c new file mode 100644 index 0000000000..5a413f0ec7 --- /dev/null +++ b/drivers/mmc/snps_dw_mmc.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Synopsys DesignWare Multimedia Card Interface driver + * extensions used in various Synopsys ARC devboards. + * + * Copyright (C) 2019 Synopsys + * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/libfdt.h> +#include <linux/err.h> +#include <malloc.h> + +#define CLOCK_MIN 400000 /* 400 kHz */ +#define FIFO_MIN 8 +#define FIFO_MAX 4096 + +struct snps_dwmci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct snps_dwmci_priv_data { + struct dwmci_host host; + u32 f_max; +}; + +static int snps_dwmmc_clk_setup(struct udevice *dev) +{ + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + + struct clk clk_ciu, clk_biu; + int ret; + + ret = clk_get_by_name(dev, "ciu", &clk_ciu); + if (ret) + goto clk_err; + + ret = clk_enable(&clk_ciu); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) + goto clk_err_ciu; + + host->bus_hz = clk_get_rate(&clk_ciu); + if (host->bus_hz < CLOCK_MIN) { + ret = -EINVAL; + goto clk_err_ciu_dis; + } + + ret = clk_get_by_name(dev, "biu", &clk_biu); + if (ret) + goto clk_err_ciu_dis; + + ret = clk_enable(&clk_biu); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) + goto clk_err_biu; + + return 0; + +clk_err_biu: + clk_free(&clk_biu); +clk_err_ciu_dis: + clk_disable(&clk_ciu); +clk_err_ciu: + clk_free(&clk_ciu); +clk_err: + dev_err(dev, "failed to setup clocks, ret %d\n", ret); + + return ret; +} + +static int snps_dwmmc_ofdata_to_platdata(struct udevice *dev) +{ + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + u32 fifo_depth; + int ret; + + host->ioaddr = devfdt_get_addr_ptr(dev); + + /* + * If fifo-depth is unset don't set fifoth_val - we will try to + * auto detect it. + */ + ret = dev_read_u32(dev, "fifo-depth", &fifo_depth); + if (!ret) { + if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX) + return -EINVAL; + + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(fifo_depth / 2 - 1) | + TX_WMARK(fifo_depth / 2); + } + + host->buswidth = dev_read_u32_default(dev, "bus-width", 4); + if (host->buswidth != 1 && host->buswidth != 4 && host->buswidth != 8) + return -EINVAL; + + /* + * If max-frequency is unset don't set priv->f_max - we will use + * host->bus_hz in probe() instead. + */ + ret = dev_read_u32(dev, "max-frequency", &priv->f_max); + if (!ret && priv->f_max < CLOCK_MIN) + return -EINVAL; + + host->fifo_mode = dev_read_bool(dev, "fifo-mode"); + host->name = dev->name; + host->dev_index = 0; + host->priv = priv; + + return 0; +} + +int snps_dwmmc_getcd(struct udevice *dev) +{ + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + +struct dm_mmc_ops snps_dwmci_dm_ops; + +static int snps_dwmmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_BLK + struct snps_dwmci_plat *plat = dev_get_platdata(dev); +#endif + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + unsigned int clock_max; + int ret; + + /* Extend generic 'dm_dwmci_ops' with our 'getcd' implementation */ + memcpy(&snps_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops)); + snps_dwmci_dm_ops.get_cd = snps_dwmmc_getcd; + + ret = snps_dwmmc_clk_setup(dev); + if (ret) + return ret; + + if (!priv->f_max) + clock_max = host->bus_hz; + else + clock_max = min_t(unsigned int, host->bus_hz, priv->f_max); + +#ifdef CONFIG_BLK + dwmci_setup_cfg(&plat->cfg, host, clock_max, CLOCK_MIN); + host->mmc = &plat->mmc; +#else + ret = add_dwmci(host, clock_max, CLOCK_MIN); + if (ret) + return ret; +#endif + host->mmc->priv = &priv->host; + upriv->mmc = host->mmc; + host->mmc->dev = dev; + + return dwmci_probe(dev); +} + +static int snps_dwmmc_bind(struct udevice *dev) +{ +#ifdef CONFIG_BLK + struct snps_dwmci_plat *plat = dev_get_platdata(dev); + int ret; + + ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; +#endif + + return 0; +} + +static const struct udevice_id snps_dwmmc_ids[] = { + { .compatible = "snps,dw-mshc" }, + { } +}; + +U_BOOT_DRIVER(snps_dwmmc_drv) = { + .name = "snps_dw_mmc", + .id = UCLASS_MMC, + .of_match = snps_dwmmc_ids, + .ofdata_to_platdata = snps_dwmmc_ofdata_to_platdata, + .ops = &snps_dwmci_dm_ops, + .bind = snps_dwmmc_bind, + .probe = snps_dwmmc_probe, + .priv_auto_alloc_size = sizeof(struct snps_dwmci_priv_data), + .platdata_auto_alloc_size = sizeof(struct snps_dwmci_plat), +}; diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 019deda094..63ae828768 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -10,6 +10,7 @@ #include <linux/bitops.h> #include <linux/mtd/rawnand.h> #include <linux/types.h> +#include <reset.h> #define DEVICE_RESET 0x0 #define DEVICE_RESET__BANK(bank) BIT(bank) @@ -315,6 +316,7 @@ struct denali_nand_info { void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, int page, int write); + struct reset_ctl_bulk resets; }; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index d384b974df..0ce81324b9 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -131,15 +131,30 @@ static int denali_dt_probe(struct udevice *dev) denali->clk_x_rate = 200000000; } + ret = reset_get_bulk(dev, &denali->resets); + if (ret) + dev_warn(dev, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&denali->resets); + return denali_init(denali); } +static int denali_dt_remove(struct udevice *dev) +{ + struct denali_nand_info *denali = dev_get_priv(dev); + + return reset_release_bulk(&denali->resets); +} + U_BOOT_DRIVER(denali_nand_dt) = { .name = "denali-nand-dt", .id = UCLASS_MISC, .of_match = denali_nand_dt_ids, .probe = denali_dt_probe, .priv_auto_alloc_size = sizeof(struct denali_nand_info), + .remove = denali_dt_remove, + .flags = DM_FLAG_OS_PREPARE, }; void board_nand_init(void) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 77d0b3a01f..d0e5426a99 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -190,7 +190,7 @@ config FEC_MXC_MDIO_BASE config FEC_MXC bool "FEC Ethernet controller" - depends on MX5 || MX6 || MX7 || IMX8 + depends on MX5 || MX6 || MX7 || IMX8 || VF610 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 84f010d805..a672250e16 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1491,6 +1491,7 @@ static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx6ul-fec" }, { .compatible = "fsl,imx53-fec" }, { .compatible = "fsl,imx7d-fec" }, + { .compatible = "fsl,mvf600-fec" }, { } }; diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7..98bd7a5823 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -14,12 +14,14 @@ #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <common.h> +#include <clk.h> #include <dm.h> #include <fdt_support.h> #include <linux/err.h> #include <malloc.h> #include <miiphy.h> #include <net.h> +#include <reset.h> #include <dt-bindings/pinctrl/sun4i-a10.h> #ifdef CONFIG_DM_GPIO #include <asm-generic/gpio.h> @@ -135,6 +137,8 @@ struct emac_eth_dev { phys_addr_t sysctl_reg; struct phy_device *phydev; struct mii_dev *bus; + struct clk tx_clk; + struct reset_ctl tx_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -285,10 +289,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, int ret; u32 reg; - reg = readl(priv->sysctl_reg + 0x30); + if (priv->variant == R40_GMAC) { + /* Select RGMII for R40 */ + reg = readl(priv->sysctl_reg + 0x164); + reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII | + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY); - if (priv->variant == R40_GMAC) + writel(reg, priv->sysctl_reg + 0x164); return 0; + } + + reg = readl(priv->sysctl_reg + 0x30); if (priv->variant == H3_EMAC) { ret = sun8i_emac_set_syscon_ephy(priv, ®); @@ -639,9 +651,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev) return _sun8i_write_hwaddr(priv, pdata->enetaddr); } -static void sun8i_emac_board_setup(struct emac_eth_dev *priv) +static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int ret; + + ret = clk_enable(&priv->tx_clk); + if (ret) { + dev_err(dev, "failed to enable TX clock\n"); + return ret; + } + + if (reset_valid(&priv->tx_rst)) { + ret = reset_deassert(&priv->tx_rst); + if (ret) { + dev_err(dev, "failed to deassert TX reset\n"); + goto err_tx_clk; + } + } if (priv->variant == H3_EMAC) { /* Only H3/H5 have clock controls for internal EPHY */ @@ -656,26 +683,11 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) } } - if (priv->variant == R40_GMAC) { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC)); + return 0; - /* Select RGMII for R40 */ - setbits_le32(&ccm->gmac_clk_cfg, - CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | - CCM_GMAC_CTRL_GPIT_RGMII); - setbits_le32(&ccm->gmac_clk_cfg, - CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); - } else { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); - - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - } +err_tx_clk: + clk_disable(&priv->tx_clk); + return ret; } #if defined(CONFIG_DM_GPIO) @@ -802,10 +814,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev) struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); + int ret; priv->mac_reg = (void *)pdata->iobase; - sun8i_emac_board_setup(priv); + ret = sun8i_emac_board_setup(priv); + if (ret) + return ret; + sun8i_emac_set_syscon(sun8i_pdata, priv); sun8i_mdio_init(dev->name, dev); @@ -834,8 +850,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) int offset = 0; #ifdef CONFIG_DM_GPIO int reset_flags = GPIOD_IS_OUT; - int ret = 0; #endif + int ret; pdata->iobase = devfdt_get_addr(dev); if (pdata->iobase == FDT_ADDR_T_NONE) { @@ -850,25 +866,35 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } - if (priv->variant != R40_GMAC) { - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); - if (offset < 0) { - debug("%s: cannot find syscon node\n", __func__); - return -EINVAL; - } - reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); - if (!reg) { - debug("%s: cannot find reg property in syscon node\n", - __func__); - return -EINVAL; - } - priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, - offset, reg); - if (priv->sysctl_reg == FDT_ADDR_T_NONE) { - debug("%s: Cannot find syscon base address\n", - __func__); - return -EINVAL; - } + ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk); + if (ret) { + dev_err(dev, "failed to get TX clock\n"); + return ret; + } + + ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get TX reset\n"); + return ret; + } + + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); + if (offset < 0) { + debug("%s: cannot find syscon node\n", __func__); + return -EINVAL; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); + if (!reg) { + debug("%s: cannot find reg property in syscon node\n", + __func__); + return -EINVAL; + } + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", __func__); + return -EINVAL; } pdata->phy_interface = -1; diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 8dbd3c50c1..9a5f7fd3c7 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> #include <linux/err.h> #include <malloc.h> @@ -157,6 +158,7 @@ struct sunxi_sramc_regs { struct emac_eth_dev { struct emac_regs *regs; + struct clk clk; struct mii_dev *bus; struct phy_device *phydev; int link_printed; @@ -500,14 +502,12 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet, return 0; } -static void sunxi_emac_board_setup(struct emac_eth_dev *priv) +static int sunxi_emac_board_setup(struct emac_eth_dev *priv) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; struct sunxi_sramc_regs *sram = (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; struct emac_regs *regs = priv->regs; - int pin; + int pin, ret; /* Map SRAM to EMAC */ setbits_le32(&sram->ctrl1, 0x5 << 2); @@ -517,10 +517,16 @@ static void sunxi_emac_board_setup(struct emac_eth_dev *priv) sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC); /* Set up clock gating */ - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); + ret = clk_enable(&priv->clk); + if (ret) { + dev_err(dev, "failed to enable emac clock\n"); + return ret; + } /* Set MII clock */ clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); + + return 0; } static int sunxi_emac_eth_start(struct udevice *dev) @@ -557,9 +563,19 @@ static int sunxi_emac_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct emac_eth_dev *priv = dev_get_priv(dev); + int ret; priv->regs = (struct emac_regs *)pdata->iobase; - sunxi_emac_board_setup(priv); + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) { + dev_err(dev, "failed to get emac clock\n"); + return ret; + } + + ret = sunxi_emac_board_setup(priv); + if (ret) + return ret; return sunxi_emac_init_phy(priv, dev); } diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 3bd0093b7a..033efb8195 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -261,45 +261,6 @@ static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr, ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); } -static int phy_detection(struct udevice *dev) -{ - int i; - u16 phyreg = 0; - struct zynq_gem_priv *priv = dev->priv; - - if (priv->phyaddr != -1) { - phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); - if ((phyreg != 0xFFFF) && - ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { - /* Found a valid PHY address */ - debug("Default phy address %d is valid\n", - priv->phyaddr); - return 0; - } else { - debug("PHY address is not setup correctly %d\n", - priv->phyaddr); - priv->phyaddr = -1; - } - } - - debug("detecting phy address\n"); - if (priv->phyaddr == -1) { - /* detect the PHY address */ - for (i = 31; i >= 0; i--) { - phyread(priv, i, PHY_DETECT_REG, &phyreg); - if ((phyreg != 0xFFFF) && - ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { - /* Found a valid PHY address */ - priv->phyaddr = i; - debug("Found valid phy address, %d\n", i); - return 0; - } - } - } - printf("PHY is not detected\n"); - return -1; -} - static int zynq_gem_setup_mac(struct udevice *dev) { u32 i, macaddrlow, macaddrhigh; @@ -345,28 +306,20 @@ static int zynq_phy_init(struct udevice *dev) /* Enable only MDIO bus */ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); - if ((priv->interface != PHY_INTERFACE_MODE_SGMII) && - (priv->interface != PHY_INTERFACE_MODE_GMII)) { - ret = phy_detection(dev); - if (ret) { - printf("GEM PHY init failed\n"); - return ret; - } - } - priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); if (!priv->phydev) return -ENODEV; - priv->phydev->supported &= supported | ADVERTISED_Pause | - ADVERTISED_Asym_Pause; if (priv->max_speed) { ret = phy_set_supported(priv->phydev, priv->max_speed); if (ret) return ret; } + priv->phydev->supported &= supported | ADVERTISED_Pause | + ADVERTISED_Asym_Pause; + priv->phydev->advertising = priv->phydev->supported; priv->phydev->node = priv->phy_of_node; diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 8e98b4b627..6f1119036d 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -37,7 +37,8 @@ #define MAX_PHYS 2 -#define PLL_LOCK_TIME_US 100 +/* max 100 us for PLL lock and 100 us for PHY init */ +#define PLL_INIT_TIME_US 200 #define PLL_PWR_DOWN_TIME_US 5 #define PLL_FVCO 2880 /* in MHz */ #define PLL_INFF_MIN_RATE 19200000 /* in Hz */ @@ -51,17 +52,17 @@ struct pll_params { struct stm32_usbphyc { fdt_addr_t base; struct clk clk; + struct udevice *vdda1v1; + struct udevice *vdda1v8; struct stm32_usbphyc_phy { struct udevice *vdd; - struct udevice *vdda1v1; - struct udevice *vdda1v8; - int index; bool init; bool powered; } phys[MAX_PHYS]; }; -void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params) +static void stm32_usbphyc_get_pll_params(u32 clk_rate, + struct pll_params *pll_params) { unsigned long long fvco, ndiv, frac; @@ -154,6 +155,18 @@ static int stm32_usbphyc_phy_init(struct phy *phy) if (pllen && stm32_usbphyc_is_init(usbphyc)) goto initialized; + if (usbphyc->vdda1v1) { + ret = regulator_set_enable(usbphyc->vdda1v1, true); + if (ret) + return ret; + } + + if (usbphyc->vdda1v8) { + ret = regulator_set_enable(usbphyc->vdda1v8, true); + if (ret) + return ret; + } + if (pllen) { clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN); udelay(PLL_PWR_DOWN_TIME_US); @@ -165,11 +178,8 @@ static int stm32_usbphyc_phy_init(struct phy *phy) setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN); - /* - * We must wait PLL_LOCK_TIME_US before checking that PLLEN - * bit is still set - */ - udelay(PLL_LOCK_TIME_US); + /* We must wait PLL_INIT_TIME_US before using PHY */ + udelay(PLL_INIT_TIME_US); if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)) return -EIO; @@ -184,6 +194,7 @@ static int stm32_usbphyc_phy_exit(struct phy *phy) { struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev); struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; + int ret; pr_debug("%s phy ID = %lu\n", __func__, phy->id); usbphyc_phy->init = false; @@ -203,6 +214,18 @@ static int stm32_usbphyc_phy_exit(struct phy *phy) if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN) return -EIO; + if (usbphyc->vdda1v1) { + ret = regulator_set_enable(usbphyc->vdda1v1, false); + if (ret) + return ret; + } + + if (usbphyc->vdda1v8) { + ret = regulator_set_enable(usbphyc->vdda1v8, false); + if (ret) + return ret; + } + return 0; } @@ -213,17 +236,6 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy) int ret; pr_debug("%s phy ID = %lu\n", __func__, phy->id); - if (usbphyc_phy->vdda1v1) { - ret = regulator_set_enable(usbphyc_phy->vdda1v1, true); - if (ret) - return ret; - } - - if (usbphyc_phy->vdda1v8) { - ret = regulator_set_enable(usbphyc_phy->vdda1v8, true); - if (ret) - return ret; - } if (usbphyc_phy->vdd) { ret = regulator_set_enable(usbphyc_phy->vdd, true); if (ret) @@ -247,18 +259,6 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) if (stm32_usbphyc_is_powered(usbphyc)) return 0; - if (usbphyc_phy->vdda1v1) { - ret = regulator_set_enable(usbphyc_phy->vdda1v1, false); - if (ret) - return ret; - } - - if (usbphyc_phy->vdda1v8) { - ret = regulator_set_enable(usbphyc_phy->vdda1v8, false); - if (ret) - return ret; - } - if (usbphyc_phy->vdd) { ret = regulator_set_enable(usbphyc_phy->vdd, false); if (ret) @@ -298,19 +298,20 @@ static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node, static int stm32_usbphyc_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { - if (args->args_count > 1) { - pr_debug("%s: invalid args_count: %d\n", __func__, - args->args_count); - return -EINVAL; - } + if (args->args_count < 1) + return -ENODEV; if (args->args[0] >= MAX_PHYS) return -ENODEV; - if (args->args_count) - phy->id = args->args[0]; - else - phy->id = 0; + phy->id = args->args[0]; + + if ((phy->id == 0 && args->args_count != 1) || + (phy->id == 1 && args->args_count != 2)) { + dev_err(dev, "invalid number of cells for phy port%ld\n", + phy->id); + return -EINVAL; + } return 0; } @@ -351,6 +352,21 @@ static int stm32_usbphyc_probe(struct udevice *dev) reset_deassert(&reset); } + /* get usbphyc regulator */ + ret = device_get_supply_regulator(dev, "vdda1v1-supply", + &usbphyc->vdda1v1); + if (ret) { + dev_err(dev, "Can't get vdda1v1-supply regulator\n"); + return ret; + } + + ret = device_get_supply_regulator(dev, "vdda1v8-supply", + &usbphyc->vdda1v8); + if (ret) { + dev_err(dev, "Can't get vdda1v8-supply regulator\n"); + return ret; + } + /* * parse all PHY subnodes in order to populate regulator associated * to each PHY port @@ -359,7 +375,6 @@ static int stm32_usbphyc_probe(struct udevice *dev) for (i = 0; i < MAX_PHYS; i++) { struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i; - usbphyc_phy->index = i; usbphyc_phy->init = false; usbphyc_phy->powered = false; ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply", @@ -367,16 +382,6 @@ static int stm32_usbphyc_probe(struct udevice *dev) if (ret) return ret; - ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v1-supply", - &usbphyc_phy->vdda1v1); - if (ret) - return ret; - - ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v8-supply", - &usbphyc_phy->vdda1v8); - if (ret) - return ret; - node = dev_read_next_subnode(node); } diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index b2acfcd2ec..cb8312619f 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -24,9 +24,39 @@ #define NR_BANKS 8 struct socfpga_reset_data { - void __iomem *membase; + void __iomem *modrst_base; }; +/* + * For compatibility with Kernels that don't support peripheral reset, this + * driver can keep the old behaviour of not asserting peripheral reset before + * starting the OS and deasserting all peripheral resets (enabling all + * peripherals). + * + * For that, the reset driver checks the environment variable + * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not + * reset again once taken out of reset and all peripherals in 'permodrst' are + * taken out of reset before booting into the OS. + * Note that this should be required for gen5 systems only that are running + * Linux kernels without proper peripheral reset support for all drivers used. + */ +static bool socfpga_reset_keep_enabled(void) +{ +#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT) + const char *env_str; + long val; + + env_str = env_get("socfpga_legacy_reset_compat"); + if (env_str) { + val = simple_strtol(env_str, NULL, 0); + if (val == 1) + return true; + } +#endif + + return false; +} + static int socfpga_reset_assert(struct reset_ctl *reset_ctl) { struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); @@ -35,7 +65,7 @@ static int socfpga_reset_assert(struct reset_ctl *reset_ctl) int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE); - setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); return 0; } @@ -47,7 +77,7 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE); - clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); return 0; } @@ -80,11 +110,24 @@ static int socfpga_reset_probe(struct udevice *dev) const void *blob = gd->fdt_blob; int node = dev_of_offset(dev); u32 modrst_offset; + void __iomem *membase; - data->membase = devfdt_get_addr_ptr(dev); + membase = devfdt_get_addr_ptr(dev); modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10); - data->membase += modrst_offset; + data->modrst_base = membase + modrst_offset; + + return 0; +} + +static int socfpga_reset_remove(struct udevice *dev) +{ + struct socfpga_reset_data *data = dev_get_priv(dev); + + if (socfpga_reset_keep_enabled()) { + puts("Deasserting all peripheral resets\n"); + writel(0, data->modrst_base + 4); + } return 0; } @@ -101,4 +144,6 @@ U_BOOT_DRIVER(socfpga_reset) = { .probe = socfpga_reset_probe, .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), .ops = &socfpga_reset_ops, + .remove = socfpga_reset_remove, + .flags = DM_FLAG_OS_PREPARE, }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a700f240ad..fb794adae7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -259,6 +259,13 @@ config TEGRA210_QSPI be used to access SPI chips on platforms embedding this NVIDIA Tegra210 IP core. +config TI_QSPI + bool "TI QSPI driver" + imply TI_EDMA3 + help + Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. + This driver support spi flash single, quad and memory reads. + config XILINX_SPI bool "Xilinx SPI driver" help @@ -346,12 +353,6 @@ config SH_QSPI Enable the Renesas Quad SPI controller driver. This driver can be used on Renesas SoCs. -config TI_QSPI - bool "TI QSPI driver" - help - Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. - This driver support spi flash single, quad and memory reads. - config KIRKWOOD_SPI bool "Marvell Kirkwood SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 01907bef79..8be9a4baa2 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -9,6 +9,7 @@ obj-y += spi-uclass.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SPI_MEM) += spi-mem.o +obj-$(CONFIG_TI_QSPI) += ti_qspi.o else obj-y += spi.o obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o @@ -56,7 +57,6 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o -obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index efdb178450..41c87004d8 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -8,6 +8,7 @@ #include <dm.h> #include <fdtdec.h> #include <malloc.h> +#include <reset.h> #include <spi.h> #include <linux/errno.h> #include "cadence_qspi.h" @@ -154,10 +155,17 @@ static int cadence_spi_probe(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + int ret; priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; + ret = reset_get_bulk(bus, &priv->resets); + if (ret) + dev_warn(bus, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&priv->resets); + if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(plat); priv->qspi_is_init = 1; @@ -166,6 +174,13 @@ static int cadence_spi_probe(struct udevice *bus) return 0; } +static int cadence_spi_remove(struct udevice *dev) +{ + struct cadence_spi_priv *priv = dev_get_priv(dev); + + return reset_release_bulk(&priv->resets); +} + static int cadence_spi_set_mode(struct udevice *bus, uint mode) { struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -342,4 +357,6 @@ U_BOOT_DRIVER(cadence_spi) = { .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata), .priv_auto_alloc_size = sizeof(struct cadence_spi_priv), .probe = cadence_spi_probe, + .remove = cadence_spi_remove, + .flags = DM_FLAG_OS_PREPARE, }; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index b491407130..20cceca239 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -7,6 +7,8 @@ #ifndef __CADENCE_QSPI_H__ #define __CADENCE_QSPI_H__ +#include <reset.h> + #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) #define CQSPI_NO_DECODER_MAX_CS 4 @@ -42,6 +44,8 @@ struct cadence_spi_priv { unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; unsigned int previous_hz; + + struct reset_ctl_bulk resets; }; /* Functions call declaration */ diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 2dcce66de0..77fa17ee8a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -10,6 +10,7 @@ #include <asm/arch/omap.h> #include <malloc.h> #include <spi.h> +#include <spi-mem.h> #include <dm.h> #include <asm/gpio.h> #include <asm/omap_gpio.h> @@ -40,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_INVAL (4 << 16) #define QSPI_RD_QUAD (7 << 16) /* device control */ -#define QSPI_DD(m, n) (m << (3 + n*8)) #define QSPI_CKPHA(n) (1 << (2 + n*8)) #define QSPI_CSPOL(n) (1 << (1 + n*8)) #define QSPI_CKPOL(n) (1 << (n*8)) @@ -52,22 +52,12 @@ DECLARE_GLOBAL_DATA_PTR; #define MM_SWITCH 0x01 #define MEM_CS(cs) ((cs + 1) << 8) #define MEM_CS_UNSELECT 0xfffff8ff -#define MMAP_START_ADDR_DRA 0x5c000000 -#define MMAP_START_ADDR_AM43x 0x30000000 -#define CORE_CTRL_IO 0x4a002558 - -#define QSPI_CMD_READ (0x3 << 0) -#define QSPI_CMD_READ_DUAL (0x6b << 0) -#define QSPI_CMD_READ_QUAD (0x6c << 0) -#define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8) -#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) -#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) + #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) #define QSPI_SETUP0_READ_DUAL (0x1 << 12) #define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x12 << 16) -#define QSPI_NUM_DUMMY_BITS (0x0 << 24) +#define QSPI_SETUP0_ADDR_SHIFT (8) +#define QSPI_SETUP0_DBITS_SHIFT (10) /* ti qspi register set */ struct ti_qspi_regs { @@ -98,13 +88,10 @@ struct ti_qspi_regs { /* ti qspi priv */ struct ti_qspi_priv { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#else void *memory_map; + size_t mmap_size; uint max_hz; u32 num_cs; -#endif struct ti_qspi_regs *base; void *ctrl_mod_mmap; ulong fclk; @@ -113,8 +100,9 @@ struct ti_qspi_priv { u32 dc; }; -static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) +static int ti_qspi_set_speed(struct udevice *bus, uint hz) { + struct ti_qspi_priv *priv = dev_get_priv(bus); uint clk_div; if (!hz) @@ -133,6 +121,8 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) &priv->base->clk_ctrl); /* enable SCLK and program the clk divider */ writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); + + return 0; } static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) @@ -142,38 +132,6 @@ static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) readl(&priv->base->cmd); } -static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) -{ - priv->dc = 0; - if (mode & SPI_CPHA) - priv->dc |= QSPI_CKPHA(0); - if (mode & SPI_CPOL) - priv->dc |= QSPI_CKPOL(0); - if (mode & SPI_CS_HIGH) - priv->dc |= QSPI_CSPOL(0); - - return 0; -} - -static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs) -{ - writel(priv->dc, &priv->base->dc); - writel(0, &priv->base->cmd); - writel(0, &priv->base->data); - - priv->dc <<= cs * 8; - writel(priv->dc, &priv->base->dc); - - return 0; -} - -static void __ti_qspi_release_bus(struct ti_qspi_priv *priv) -{ - writel(0, &priv->base->dc); - writel(0, &priv->base->cmd); - writel(0, &priv->base->data); -} - static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) { u32 val; @@ -186,27 +144,25 @@ static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) writel(val, ctrl_mod_mmap); } -static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, - const void *dout, void *din, unsigned long flags, - u32 cs) +static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; uint words = bitlen >> 3; /* fixed 8-bit word length */ const uchar *txp = dout; uchar *rxp = din; uint status; int timeout; + unsigned int cs = slave->cs; - /* Setup mmap flags */ - if (flags & SPI_XFER_MMAP) { - writel(MM_SWITCH, &priv->base->memswitch); - if (priv->ctrl_mod_mmap) - ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true); - return 0; - } else if (flags & SPI_XFER_MMAP_END) { - writel(~MM_SWITCH, &priv->base->memswitch); - if (priv->ctrl_mod_mmap) - ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false); - return 0; + bus = dev->parent; + priv = dev_get_priv(bus); + + if (cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; } if (bitlen == 0) @@ -294,9 +250,9 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, } /* TODO: control from sf layer to here through dm-spi */ -#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) -void spi_flash_copy_mmap(void *data, void *offset, size_t len) +static void ti_qspi_copy_mmap(void *data, void *offset, size_t len) { +#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) unsigned int addr = (unsigned int) (data); unsigned int edma_slot_num = 1; @@ -311,187 +267,85 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len) /* disable edma3 clocks */ disable_edma3_clocks(); - - *((unsigned int *)offset) += len; -} -#endif - -#ifndef CONFIG_DM_SPI - -static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) -{ - return container_of(slave, struct ti_qspi_priv, slave); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* CS handled in xfer */ - return; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - ti_qspi_cs_deactivate(priv); -} - -void spi_init(void) -{ - /* nothing to do */ -} - -static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) -{ - u32 memval = 0; - -#ifdef CONFIG_QSPI_QUAD_SUPPORT - struct spi_slave *slave = &priv->slave; - memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_8_BITS | - QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS); - slave->mode |= SPI_RX_QUAD; #else - memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_NO_BITS | - QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS; + memcpy_fromio(data, offset, len); #endif - writel(memval, &priv->base->setup0); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct ti_qspi_priv *priv; - -#ifdef CONFIG_AM43XX - gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); - gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); -#endif - - priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); - if (!priv) { - printf("SPI_error: Fail to allocate ti_qspi_priv\n"); - return NULL; - } - - priv->base = (struct ti_qspi_regs *)QSPI_BASE; - priv->mode = mode; -#if defined(CONFIG_DRA7XX) - priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; - priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; - priv->fclk = QSPI_DRA7XX_FCLK; -#else - priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; - priv->fclk = QSPI_FCLK; -#endif - - ti_spi_set_speed(priv, max_hz); - -#ifdef CONFIG_TI_SPI_MMAP - ti_spi_setup_spi_register(priv); -#endif - - return &priv->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - free(priv); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); - __ti_qspi_set_mode(priv, priv->mode); - return __ti_qspi_claim_bus(priv, priv->slave.cs); -} -void spi_release_bus(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); - __ti_qspi_release_bus(priv); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n", - priv->slave.bus, priv->slave.cs, bitlen, flags); - return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); + *((unsigned int *)offset) += len; } -#else /* CONFIG_DM_SPI */ - -static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, - struct spi_slave *slave, - bool enable) +static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode, + u8 data_nbits, u8 addr_width, + u8 dummy_bytes) { - u32 memval; - u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL); - - if (!enable) { - writel(0, &priv->base->setup0); - return; - } - - memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; + u32 memval = opcode; - switch (mode) { - case SPI_RX_QUAD: - memval |= QSPI_CMD_READ_QUAD; - memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + switch (data_nbits) { + case 4: memval |= QSPI_SETUP0_READ_QUAD; - slave->mode |= SPI_RX_QUAD; break; - case SPI_RX_DUAL: - memval |= QSPI_CMD_READ_DUAL; - memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + case 2: memval |= QSPI_SETUP0_READ_DUAL; break; default: - memval |= QSPI_CMD_READ; - memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS; memval |= QSPI_SETUP0_READ_NORMAL; break; } + memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT | + dummy_bytes << QSPI_SETUP0_DBITS_SHIFT); + writel(memval, &priv->base->setup0); } - -static int ti_qspi_set_speed(struct udevice *bus, uint max_hz) +static int ti_qspi_set_mode(struct udevice *bus, uint mode) { struct ti_qspi_priv *priv = dev_get_priv(bus); - ti_spi_set_speed(priv, max_hz); + priv->dc = 0; + if (mode & SPI_CPHA) + priv->dc |= QSPI_CKPHA(0); + if (mode & SPI_CPOL) + priv->dc |= QSPI_CKPOL(0); + if (mode & SPI_CS_HIGH) + priv->dc |= QSPI_CSPOL(0); return 0; } -static int ti_qspi_set_mode(struct udevice *bus, uint mode) +static int ti_qspi_exec_mem_op(struct spi_slave *slave, + const struct spi_mem_op *op) { - struct ti_qspi_priv *priv = dev_get_priv(bus); - return __ti_qspi_set_mode(priv, mode); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = slave->dev->parent; + priv = dev_get_priv(bus); + u32 from = 0; + int ret = 0; + + /* Only optimize read path. */ + if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN || + !op->addr.nbytes || op->addr.nbytes > 4) + return -ENOTSUPP; + + /* Address exceeds MMIO window size, fall back to regular mode. */ + from = op->addr.val; + if (from + op->data.nbytes > priv->mmap_size) + return -ENOTSUPP; + + ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth, + op->addr.nbytes, op->dummy.nbytes); + + ti_qspi_copy_mmap((void *)op->data.buf.in, + (void *)priv->memory_map + from, op->data.nbytes); + + return ret; } static int ti_qspi_claim_bus(struct udevice *dev) { struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); - struct spi_slave *slave = dev_get_parent_priv(dev); struct ti_qspi_priv *priv; struct udevice *bus; @@ -503,42 +357,41 @@ static int ti_qspi_claim_bus(struct udevice *dev) return -EINVAL; } - __ti_qspi_setup_memorymap(priv, slave, true); - - return __ti_qspi_claim_bus(priv, slave_plat->cs); -} - -static int ti_qspi_release_bus(struct udevice *dev) -{ - struct spi_slave *slave = dev_get_parent_priv(dev); - struct ti_qspi_priv *priv; - struct udevice *bus; + writel(MM_SWITCH, &priv->base->memswitch); + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, + slave_plat->cs, true); - bus = dev->parent; - priv = dev_get_priv(bus); + writel(priv->dc, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data); - __ti_qspi_setup_memorymap(priv, slave, false); - __ti_qspi_release_bus(priv); + priv->dc <<= slave_plat->cs * 8; + writel(priv->dc, &priv->base->dc); return 0; } -static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int ti_qspi_release_bus(struct udevice *dev) { - struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); struct ti_qspi_priv *priv; struct udevice *bus; bus = dev->parent; priv = dev_get_priv(bus); - if (slave->cs > priv->num_cs) { - debug("invalid qspi chip select\n"); - return -EINVAL; - } + writel(~MM_SWITCH, &priv->base->memswitch); + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, + slave_plat->cs, false); - return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs); + writel(0, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data); + writel(0, &priv->base->setup0); + + return 0; } static int ti_qspi_probe(struct udevice *bus) @@ -594,12 +447,15 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus) struct ti_qspi_priv *priv = dev_get_priv(bus); const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); + fdt_addr_t mmap_addr; + fdt_addr_t mmap_size; priv->ctrl_mod_mmap = map_syscon_chipselects(bus); priv->base = map_physmem(devfdt_get_addr(bus), sizeof(struct ti_qspi_regs), MAP_NOCACHE); - priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0, - MAP_NOCACHE); + mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size); + priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE); + priv->mmap_size = mmap_size; priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { @@ -614,15 +470,9 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus) return 0; } -static int ti_qspi_child_pre_probe(struct udevice *dev) -{ - struct spi_slave *slave = dev_get_parent_priv(dev); - struct udevice *bus = dev_get_parent(dev); - struct ti_qspi_priv *priv = dev_get_priv(bus); - - slave->memory_map = priv->memory_map; - return 0; -} +static const struct spi_controller_mem_ops ti_qspi_mem_ops = { + .exec_op = ti_qspi_exec_mem_op, +}; static const struct dm_spi_ops ti_qspi_ops = { .claim_bus = ti_qspi_claim_bus, @@ -630,6 +480,7 @@ static const struct dm_spi_ops ti_qspi_ops = { .xfer = ti_qspi_xfer, .set_speed = ti_qspi_set_speed, .set_mode = ti_qspi_set_mode, + .mem_ops = &ti_qspi_mem_ops, }; static const struct udevice_id ti_qspi_ids[] = { @@ -646,6 +497,4 @@ U_BOOT_DRIVER(ti_qspi) = { .ofdata_to_platdata = ti_qspi_ofdata_to_platdata, .priv_auto_alloc_size = sizeof(struct ti_qspi_priv), .probe = ti_qspi_probe, - .child_pre_probe = ti_qspi_child_pre_probe, }; -#endif /* CONFIG_DM_SPI */ diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index da9413c066..04ea42cbcc 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -267,7 +267,7 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << TAP_DLY_BYPASS_LQSPI_RX_SHIFT); - } else if (reqhz < GQSPI_FREQ_100MHZ) { + } else if (reqhz <= GQSPI_FREQ_100MHZ) { zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << TAP_DLY_BYPASS_LQSPI_RX_SHIFT); @@ -277,7 +277,7 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) | (GQSPI_DATA_DLY_ADJ_VALUE << GQSPI_DATA_DLY_ADJ_SHIFT)); - } else if (reqhz < GQSPI_FREQ_150MHZ) { + } else if (reqhz <= GQSPI_FREQ_150MHZ) { lpbkdlyadj = readl(®s->lpbkdly); lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) | GQSPI_LPBK_DLY_ADJ_DLY_0); diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 085bfb02c5..cb48801af1 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -32,7 +32,7 @@ static int dw_apb_timer_get_count(struct udevice *dev, u64 *count) * requires the count to be incrementing. Invert the * result. */ - *count = ~readl(priv->regs + DW_APB_CURR_VAL); + *count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL)); return 0; } diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 3c7ad033e3..494ab533cc 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -18,11 +18,17 @@ */ #undef DEBUG #include <common.h> +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <malloc.h> +#include <reset.h> + #include <linux/errno.h> #include <linux/list.h> -#include <malloc.h> #include <linux/usb/ch9.h> +#include <linux/usb/otg.h> #include <linux/usb/gadget.h> #include <asm/byteorder.h> @@ -31,6 +37,8 @@ #include <asm/mach-types.h> +#include <power/regulator.h> + #include "dwc2_udc_otg_regs.h" #include "dwc2_udc_otg_priv.h" @@ -140,7 +148,6 @@ static struct usb_ep_ops dwc2_ep_ops = { /***********************************************************/ -void __iomem *regs_otg; struct dwc2_usbotg_reg *reg; bool dfu_usb_get_reset(void) @@ -223,6 +230,7 @@ static int udc_enable(struct dwc2_udc *dev) return 0; } +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) /* Register entry point for the peripheral controller driver. */ @@ -297,6 +305,54 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) udc_disable(dev); return 0; } +#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */ + +static int dwc2_gadget_start(struct usb_gadget *g, + struct usb_gadget_driver *driver) +{ + struct dwc2_udc *dev = the_controller; + + debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name"); + + if (!driver || + (driver->speed != USB_SPEED_FULL && + driver->speed != USB_SPEED_HIGH) || + !driver->bind || !driver->disconnect || !driver->setup) + return -EINVAL; + + if (!dev) + return -ENODEV; + + if (dev->driver) + return -EBUSY; + + /* first hook up the driver ... */ + dev->driver = driver; + + debug_cond(DEBUG_SETUP != 0, + "Registered gadget driver %s\n", dev->gadget.name); + return udc_enable(dev); +} + +static int dwc2_gadget_stop(struct usb_gadget *g) +{ + struct dwc2_udc *dev = the_controller; + + if (!dev) + return -ENODEV; + + if (!dev->driver) + return -EINVAL; + + dev->driver = 0; + stop_activity(dev, dev->driver); + + udc_disable(dev); + + return 0; +} + +#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */ /* * done - retire a request; caller blocked irqs @@ -400,6 +456,8 @@ static void reconfig_usbd(struct dwc2_udc *dev) unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); uint32_t dflt_gusbcfg; uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz; + u32 max_hw_ep; + int pdata_hw_ep; debug("Reseting OTG controller\n"); @@ -482,10 +540,23 @@ static void reconfig_usbd(struct dwc2_udc *dev) writel((np_tx_fifo_sz << 16) | rx_fifo_sz, ®->gnptxfsiz); - for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++) - writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) | - tx_fifo_sz << 16, ®->dieptxf[i-1]); + /* retrieve the number of IN Endpoints (excluding ep0) */ + max_hw_ep = (readl(®->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >> + GHWCFG4_NUM_IN_EPS_SHIFT; + pdata_hw_ep = dev->pdata->tx_fifo_sz_nb; + + /* tx_fifo_sz_nb should equal to number of IN Endpoint */ + if (pdata_hw_ep && max_hw_ep != pdata_hw_ep) + pr_warn("Got %d hw endpoint but %d tx-fifo-size in array !!\n", + max_hw_ep, pdata_hw_ep); + + for (i = 0; i < max_hw_ep; i++) { + if (pdata_hw_ep) + tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i]; + writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) | + tx_fifo_sz << 16, ®->dieptxf[i]); + } /* Flush the RX FIFO */ writel(RX_FIFO_FLUSH, ®->grstctl); while (readl(®->grstctl) & RX_FIFO_FLUSH) @@ -731,6 +802,10 @@ static void dwc2_fifo_flush(struct usb_ep *_ep) static const struct usb_gadget_ops dwc2_udc_ops = { /* current versions must always be self-powered */ +#if CONFIG_IS_ENABLED(DM_USB_GADGET) + .udc_start = dwc2_gadget_start, + .udc_stop = dwc2_gadget_stop, +#endif }; static struct dwc2_udc memory = { @@ -818,8 +893,6 @@ int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata) reg = (struct dwc2_usbotg_reg *)pdata->regs_otg; - /* regs_otg = (void *)pdata->regs_otg; */ - dev->gadget.is_dualspeed = 1; /* Hack only*/ dev->gadget.is_otg = 0; dev->gadget.is_a_peripheral = 0; @@ -844,12 +917,311 @@ int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata) return retval; } -int usb_gadget_handle_interrupts(int index) +int dwc2_udc_handle_interrupt(void) { u32 intr_status = readl(®->gintsts); u32 gintmsk = readl(®->gintmsk); if (intr_status & gintmsk) return dwc2_udc_irq(1, (void *)the_controller); + + return 0; +} + +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) + +int usb_gadget_handle_interrupts(int index) +{ + return dwc2_udc_handle_interrupt(); +} + +#else /* CONFIG_IS_ENABLED(DM_USB_GADGET) */ + +struct dwc2_priv_data { + struct clk_bulk clks; + struct reset_ctl_bulk resets; + struct phy *phys; + int num_phys; + struct udevice *usb33d_supply; +}; + +int dm_usb_gadget_handle_interrupts(struct udevice *dev) +{ + return dwc2_udc_handle_interrupt(); +} + +int dwc2_phy_setup(struct udevice *dev, struct phy **array, int *num_phys) +{ + int i, ret, count; + struct phy *usb_phys; + + /* Return if no phy declared */ + if (!dev_read_prop(dev, "phys", NULL)) + return 0; + + count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); + if (count <= 0) + return count; + + usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), + GFP_KERNEL); + if (!usb_phys) + return -ENOMEM; + + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + dev_err(dev, "Failed to get USB PHY%d for %s\n", + i, dev->name); + return ret; + } + } + + for (i = 0; i < count; i++) { + ret = generic_phy_init(&usb_phys[i]); + if (ret) { + dev_err(dev, "Can't init USB PHY%d for %s\n", + i, dev->name); + goto phys_init_err; + } + } + + for (i = 0; i < count; i++) { + ret = generic_phy_power_on(&usb_phys[i]); + if (ret) { + dev_err(dev, "Can't power USB PHY%d for %s\n", + i, dev->name); + goto phys_poweron_err; + } + } + + *array = usb_phys; + *num_phys = count; + return 0; + +phys_poweron_err: + for (i = count - 1; i >= 0; i--) + generic_phy_power_off(&usb_phys[i]); + + for (i = 0; i < count; i++) + generic_phy_exit(&usb_phys[i]); + + return ret; + +phys_init_err: + for (; i >= 0; i--) + generic_phy_exit(&usb_phys[i]); + + return ret; +} + +void dwc2_phy_shutdown(struct udevice *dev, struct phy *usb_phys, int num_phys) +{ + int i, ret; + + for (i = 0; i < num_phys; i++) { + if (!generic_phy_valid(&usb_phys[i])) + continue; + + ret = generic_phy_power_off(&usb_phys[i]); + ret |= generic_phy_exit(&usb_phys[i]); + if (ret) { + dev_err(dev, "Can't shutdown USB PHY%d for %s\n", + i, dev->name); + } + } +} + +static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) +{ + struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev); + int node = dev_of_offset(dev); + ulong drvdata; + void (*set_params)(struct dwc2_plat_otg_data *data); + + if (usb_get_dr_mode(node) != USB_DR_MODE_PERIPHERAL) { + dev_dbg(dev, "Invalid mode\n"); + return -ENODEV; + } + + platdata->regs_otg = dev_read_addr(dev); + + platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0); + platdata->np_tx_fifo_sz = dev_read_u32_default(dev, + "g-np-tx-fifo-size", 0); + platdata->tx_fifo_sz = dev_read_u32_default(dev, "g-tx-fifo-size", 0); + + platdata->force_b_session_valid = + dev_read_bool(dev, "u-boot,force-b-session-valid"); + + /* force platdata according compatible */ + drvdata = dev_get_driver_data(dev); + if (drvdata) { + set_params = (void *)drvdata; + set_params(platdata); + } + + return 0; +} + +static void dwc2_set_stm32mp1_hsotg_params(struct dwc2_plat_otg_data *p) +{ + p->activate_stm_id_vb_detection = true; + p->usb_gusbcfg = + 0 << 15 /* PHY Low Power Clock sel*/ + | 0x9 << 10 /* USB Turnaround time (0x9 for HS phy) */ + | 0 << 9 /* [0:HNP disable,1:HNP enable]*/ + | 0 << 8 /* [0:SRP disable 1:SRP enable]*/ + | 0 << 6 /* 0: high speed utmi+, 1: full speed serial*/ + | 0x7 << 0; /* FS timeout calibration**/ + + if (p->force_b_session_valid) + p->usb_gusbcfg |= 1 << 30; /* FDMOD: Force device mode */ +} + +static int dwc2_udc_otg_reset_init(struct udevice *dev, + struct reset_ctl_bulk *resets) +{ + int ret; + + ret = reset_get_bulk(dev, resets); + if (ret == -ENOTSUPP) + return 0; + + if (ret) + return ret; + + ret = reset_assert_bulk(resets); + + if (!ret) { + udelay(2); + ret = reset_deassert_bulk(resets); + } + if (ret) { + reset_release_bulk(resets); + return ret; + } + + return 0; +} + +static int dwc2_udc_otg_clk_init(struct udevice *dev, + struct clk_bulk *clks) +{ + int ret; + + ret = clk_get_bulk(dev, clks); + if (ret == -ENOSYS) + return 0; + + if (ret) + return ret; + + ret = clk_enable_bulk(clks); + if (ret) { + clk_release_bulk(clks); + return ret; + } + + return 0; +} + +static int dwc2_udc_otg_probe(struct udevice *dev) +{ + struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev); + struct dwc2_priv_data *priv = dev_get_priv(dev); + struct dwc2_usbotg_reg *usbotg_reg = + (struct dwc2_usbotg_reg *)platdata->regs_otg; + int ret; + + ret = dwc2_udc_otg_clk_init(dev, &priv->clks); + if (ret) + return ret; + + ret = dwc2_udc_otg_reset_init(dev, &priv->resets); + if (ret) + return ret; + + ret = dwc2_phy_setup(dev, &priv->phys, &priv->num_phys); + if (ret) + return ret; + + if (CONFIG_IS_ENABLED(DM_REGULATOR) && + platdata->activate_stm_id_vb_detection && + !platdata->force_b_session_valid) { + ret = device_get_supply_regulator(dev, "usb33d-supply", + &priv->usb33d_supply); + if (ret) { + dev_err(dev, "can't get voltage level detector supply\n"); + return ret; + } + ret = regulator_set_enable(priv->usb33d_supply, true); + if (ret) { + dev_err(dev, "can't enable voltage level detector supply\n"); + return ret; + } + /* Enable vbus sensing */ + setbits_le32(&usbotg_reg->ggpio, + GGPIO_STM32_OTG_GCCFG_VBDEN | + GGPIO_STM32_OTG_GCCFG_IDEN); + } + + if (platdata->force_b_session_valid) + /* Override B session bits : value and enable */ + setbits_le32(&usbotg_reg->gotgctl, + A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL); + + ret = dwc2_udc_probe(platdata); + if (ret) + return ret; + + the_controller->driver = 0; + + ret = usb_add_gadget_udc((struct device *)dev, &the_controller->gadget); + + return ret; +} + +static int dwc2_udc_otg_remove(struct udevice *dev) +{ + struct dwc2_priv_data *priv = dev_get_priv(dev); + + usb_del_gadget_udc(&the_controller->gadget); + + reset_release_bulk(&priv->resets); + + clk_release_bulk(&priv->clks); + + dwc2_phy_shutdown(dev, priv->phys, priv->num_phys); + + return dm_scan_fdt_dev(dev); +} + +static const struct udevice_id dwc2_udc_otg_ids[] = { + { .compatible = "snps,dwc2" }, + { .compatible = "st,stm32mp1-hsotg", + .data = (ulong)dwc2_set_stm32mp1_hsotg_params }, + {}, +}; + +U_BOOT_DRIVER(dwc2_udc_otg) = { + .name = "dwc2-udc-otg", + .id = UCLASS_USB_GADGET_GENERIC, + .of_match = dwc2_udc_otg_ids, + .ofdata_to_platdata = dwc2_udc_otg_ofdata_to_platdata, + .probe = dwc2_udc_otg_probe, + .remove = dwc2_udc_otg_remove, + .platdata_auto_alloc_size = sizeof(struct dwc2_plat_otg_data), + .priv_auto_alloc_size = sizeof(struct dwc2_priv_data), +}; + +int dwc2_udc_B_session_valid(struct udevice *dev) +{ + struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev); + struct dwc2_usbotg_reg *usbotg_reg = + (struct dwc2_usbotg_reg *)platdata->regs_otg; + + return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID; } +#endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */ diff --git a/drivers/usb/gadget/dwc2_udc_otg_priv.h b/drivers/usb/gadget/dwc2_udc_otg_priv.h index aaa90187fb..e72b22ac61 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_priv.h +++ b/drivers/usb/gadget/dwc2_udc_otg_priv.h @@ -23,7 +23,6 @@ #define EP_FIFO_SIZE2 1024 /* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */ #define DWC2_MAX_ENDPOINTS 4 -#define DWC2_MAX_HW_ENDPOINTS 16 #define WAIT_FOR_SETUP 0 #define DATA_STATE_XMIT 1 diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index a1829b3fd1..434db5ba39 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -60,22 +60,26 @@ struct dwc2_usbotg_reg { u32 grxstsp; /* Receive Status Debug Pop/Status Pop */ u32 grxfsiz; /* Receive FIFO Size */ u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */ - u8 res1[216]; + u8 res0[12]; + u32 ggpio; /* 0x038 */ + u8 res1[20]; + u32 ghwcfg4; /* User HW Config4 */ + u8 res2[176]; u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */ - u8 res2[1728]; + u8 res3[1728]; /* Device Configuration */ u32 dcfg; /* Device Configuration Register */ u32 dctl; /* Device Control */ u32 dsts; /* Device Status */ - u8 res3[4]; + u8 res4[4]; u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */ u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */ u32 daint; /* Device All Endpoints Interrupt */ u32 daintmsk; /* Device All Endpoints Interrupt Mask */ - u8 res4[224]; + u8 res5[224]; struct dwc2_dev_in_endp in_endp[16]; struct dwc2_dev_out_endp out_endp[16]; - u8 res5[768]; + u8 res6[768]; struct ep_fifo ep[16]; }; @@ -83,8 +87,15 @@ struct dwc2_usbotg_reg { /*definitions related to CSR setting */ /* DWC2_UDC_OTG_GOTGCTL */ -#define B_SESSION_VALID (0x1<<19) -#define A_SESSION_VALID (0x1<<18) +#define B_SESSION_VALID BIT(19) +#define A_SESSION_VALID BIT(18) +#define B_VALOVAL BIT(7) +#define B_VALOEN BIT(6) +#define A_VALOVAL BIT(5) +#define A_VALOEN BIT(4) + +/* DWC2_UDC_OTG_GOTINT */ +#define GOTGINT_SES_END_DET (1<<2) /* DWC2_UDC_OTG_GAHBCFG */ #define PTXFE_HALF (0<<8) @@ -118,6 +129,7 @@ struct dwc2_usbotg_reg { #define INT_NP_TX_FIFO_EMPTY (0x1<<5) #define INT_RX_FIFO_NOT_EMPTY (0x1<<4) #define INT_SOF (0x1<<3) +#define INT_OTG (0x1<<2) #define INT_DEV_MODE (0x0<<0) #define INT_HOST_MODE (0x1<<1) #define INT_GOUTNakEff (0x01<<7) @@ -246,7 +258,7 @@ struct dwc2_usbotg_reg { /* Masks definitions */ #define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\ - | INT_RESET | INT_SUSPEND) + | INT_RESET | INT_SUSPEND | INT_OTG) #define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE) #define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE) #define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\ @@ -269,4 +281,13 @@ struct dwc2_usbotg_reg { /* Device ALL Endpoints Interrupt Register (DAINT) */ #define DAINT_IN_EP_INT(x) (x << 0) #define DAINT_OUT_EP_INT(x) (x << 16) + +/* User HW Config4 */ +#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) +#define GHWCFG4_NUM_IN_EPS_SHIFT 26 + +/* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */ +#define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21) +#define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22) + #endif diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index a75af4987f..7eb632d3b1 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -467,7 +467,7 @@ static void process_ep_out_intr(struct dwc2_udc *dev) static int dwc2_udc_irq(int irq, void *_dev) { struct dwc2_udc *dev = _dev; - u32 intr_status; + u32 intr_status, gotgint; u32 usb_status, gintmsk; unsigned long flags = 0; @@ -521,14 +521,24 @@ static int dwc2_udc_irq(int irq, void *_dev) && dev->driver) { if (dev->driver->suspend) dev->driver->suspend(&dev->gadget); + } + } + + if (intr_status & INT_OTG) { + gotgint = readl(®->gotgint); + debug_cond(DEBUG_ISR, + "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint); - /* HACK to let gadget detect disconnected state */ + if (gotgint & GOTGINT_SES_END_DET) { + debug_cond(DEBUG_ISR, "\t\tSession End Detected\n"); + /* Let gadget detect disconnected state */ if (dev->driver->disconnect) { spin_unlock_irqrestore(&dev->lock, flags); dev->driver->disconnect(&dev->gadget); spin_lock_irqsave(&dev->lock, flags); } } + writel(gotgint, ®->gotgint); } if (intr_status & INT_RESUME) { diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index ba1e6bfa43..0fbc115801 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -154,6 +154,13 @@ config USB_EHCI_OMAP Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. +config USB_EHCI_VF + bool "Support for Vybrid on-chip EHCI USB controller" + depends on ARCH_VF610 + default y + help + Enables support for the on-chip EHCI controller on Vybrid SoCs. + if USB_EHCI_MX7 config MXC_USB_OTG_HACTIVE diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index f8f2205a62..75005ccdd1 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -21,6 +21,7 @@ config USB_MUSB_GADGET config USB_MUSB_TI bool "Enable TI OTG USB controller" depends on DM_USB + select USB_MUSB_DSPS default n help Say y here to enable support for the dual role high @@ -54,6 +55,15 @@ config USB_MUSB_SUNXI Say y here to enable support for the sunxi OTG / DRC USB controller used on almost all sunxi boards. +config USB_MUSB_DISABLE_BULK_COMBINE_SPLIT + bool "Disable MUSB bulk split/combine" + default y + help + On TI AM335x devices, MUSB has bulk split/combine feature enabled + in the ConfigData register, but the current MUSB driver does not + support it yet. Select this option to disable the feature until the + driver adds the support. + endif config USB_MUSB_PIO_ONLY diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2eac4b6381..c3781b160d 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -120,7 +120,7 @@ config CONSOLE_TRUETYPE_SIZE config SYS_WHITE_ON_BLACK bool "Display console as white on a black background" - default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || TEGRA || X86 + default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || TEGRA || X86 || ARCH_SUNXI help Normally the display is black on a white background, Enable this option to invert this, i.e. white on a black background. This can be @@ -538,6 +538,8 @@ config VIDEO_TEGRA124 source "drivers/video/bridge/Kconfig" +source "drivers/video/imx/Kconfig" + config VIDEO bool "Enable legacy video support" depends on !DM_VIDEO @@ -547,13 +549,6 @@ config VIDEO model. Video drivers typically provide a colour text console and cursor. -config VIDEO_IPUV3 - bool "i.MX IPUv3 Core video support" - depends on VIDEO && MX6 - help - This enables framebuffer driver for i.MX processors working - on the IPUv3(Image Processing Unit) internal graphic processor. - config CFB_CONSOLE bool "Enable colour frame buffer console" depends on VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 671f037c35..349a207035 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_VIDEO_EFI) += efi.o obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o -obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_VIDEO_IPUV3) += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 2cfa510d5f..7f01ee9424 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -84,7 +84,8 @@ static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y, return -EAGAIN; for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { - uchar bits = video_fontdata[ch * VIDEO_FONT_HEIGHT + row]; + unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row; + uchar bits = video_fontdata[idx]; switch (vid_priv->bpix) { #ifdef CONFIG_VIDEO_BPP8 diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index f076570335..71a5c5efba 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -90,7 +90,7 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) int i, col; int mask = 0x80; void *line; - uchar *pfont = video_fontdata + ch * VIDEO_FONT_HEIGHT; + uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; line = vid_priv->fb + (VID_TO_PIXEL(x_frac) + 1) * vid_priv->line_length - (y + 1) * pbytes; @@ -222,7 +222,8 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) VIDEO_FONT_WIDTH - 1) * VNBYTES(vid_priv->bpix); for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { - uchar bits = video_fontdata[ch * VIDEO_FONT_HEIGHT + row]; + unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row; + uchar bits = video_fontdata[idx]; switch (vid_priv->bpix) { #ifdef CONFIG_VIDEO_BPP8 @@ -348,7 +349,7 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) void *line = vid_priv->fb + (vid_priv->ysize - VID_TO_PIXEL(x_frac) - 1) * vid_priv->line_length + y * pbytes; - uchar *pfont = video_fontdata + ch * VIDEO_FONT_HEIGHT; + uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig new file mode 100644 index 0000000000..c33620e075 --- /dev/null +++ b/drivers/video/imx/Kconfig @@ -0,0 +1,8 @@ + +config VIDEO_IPUV3 + bool "i.MX IPUv3 Core video support" + depends on (VIDEO || DM_VIDEO) && (MX5 || MX6) + help + This enables framebuffer driver for i.MX processors working + on the IPUv3(Image Processing Unit) internal graphic processor. + diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile new file mode 100644 index 0000000000..179ea651fe --- /dev/null +++ b/drivers/video/imx/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o diff --git a/drivers/video/ipu.h b/drivers/video/imx/ipu.h index 1e02c7ab6d..1e02c7ab6d 100644 --- a/drivers/video/ipu.h +++ b/drivers/video/imx/ipu.h diff --git a/drivers/video/ipu_common.c b/drivers/video/imx/ipu_common.c index cbe1984e4f..cbe1984e4f 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/imx/ipu_common.c diff --git a/drivers/video/ipu_disp.c b/drivers/video/imx/ipu_disp.c index 5c7722962d..5c7722962d 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/imx/ipu_disp.c diff --git a/drivers/video/ipu_regs.h b/drivers/video/imx/ipu_regs.h index deb44002d7..deb44002d7 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/imx/ipu_regs.h diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 23cd55de47..3e38d4bdcc 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -17,13 +17,17 @@ #include <linux/list.h> #include <linux/fb.h> #include <asm/io.h> +#include <asm/mach-imx/video.h> #include <malloc.h> #include <video_fb.h> -#include "videomodes.h" +#include "../videomodes.h" #include "ipu.h" #include "mxcfb.h" #include "ipu_regs.h" +#include <dm.h> +#include <video.h> + DECLARE_GLOBAL_DATA_PTR; static int mxcfb_map_video_memory(struct fb_info *fbi); @@ -401,8 +405,14 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->fix.line_length; } fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN); + +#if CONFIG_IS_ENABLED(DM_VIDEO) + fbi->screen_base = (char *)gd->video_bottom; +#else fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN, fbi->fix.smem_len); +#endif + fbi->fix.smem_start = (unsigned long)fbi->screen_base; if (fbi->screen_base == 0) { puts("Unable to allocate framebuffer memory\n"); @@ -416,7 +426,9 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->screen_size = fbi->fix.smem_len; +#if CONFIG_IS_ENABLED(VIDEO) gd->fb_base = fbi->fix.smem_start; +#endif /* Clear the screen */ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); @@ -611,3 +623,78 @@ int ipuv3_fb_init(struct fb_videomode const *mode, return 0; } + +#if CONFIG_IS_ENABLED(DM_VIDEO) +enum { + /* Maximum display size we support */ + LCD_MAX_WIDTH = 1920, + LCD_MAX_HEIGHT = 1080, + LCD_MAX_LOG2_BPP = VIDEO_BPP16, +}; + +static int ipuv3_video_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + u32 fb_start, fb_end; + int ret; + + debug("%s() plat: base 0x%lx, size 0x%x\n", + __func__, plat->base, plat->size); + + ret = ipu_probe(); + if (ret) + return ret; + + ret = ipu_displays_init(); + if (ret < 0) + return ret; + + ret = mxcfb_probe(gpixfmt, gdisp, gmode); + if (ret < 0) + return ret; + + uc_priv->xsize = gmode->xres; + uc_priv->ysize = gmode->yres; + uc_priv->bpix = LCD_MAX_LOG2_BPP; + + /* Enable dcache for the frame buffer */ + fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_end = plat->base + plat->size; + fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, + DCACHE_WRITEBACK); + video_set_flush_dcache(dev, true); + + return 0; +} + +struct ipuv3_video_priv { + ulong regs; +}; + +static int ipuv3_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP) / 8; + + return 0; +} + +static const struct udevice_id ipuv3_video_ids[] = { + { .compatible = "fsl,imx6q-ipu" }, + { } +}; + +U_BOOT_DRIVER(ipuv3_video) = { + .name = "ipuv3_video", + .id = UCLASS_VIDEO, + .of_match = ipuv3_video_ids, + .bind = ipuv3_video_bind, + .probe = ipuv3_video_probe, + .priv_auto_alloc_size = sizeof(struct ipuv3_video_priv), + .flags = DM_FLAG_PRE_RELOC, +}; +#endif /* CONFIG_DM_VIDEO */ diff --git a/drivers/video/mxcfb.h b/drivers/video/imx/mxcfb.h index 0dc3886193..0dc3886193 100644 --- a/drivers/video/mxcfb.h +++ b/drivers/video/imx/mxcfb.h diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c index bd733f5f1c..a587977c22 100644 --- a/drivers/video/pwm_backlight.c +++ b/drivers/video/pwm_backlight.c @@ -39,6 +39,12 @@ struct pwm_backlight_priv { struct udevice *pwm; uint channel; uint period_ns; + /* + * the polarity of one PWM + * 0: normal polarity + * 1: inverted polarity + */ + bool polarity; u32 *levels; int num_levels; uint default_level; @@ -57,7 +63,10 @@ static int set_pwm(struct pwm_backlight_priv *priv) (priv->max_level - priv->min_level + 1); ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns, duty_cycle); + if (ret) + return log_ret(ret); + ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity); return log_ret(ret); } @@ -202,6 +211,8 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice *dev) return log_msg_ret("Not enough arguments to pwm\n", -EINVAL); priv->channel = args.args[0]; priv->period_ns = args.args[1]; + if (args.args_count > 2) + priv->polarity = args.args[2]; index = dev_read_u32_default(dev, "default-brightness-level", 255); cell = dev_read_prop(dev, "brightness-levels", &len); diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 2ca19d4049..c31303b56e 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -259,6 +259,43 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) priv->escape = 0; switch (ch) { + case 'A': + case 'B': + case 'C': + case 'D': + case 'E': + case 'F': { + int row, col, num; + char *s = priv->escape_buf; + + /* + * Cursor up/down: [%dA, [%dB, [%dE, [%dF + * Cursor left/right: [%dD, [%dC + */ + s++; /* [ */ + s = parsenum(s, &num); + if (num == 0) /* No digit in sequence ... */ + num = 1; /* ... means "move by 1". */ + + get_cursor_position(priv, &row, &col); + if (ch == 'A' || ch == 'F') + row -= num; + if (ch == 'C') + col += num; + if (ch == 'D') + col -= num; + if (ch == 'B' || ch == 'E') + row += num; + if (ch == 'E' || ch == 'F') + col = 0; + if (col < 0) + col = 0; + if (row < 0) + row = 0; + /* Right and bottom overflows are handled in the callee. */ + set_cursor_position(priv, row, col); + break; + } case 'H': case 'f': { int row, col; @@ -309,6 +346,25 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) } break; } + case 'K': { + struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + int mode; + + /* + * Clear (parts of) current line + * [0K - clear line to end + * [2K - clear entire line + */ + parsenum(priv->escape_buf + 1, &mode); + + if (mode == 2) { + int row, col; + + get_cursor_position(priv, &row, &col); + vidconsole_set_row(dev, row, vid_priv->colour_bg); + } + break; + } case 'm': { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); char *s = priv->escape_buf; @@ -360,6 +416,13 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) vid_priv->colour_fg = vid_console_color( vid_priv, vid_priv->fg_col_idx); break; + case 7: + /* reverse video */ + vid_priv->colour_fg = vid_console_color( + vid_priv, vid_priv->bg_col_idx); + vid_priv->colour_bg = vid_console_color( + vid_priv, vid_priv->fg_col_idx); + break; case 30 ... 37: /* foreground color */ vid_priv->fg_col_idx &= ~7; @@ -368,9 +431,11 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) vid_priv, vid_priv->fg_col_idx); break; case 40 ... 47: - /* background color */ + /* background color, also mask the bold bit */ + vid_priv->bg_col_idx &= ~0xf; + vid_priv->bg_col_idx |= val - 40; vid_priv->colour_bg = vid_console_color( - vid_priv, val - 40); + vid_priv, vid_priv->bg_col_idx); break; default: /* ignore unsupported SGR parameter */ @@ -392,6 +457,32 @@ error: priv->escape = 0; } +/* Put that actual character on the screen (using the CP437 code page). */ +static int vidconsole_output_glyph(struct udevice *dev, char ch) +{ + struct vidconsole_priv *priv = dev_get_uclass_priv(dev); + int ret; + + /* + * Failure of this function normally indicates an unsupported + * colour depth. Check this and return an error to help with + * diagnosis. + */ + ret = vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ch); + if (ret == -EAGAIN) { + vidconsole_newline(dev); + ret = vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ch); + } + if (ret < 0) + return ret; + priv->xcur_frac += ret; + priv->last_ch = ch; + if (priv->xcur_frac >= priv->xsize_frac) + vidconsole_newline(dev); + + return 0; +} + int vidconsole_put_char(struct udevice *dev, char ch) { struct vidconsole_priv *priv = dev_get_uclass_priv(dev); @@ -429,23 +520,9 @@ int vidconsole_put_char(struct udevice *dev, char ch) priv->last_ch = 0; break; default: - /* - * Failure of this function normally indicates an unsupported - * colour depth. Check this and return an error to help with - * diagnosis. - */ - ret = vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ch); - if (ret == -EAGAIN) { - vidconsole_newline(dev); - ret = vidconsole_putc_xy(dev, priv->xcur_frac, - priv->ycur, ch); - } + ret = vidconsole_output_glyph(dev, ch); if (ret < 0) return ret; - priv->xcur_frac += ret; - priv->last_ch = ch; - if (priv->xcur_frac >= priv->xsize_frac) - vidconsole_newline(dev); break; } diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index f307cf243b..14aac88d6d 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -136,6 +136,7 @@ void video_set_default_colors(struct udevice *dev, bool invert) back = temp; } priv->fg_col_idx = fore; + priv->bg_col_idx = back; priv->colour_fg = vid_console_color(priv, fore); priv->colour_bg = vid_console_color(priv, back); } diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index 1cfeaa980f..d7614329ff 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -397,7 +397,7 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t, EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 || EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 || EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 || - /* 3d formats are not supported*/ + /* 3d formats are not supported */ EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0) return -EINVAL; |