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-rw-r--r--drivers/clk/clk-uclass.c20
-rw-r--r--drivers/clk/clk_k210.c2
-rw-r--r--drivers/clk/rockchip/clk_pll.c6
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c2
-rw-r--r--drivers/core/Kconfig2
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/adp5585_gpio.c238
-rw-r--r--drivers/input/Kconfig9
-rw-r--r--drivers/input/Makefile1
-rw-r--r--drivers/net/ftgmac100.c14
-rw-r--r--drivers/net/phy/ncsi.c1
-rw-r--r--drivers/net/phy/phy.c9
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c1
-rw-r--r--drivers/ram/rockchip/Kconfig2
15 files changed, 290 insertions, 24 deletions
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index b89c77bf79..2f9635524c 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -505,7 +505,7 @@ struct clk *clk_get_parent(struct clk *clk)
return pclk;
}
-long long clk_get_parent_rate(struct clk *clk)
+ulong clk_get_parent_rate(struct clk *clk)
{
const struct clk_ops *ops;
struct clk *pclk;
@@ -544,6 +544,19 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
return ops->round_rate(clk, rate);
}
+static void clk_get_priv(struct clk *clk, struct clk **clkp)
+{
+ *clkp = clk;
+
+ /* get private clock struct associated to the provided clock */
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ /* Take id 0 as a non-valid clk, such as dummy */
+ if (clk->id)
+ clk_get_by_id(clk->id, clkp);
+ }
+}
+
+/* clean cache, called with private clock struct */
static void clk_clean_rate_cache(struct clk *clk)
{
struct udevice *child_dev;
@@ -563,6 +576,7 @@ static void clk_clean_rate_cache(struct clk *clk)
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
+ struct clk *clkp;
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
if (!clk_valid(clk))
@@ -572,8 +586,10 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
if (!ops->set_rate)
return -ENOSYS;
+ /* get private clock struct used for cache */
+ clk_get_priv(clk, &clkp);
/* Clean up cached rates for us and all child clocks */
- clk_clean_rate_cache(clk);
+ clk_clean_rate_cache(clkp);
return ops->set_rate(clk, rate);
}
diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c
index 1961efaa5e..f7d36963f8 100644
--- a/drivers/clk/clk_k210.c
+++ b/drivers/clk/clk_k210.c
@@ -846,7 +846,7 @@ again:
error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
/* The lower 16 bits are spurious */
- error = abs((error - BIT(32))) >> 16;
+ error = abs64((error - BIT_ULL(32))) >> 16;
if (error < best_error) {
best->r = r;
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 8d2aaf5b84..09b97cf57a 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -31,7 +31,7 @@ static struct rockchip_pll_rate_table rockchip_auto_table;
#define RK3036_PLLCON1_DSMPD_SHIFT 12
#define RK3036_PLLCON2_FRAC_MASK 0xffffff
#define RK3036_PLLCON2_FRAC_SHIFT 0
-#define RK3036_PLLCON1_PWRDOWN_SHIT 13
+#define RK3036_PLLCON1_PWRDOWN_SHIFT 13
#define MHZ 1000000
#define KHZ 1000
@@ -207,7 +207,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
/* Power down */
rk_setreg(base + pll->con_offset + 0x4,
- 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
+ 1 << RK3036_PLLCON1_PWRDOWN_SHIFT);
rk_clrsetreg(base + pll->con_offset,
(RK3036_PLLCON0_POSTDIV1_MASK |
@@ -231,7 +231,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
/* Power Up */
rk_clrreg(base + pll->con_offset + 0x4,
- 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
+ 1 << RK3036_PLLCON1_PWRDOWN_SHIFT);
/* waiting for pll lock */
while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 97bf1c6e15..eaeac451df 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -856,7 +856,7 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
switch (set_rate) {
case 50 * MHz:
dpll_cfg = (struct pll_div)
- {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
+ {.refdiv = 2, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 6};
break;
case 200 * MHz:
dpll_cfg = (struct pll_div)
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index c9bf5de433..0dc442b921 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -1,7 +1,7 @@
menu "Generic Driver Options"
config DM
- bool "Enable Driver Model"
+ def_bool y
help
This config option enables Driver Model. This brings in the core
support, including scanning of platform data on start-up. If
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2a60478b47..220e2cb162 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -611,4 +611,10 @@ config FTGPIO010
help
Support for GPIOs on Faraday Technology's FTGPIO010 controller.
+config ADP5585_GPIO
+ bool "ADP5585 GPIO driver"
+ depends on DM_GPIO && DM_I2C
+ help
+ Support ADP5585 GPIO expander.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index eee7908871..7235714fcc 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o
obj-$(CONFIG_FTGPIO010) += ftgpio010.o
+obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c
new file mode 100644
index 0000000000..ea0cb75459
--- /dev/null
+++ b/drivers/gpio/adp5585_gpio.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * ADP5585 I/O Expander Controller
+ *
+ * Author: Alice Guo <alice.guo@nxp.com>
+ */
+
+#include <asm/gpio.h>
+#include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <i2c.h>
+
+#define ADP5585_ID 0x00
+#define ADP5585_INT_STATUS 0x01
+#define ADP5585_STATUS 0x02
+#define ADP5585_FIFO_1 0x03
+#define ADP5585_FIFO_2 0x04
+#define ADP5585_FIFO_3 0x05
+#define ADP5585_FIFO_4 0x06
+#define ADP5585_FIFO_5 0x07
+#define ADP5585_FIFO_6 0x08
+#define ADP5585_FIFO_7 0x09
+#define ADP5585_FIFO_8 0x0A
+#define ADP5585_FIFO_9 0x0B
+#define ADP5585_FIFO_10 0x0C
+#define ADP5585_FIFO_11 0x0D
+#define ADP5585_FIFO_12 0x0E
+#define ADP5585_FIFO_13 0x0F
+#define ADP5585_FIFO_14 0x10
+#define ADP5585_FIFO_15 0x11
+#define ADP5585_FIFO_16 0x12
+#define ADP5585_GPI_INT_STAT_A 0x13
+#define ADP5585_GPI_INT_STAT_B 0x14
+#define ADP5585_GPI_STATUS_A 0x15
+#define ADP5585_GPI_STATUS_B 0x16
+#define ADP5585_RPULL_CONFIG_A 0x17
+#define ADP5585_RPULL_CONFIG_B 0x18
+#define ADP5585_RPULL_CONFIG_C 0x19
+#define ADP5585_RPULL_CONFIG_D 0x1A
+#define ADP5585_GPI_INT_LEVEL_A 0x1B
+#define ADP5585_GPI_INT_LEVEL_B 0x1C
+#define ADP5585_GPI_EVENT_EN_A 0x1D
+#define ADP5585_GPI_EVENT_EN_B 0x1E
+#define ADP5585_GPI_INTERRUPT_EN_A 0x1F
+#define ADP5585_GPI_INTERRUPT_EN_B 0x20
+#define ADP5585_DEBOUNCE_DIS_A 0x21
+#define ADP5585_DEBOUNCE_DIS_B 0x22
+#define ADP5585_GPO_DATA_OUT_A 0x23
+#define ADP5585_GPO_DATA_OUT_B 0x24
+#define ADP5585_GPO_OUT_MODE_A 0x25
+#define ADP5585_GPO_OUT_MODE_B 0x26
+#define ADP5585_GPIO_DIRECTION_A 0x27
+#define ADP5585_GPIO_DIRECTION_B 0x28
+#define ADP5585_RESET1_EVENT_A 0x29
+#define ADP5585_RESET1_EVENT_B 0x2A
+#define ADP5585_RESET1_EVENT_C 0x2B
+#define ADP5585_RESET2_EVENT_A 0x2C
+#define ADP5585_RESET2_EVENT_B 0x2D
+#define ADP5585_RESET_CFG 0x2E
+#define ADP5585_PWM_OFFT_LOW 0x2F
+#define ADP5585_PWM_OFFT_HIGH 0x30
+#define ADP5585_PWM_ONT_LOW 0x31
+#define ADP5585_PWM_ONT_HIGH 0x32
+#define ADP5585_PWM_CFG 0x33
+#define ADP5585_LOGIC_CFG 0x34
+#define ADP5585_LOGIC_FF_CFG 0x35
+#define ADP5585_LOGIC_INT_EVENT_EN 0x36
+#define ADP5585_POLL_PTIME_CFG 0x37
+#define ADP5585_PIN_CONFIG_A 0x38
+#define ADP5585_PIN_CONFIG_B 0x39
+#define ADP5585_PIN_CONFIG_D 0x3A
+#define ADP5585_GENERAL_CFG 0x3B
+#define ADP5585_INT_EN 0x3C
+
+#define ADP5585_MAXGPIO 10
+#define ADP5585_BANK(offs) ((offs) > 4)
+#define ADP5585_BIT(offs) ((offs) > 4 ? \
+ 1u << ((offs) - 5) : 1u << (offs))
+
+struct adp5585_plat {
+ fdt_addr_t addr;
+ u8 id;
+ u8 dat_out[2];
+ u8 dir[2];
+};
+
+static int adp5585_direction_input(struct udevice *dev, unsigned int offset)
+{
+ int ret;
+ unsigned int bank;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+
+ plat->dir[bank] &= ~ADP5585_BIT(offset);
+ ret = dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1);
+
+ return ret;
+}
+
+static int adp5585_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ int ret;
+ unsigned int bank, bit;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+ bit = ADP5585_BIT(offset);
+
+ plat->dir[bank] |= bit;
+
+ if (value)
+ plat->dat_out[bank] |= bit;
+ else
+ plat->dat_out[bank] &= ~bit;
+
+ ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1);
+ ret |= dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1);
+
+ return ret;
+}
+
+static int adp5585_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct adp5585_plat *plat = dev_get_plat(dev);
+ unsigned int bank = ADP5585_BANK(offset);
+ unsigned int bit = ADP5585_BIT(offset);
+ u8 val;
+
+ if (plat->dir[bank] & bit)
+ val = plat->dat_out[bank];
+ else
+ dm_i2c_read(dev, ADP5585_GPI_STATUS_A + bank, &val, 1);
+
+ return !!(val & bit);
+}
+
+static int adp5585_set_value(struct udevice *dev, unsigned int offset, int value)
+{
+ int ret;
+ unsigned int bank, bit;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+ bit = ADP5585_BIT(offset);
+
+ if (value)
+ plat->dat_out[bank] |= bit;
+ else
+ plat->dat_out[bank] &= ~bit;
+
+ ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1);
+
+ return ret;
+}
+
+static int adp5585_get_function(struct udevice *dev, unsigned int offset)
+{
+ unsigned int bank, bit, dir;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+ bit = ADP5585_BIT(offset);
+ dir = plat->dir[bank] & bit;
+
+ if (!dir)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_OUTPUT;
+}
+
+static int adp5585_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ desc->offset = args->args[0];
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops adp5585_ops = {
+ .direction_input = adp5585_direction_input,
+ .direction_output = adp5585_direction_output,
+ .get_value = adp5585_get_value,
+ .set_value = adp5585_set_value,
+ .get_function = adp5585_get_function,
+ .xlate = adp5585_xlate,
+};
+
+static int adp5585_probe(struct udevice *dev)
+{
+ struct adp5585_plat *plat = dev_get_plat(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ if (!plat)
+ return 0;
+
+ plat->addr = dev_read_addr(dev);
+ if (plat->addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = dm_i2c_read(dev, ADP5585_ID, &plat->id, 1);
+ if (ret < 0)
+ return ret;
+
+ uc_priv->gpio_count = ADP5585_MAXGPIO;
+ uc_priv->bank_name = "adp5585-gpio";
+
+ for (int i = 0; i < 2; i++) {
+ ret = dm_i2c_read(dev, ADP5585_GPO_DATA_OUT_A + i, &plat->dat_out[i], 1);
+ if (ret)
+ return ret;
+
+ ret = dm_i2c_read(dev, ADP5585_GPIO_DIRECTION_A + i, &plat->dir[i], 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id adp5585_ids[] = {
+ { .compatible = "adp5585" },
+ { }
+};
+
+U_BOOT_DRIVER(adp5585) = {
+ .name = "adp5585",
+ .id = UCLASS_GPIO,
+ .of_match = adp5585_ids,
+ .probe = adp5585_probe,
+ .ops = &adp5585_ops,
+ .plat_auto = sizeof(struct adp5585_plat),
+};
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index 2718b3674a..1c534be005 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -38,15 +38,6 @@ config TPL_DM_KEYBOARD
includes methods to start/stop the device, check for available
input and update LEDs if the keyboard has them.
-config KEYBOARD
- bool "Enable legacy keyboard support (deprecated)"
- help
- Enable this to enable a custom keyboard support.
- This simply calls drv_keyboard_init() which must be
- defined in your board-specific files. This option is deprecated
- and is only used by novena. For new boards, use driver model
- instead.
-
config APPLE_SPI_KEYB
bool "Enable Apple SPI keyboard support"
depends on DM_KEYBOARD && DM_SPI
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index b1133f772f..ded76bddb2 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -3,7 +3,6 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_KEYBOARD) += input.o
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_KEYB) += cros_ec_keyb.o
obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += key_matrix.o
obj-$(CONFIG_$(SPL_TPL_)DM_KEYBOARD) += input.o keyboard-uclass.o
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 74261d14e5..a50cde338a 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -188,7 +188,7 @@ static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
struct phy_device *phydev = priv->phydev;
u32 maccr;
- if (!phydev->link) {
+ if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) {
dev_err(phydev->dev, "No link\n");
return -EREMOTEIO;
}
@@ -228,7 +228,8 @@ static int ftgmac100_phy_init(struct udevice *dev)
if (!phydev)
return -ENODEV;
- phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+ phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);
if (ret)
@@ -308,7 +309,8 @@ static void ftgmac100_stop(struct udevice *dev)
writel(0, &ftgmac100->maccr);
- phy_shutdown(priv->phydev);
+ if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+ phy_shutdown(priv->phydev);
}
static int ftgmac100_start(struct udevice *dev)
@@ -580,6 +582,9 @@ static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
+ if (dev_read_bool(dev, "use-ncsi"))
+ priv->phy_mode = PHY_INTERFACE_MODE_NCSI;
+
#ifdef CONFIG_PHY_ADDR
priv->phy_addr = CONFIG_PHY_ADDR;
#endif
@@ -592,7 +597,8 @@ static int ftgmac100_probe(struct udevice *dev)
* If DM MDIO is enabled, the MDIO bus will be initialized later in
* dm_eth_phy_connect
*/
- if (!IS_ENABLED(CONFIG_DM_MDIO)) {
+ if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI &&
+ !IS_ENABLED(CONFIG_DM_MDIO)) {
ret = ftgmac100_mdio_init(dev);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c
index bf1e832be9..bb7ecebed3 100644
--- a/drivers/net/phy/ncsi.c
+++ b/drivers/net/phy/ncsi.c
@@ -9,6 +9,7 @@
#include <log.h>
#include <malloc.h>
#include <phy.h>
+#include <net.h>
#include <net/ncsi.h>
#include <net/ncsi-pkt.h>
#include <asm/unaligned.h>
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 0350afdd1b..9087663053 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1026,7 +1026,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr,
#endif
#ifdef CONFIG_PHY_NCSI
- if (!phydev)
+ if (!phydev && interface == PHY_INTERFACE_MODE_NCSI)
phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false);
#endif
@@ -1275,3 +1275,10 @@ int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val
return 0;
}
+
+bool phy_interface_is_ncsi(void)
+{
+ struct eth_pdata *pdata = dev_get_plat(eth_get_dev());
+
+ return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI;
+}
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 9ce2bc1b3a..061104be05 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
#else
{ "uart0", 5 }, /* PE0-PE1 */
#endif
+ { "uart1", 5 }, /* PA0-PA3 */
};
static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index c459bbf5e2..c29d5e8b38 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -23,7 +23,7 @@ config RAM_ROCKCHIP_DEBUG
initialization, configurations and etc.
config RAM_PX30_DDR4
- bool "DDR3 support for Rockchip PX30"
+ bool "DDR4 support for Rockchip PX30"
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
help
This enables DDR4 sdram support instead of the default DDR3 support
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 11:12:28 +0000