diff options
Diffstat (limited to 'drivers')
61 files changed, 3386 insertions, 994 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index c9031f2ce8..00da40b704 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -14,8 +14,8 @@ obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/ obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ddr/marvell/a38x/ -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ddr/marvell/axp/ +obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ +obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/ obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/ diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f161c01c67..eb8bda9ab2 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_MX51_PATA) += mxc_ata.o obj-$(CONFIG_PATA_BFIN) += pata_bfin.o obj-$(CONFIG_SATA_DWC) += sata_dwc.o +obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o obj-$(CONFIG_SATA_SIL) += sata_sil.o obj-$(CONFIG_IDE_SIL680) += sil680.o diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 5efa821dad..d29642be77 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -10,6 +10,7 @@ #include <common.h> #include <command.h> +#include <dm.h> #include <pci.h> #include <asm/processor.h> #include <asm/errno.h> @@ -168,9 +169,14 @@ int ahci_reset(void __iomem *base) static int ahci_host_init(struct ahci_probe_ent *probe_ent) { #ifndef CONFIG_SCSI_AHCI_PLAT +# ifdef CONFIG_DM_PCI + struct udevice *dev = probe_ent->dev; + struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); +# else pci_dev_t pdev = probe_ent->dev; - u16 tmp16; unsigned short vendor; +# endif + u16 tmp16; #endif void __iomem *mmio = probe_ent->mmio_base; u32 tmp, cap_save, cmd; @@ -193,6 +199,14 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); #ifndef CONFIG_SCSI_AHCI_PLAT +# ifdef CONFIG_DM_PCI + if (pplat->vendor == PCI_VENDOR_ID_INTEL) { + u16 tmp16; + + dm_pci_read_config16(dev, 0x92, &tmp16); + dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); + } +# else pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); if (vendor == PCI_VENDOR_ID_INTEL) { @@ -201,6 +215,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) tmp16 |= 0xf; pci_write_config_word(pdev, 0x92, tmp16); } +# endif #endif probe_ent->cap = readl(mmio + HOST_CAP); probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); @@ -313,9 +328,15 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) tmp = readl(mmio + HOST_CTL); debug("HOST_CTL 0x%x\n", tmp); #ifndef CONFIG_SCSI_AHCI_PLAT +# ifdef CONFIG_DM_PCI + dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); + tmp |= PCI_COMMAND_MASTER; + dm_pci_write_config16(dev, PCI_COMMAND, tmp16); +# else pci_read_config_word(pdev, PCI_COMMAND, &tmp16); tmp |= PCI_COMMAND_MASTER; pci_write_config_word(pdev, PCI_COMMAND, tmp16); +# endif #endif return 0; } @@ -324,7 +345,11 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) static void ahci_print_info(struct ahci_probe_ent *probe_ent) { #ifndef CONFIG_SCSI_AHCI_PLAT +# ifdef CONFIG_DM_PCI + struct udevice *dev = probe_ent->dev; +# else pci_dev_t pdev = probe_ent->dev; +# endif u16 cc; #endif void __iomem *mmio = probe_ent->mmio_base; @@ -350,7 +375,11 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) #ifdef CONFIG_SCSI_AHCI_PLAT scc_s = "SATA"; #else +# ifdef CONFIG_DM_PCI + dm_pci_read_config16(dev, 0x0a, &cc); +# else pci_read_config_word(pdev, 0x0a, &cc); +# endif if (cc == 0x0101) scc_s = "IDE"; else if (cc == 0x0106) @@ -395,7 +424,11 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) } #ifndef CONFIG_SCSI_AHCI_PLAT -static int ahci_init_one(pci_dev_t pdev) +# ifdef CONFIG_DM_PCI +static int ahci_init_one(struct udevice *dev) +# else +static int ahci_init_one(pci_dev_t dev) +# endif { u16 vendor; int rc; @@ -407,7 +440,7 @@ static int ahci_init_one(pci_dev_t pdev) } memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); - probe_ent->dev = pdev; + probe_ent->dev = dev; probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY @@ -417,18 +450,31 @@ static int ahci_init_one(pci_dev_t pdev) probe_ent->pio_mask = 0x1f; probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5, +#ifdef CONFIG_DM_PCI + probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, + PCI_REGION_MEM); + + /* Take from kernel: + * JMicron-specific fixup: + * make sure we're in AHCI mode + */ + dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); + if (vendor == 0x197b) + dm_pci_write_config8(dev, 0x41, 0xa1); +#else + probe_ent->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5, PCI_REGION_MEM); - debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base); /* Take from kernel: * JMicron-specific fixup: * make sure we're in AHCI mode */ - pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); if (vendor == 0x197b) - pci_write_config_byte(pdev, 0x41, 0xa1); + pci_write_config_byte(dev, 0x41, 0xa1); +#endif + debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base); /* initialize adapter */ rc = ahci_host_init(probe_ent); if (rc) @@ -915,7 +961,17 @@ void scsi_low_level_init(int busdevfunc) u32 linkmap; #ifndef CONFIG_SCSI_AHCI_PLAT +# ifdef CONFIG_DM_PCI + struct udevice *dev; + int ret; + + ret = dm_pci_bus_find_bdf(busdevfunc, &dev); + if (ret) + return; + ahci_init_one(dev); +# else ahci_init_one(busdevfunc); +# endif #endif linkmap = probe_ent->link_port_map; diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 52c16025f8..2c6d42410c 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -13,7 +13,7 @@ #include <asm/arch/orion5x.h> #elif defined(CONFIG_KIRKWOOD) #include <asm/arch/soc.h> -#elif defined(CONFIG_ARMADA_XP) +#elif defined(CONFIG_ARCH_MVEBU) #include <linux/mbus.h> #endif @@ -102,7 +102,7 @@ struct mvsata_port_registers { * Initialize SATA memory windows for Armada XP */ -#ifdef CONFIG_ARMADA_XP +#ifdef CONFIG_ARCH_MVEBU static void mvsata_ide_conf_mbus_windows(void) { const struct mbus_dram_target_info *dram; @@ -174,7 +174,7 @@ int ide_preinit(void) int ret = MVSATA_STATUS_TIMEOUT; int status; -#ifdef CONFIG_ARMADA_XP +#ifdef CONFIG_ARCH_MVEBU mvsata_ide_conf_mbus_windows(); #endif diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 73f4c4a9e9..170f0fa5bf 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -22,9 +22,11 @@ static struct host_block_dev *find_host_device(int dev) return NULL; } -static unsigned long host_block_read(int dev, unsigned long start, - lbaint_t blkcnt, void *buffer) +static unsigned long host_block_read(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + void *buffer) { + int dev = block_dev->dev; struct host_block_dev *host_dev = find_host_device(dev); if (!host_dev) @@ -42,9 +44,11 @@ static unsigned long host_block_read(int dev, unsigned long start, return -1; } -static unsigned long host_block_write(int dev, unsigned long start, - lbaint_t blkcnt, const void *buffer) +static unsigned long host_block_write(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + const void *buffer) { + int dev = block_dev->dev; struct host_block_dev *host_dev = find_host_device(dev); if (os_lseek(host_dev->fd, start * host_dev->blk_dev.blksz, diff --git a/drivers/block/sata_mv.c b/drivers/block/sata_mv.c new file mode 100644 index 0000000000..88249341d6 --- /dev/null +++ b/drivers/block/sata_mv.c @@ -0,0 +1,1045 @@ +/* + * Copyright (C) Excito Elektronik i Skåne AB, 2010. + * Author: Tor Krill <tor@excito.com> + * + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This driver supports the SATA controller of some Mavell SoC's. + * Here a (most likely incomplete) list of the supported SoC's: + * - Kirkwood + * - Armada 370 + * - Armada XP + * + * This driver implementation is an alternative to the already available + * driver via the "ide" commands interface (drivers/block/mvsata_ide.c). + * But this driver only supports PIO mode and as this new driver also + * supports transfer via DMA, its much faster. + * + * Please note, that the newer SoC's (e.g. Armada 38x) are not supported + * by this driver. As they have an AHCI compatible SATA controller + * integrated. + */ + +/* + * TODO: + * Better error recovery + * No support for using PRDs (Thus max 64KB transfers) + * No NCQ support + * No port multiplier support + */ + +#include <common.h> +#include <fis.h> +#include <libata.h> +#include <malloc.h> +#include <sata.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <linux/mbus.h> + +#if defined(CONFIG_KIRKWOOD) +#include <asm/arch/kirkwood.h> +#define SATAHC_BASE KW_SATA_BASE +#else +#include <asm/arch/soc.h> +#define SATAHC_BASE MVEBU_AXP_SATA_BASE +#endif + +#define SATA0_BASE (SATAHC_BASE + 0x2000) +#define SATA1_BASE (SATAHC_BASE + 0x4000) + +/* EDMA registers */ +#define EDMA_CFG 0x000 +#define EDMA_CFG_NCQ (1 << 5) +#define EDMA_CFG_EQUE (1 << 9) +#define EDMA_TIMER 0x004 +#define EDMA_IECR 0x008 +#define EDMA_IEMR 0x00c +#define EDMA_RQBA_HI 0x010 +#define EDMA_RQIPR 0x014 +#define EDMA_RQIPR_IPMASK (0x1f << 5) +#define EDMA_RQIPR_IPSHIFT 5 +#define EDMA_RQOPR 0x018 +#define EDMA_RQOPR_OPMASK (0x1f << 5) +#define EDMA_RQOPR_OPSHIFT 5 +#define EDMA_RSBA_HI 0x01c +#define EDMA_RSIPR 0x020 +#define EDMA_RSIPR_IPMASK (0x1f << 3) +#define EDMA_RSIPR_IPSHIFT 3 +#define EDMA_RSOPR 0x024 +#define EDMA_RSOPR_OPMASK (0x1f << 3) +#define EDMA_RSOPR_OPSHIFT 3 +#define EDMA_CMD 0x028 +#define EDMA_CMD_ENEDMA (0x01 << 0) +#define EDMA_CMD_DISEDMA (0x01 << 1) +#define EDMA_CMD_ATARST (0x01 << 2) +#define EDMA_CMD_FREEZE (0x01 << 4) +#define EDMA_TEST_CTL 0x02c +#define EDMA_STATUS 0x030 +#define EDMA_IORTO 0x034 +#define EDMA_CDTR 0x040 +#define EDMA_HLTCND 0x060 +#define EDMA_NTSR 0x094 + +/* Basic DMA registers */ +#define BDMA_CMD 0x224 +#define BDMA_STATUS 0x228 +#define BDMA_DTLB 0x22c +#define BDMA_DTHB 0x230 +#define BDMA_DRL 0x234 +#define BDMA_DRH 0x238 + +/* SATA Interface registers */ +#define SIR_ICFG 0x050 +#define SIR_CFG_GEN2EN (0x1 << 7) +#define SIR_PLL_CFG 0x054 +#define SIR_SSTATUS 0x300 +#define SSTATUS_DET_MASK (0x0f << 0) +#define SIR_SERROR 0x304 +#define SIR_SCONTROL 0x308 +#define SIR_SCONTROL_DETEN (0x01 << 0) +#define SIR_LTMODE 0x30c +#define SIR_LTMODE_NELBE (0x01 << 7) +#define SIR_PHYMODE3 0x310 +#define SIR_PHYMODE4 0x314 +#define SIR_PHYMODE1 0x32c +#define SIR_PHYMODE2 0x330 +#define SIR_BIST_CTRL 0x334 +#define SIR_BIST_DW1 0x338 +#define SIR_BIST_DW2 0x33c +#define SIR_SERR_IRQ_MASK 0x340 +#define SIR_SATA_IFCTRL 0x344 +#define SIR_SATA_TESTCTRL 0x348 +#define SIR_SATA_IFSTATUS 0x34c +#define SIR_VEND_UNIQ 0x35c +#define SIR_FIS_CFG 0x360 +#define SIR_FIS_IRQ_CAUSE 0x364 +#define SIR_FIS_IRQ_MASK 0x368 +#define SIR_FIS_DWORD0 0x370 +#define SIR_FIS_DWORD1 0x374 +#define SIR_FIS_DWORD2 0x378 +#define SIR_FIS_DWORD3 0x37c +#define SIR_FIS_DWORD4 0x380 +#define SIR_FIS_DWORD5 0x384 +#define SIR_FIS_DWORD6 0x388 +#define SIR_PHYM9_GEN2 0x398 +#define SIR_PHYM9_GEN1 0x39c +#define SIR_PHY_CFG 0x3a0 +#define SIR_PHYCTL 0x3a4 +#define SIR_PHYM10 0x3a8 +#define SIR_PHYM12 0x3b0 + +/* Shadow registers */ +#define PIO_DATA 0x100 +#define PIO_ERR_FEATURES 0x104 +#define PIO_SECTOR_COUNT 0x108 +#define PIO_LBA_LOW 0x10c +#define PIO_LBA_MID 0x110 +#define PIO_LBA_HI 0x114 +#define PIO_DEVICE 0x118 +#define PIO_CMD_STATUS 0x11c +#define PIO_STATUS_ERR (0x01 << 0) +#define PIO_STATUS_DRQ (0x01 << 3) +#define PIO_STATUS_DF (0x01 << 5) +#define PIO_STATUS_DRDY (0x01 << 6) +#define PIO_STATUS_BSY (0x01 << 7) +#define PIO_CTRL_ALTSTAT 0x120 + +/* SATAHC arbiter registers */ +#define SATAHC_CFG 0x000 +#define SATAHC_RQOP 0x004 +#define SATAHC_RQIP 0x008 +#define SATAHC_ICT 0x00c +#define SATAHC_ITT 0x010 +#define SATAHC_ICR 0x014 +#define SATAHC_ICR_PORT0 (0x01 << 0) +#define SATAHC_ICR_PORT1 (0x01 << 1) +#define SATAHC_MIC 0x020 +#define SATAHC_MIM 0x024 +#define SATAHC_LED_CFG 0x02c + +#define REQUEST_QUEUE_SIZE 32 +#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE + +struct crqb { + u32 dtb_low; /* DW0 */ + u32 dtb_high; /* DW1 */ + u32 control_flags; /* DW2 */ + u32 drb_count; /* DW3 */ + u32 ata_cmd_feat; /* DW4 */ + u32 ata_addr; /* DW5 */ + u32 ata_addr_exp; /* DW6 */ + u32 ata_sect_count; /* DW7 */ +}; + +#define CRQB_ALIGN 0x400 + +#define CRQB_CNTRLFLAGS_DIR (0x01 << 0) +#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1) +#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1 +#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12) +#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12 +#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16) +#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17) +#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17 + +#define CRQB_CMDFEAT_CMDMASK (0xff << 16) +#define CRQB_CMDFEAT_CMDSHIFT 16 +#define CRQB_CMDFEAT_FEATMASK (0xff << 16) +#define CRQB_CMDFEAT_FEATSHIFT 24 + +#define CRQB_ADDR_LBA_LOWMASK (0xff << 0) +#define CRQB_ADDR_LBA_LOWSHIFT 0 +#define CRQB_ADDR_LBA_MIDMASK (0xff << 8) +#define CRQB_ADDR_LBA_MIDSHIFT 8 +#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16) +#define CRQB_ADDR_LBA_HIGHSHIFT 16 +#define CRQB_ADDR_DEVICE_MASK (0xff << 24) +#define CRQB_ADDR_DEVICE_SHIFT 24 + +#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0) +#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0 +#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8) +#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8 +#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16) +#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16 +#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24) +#define CRQB_ADDR_FEATURE_EXP_SHIFT 24 + +#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0) +#define CRQB_SECTCOUNT_COUNT_SHIFT 0 +#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8) +#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8 + +#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) +#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) + +struct eprd { + u32 phyaddr_low; + u32 bytecount_eot; + u32 phyaddr_hi; + u32 reserved; +}; + +#define EPRD_PHYADDR_MASK 0xfffffffe +#define EPRD_BYTECOUNT_MASK 0x0000ffff +#define EPRD_EOT (0x01 << 31) + +struct crpb { + u32 id; + u32 flags; + u32 timestamp; +}; + +#define CRPB_ALIGN 0x100 + +#define READ_CMD 0 +#define WRITE_CMD 1 + +/* + * Since we don't use PRDs yet max transfer size + * is 64KB + */ +#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE) + +/* Keep track if hw is initialized or not */ +static u32 hw_init; + +struct mv_priv { + char name[12]; + u32 link; + u32 regbase; + u32 queue_depth; + u16 pio; + u16 mwdma; + u16 udma; + + void *crqb_alloc; + struct crqb *request; + + void *crpb_alloc; + struct crpb *response; +}; + +static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec) +{ + ulong start; + + start = get_timer(0); + do { + if ((in_le32(addr) & mask) == val) + return 0; + } while (get_timer(start) < timeout_msec); + + return -ETIMEDOUT; +} + +/* Cut from sata_mv in linux kernel */ +static int mv_stop_edma_engine(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + int i; + + /* Disable eDMA. The disable bit auto clears. */ + out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA); + + /* Wait for the chip to confirm eDMA is off. */ + for (i = 10000; i > 0; i--) { + u32 reg = in_le32(priv->regbase + EDMA_CMD); + if (!(reg & EDMA_CMD_ENEDMA)) { + debug("EDMA stop on port %d succesful\n", port); + return 0; + } + udelay(10); + } + debug("EDMA stop on port %d failed\n", port); + return -1; +} + +static int mv_start_edma_engine(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + /* Check preconditions */ + tmp = in_le32(priv->regbase + SIR_SSTATUS); + if ((tmp & SSTATUS_DET_MASK) != 0x03) { + printf("Device error on port: %d\n", port); + return -1; + } + + tmp = in_le32(priv->regbase + PIO_CMD_STATUS); + if (tmp & (ATA_BUSY | ATA_DRQ)) { + printf("Device not ready on port: %d\n", port); + return -1; + } + + /* Clear interrupt cause */ + out_le32(priv->regbase + EDMA_IECR, 0x0); + + tmp = in_le32(SATAHC_BASE + SATAHC_ICR); + tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1); + out_le32(SATAHC_BASE + SATAHC_ICR, tmp); + + /* Configure edma operation */ + tmp = in_le32(priv->regbase + EDMA_CFG); + tmp &= ~EDMA_CFG_NCQ; /* No NCQ */ + tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */ + out_le32(priv->regbase + EDMA_CFG, tmp); + + out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0); + + /* Configure fis, set all to no-wait for now */ + out_le32(priv->regbase + SIR_FIS_CFG, 0x0); + + /* Setup request queue */ + out_le32(priv->regbase + EDMA_RQBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RQIPR, priv->request); + out_le32(priv->regbase + EDMA_RQOPR, 0x0); + + /* Setup response queue */ + out_le32(priv->regbase + EDMA_RSBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RSOPR, priv->response); + out_le32(priv->regbase + EDMA_RSIPR, 0x0); + + /* Start edma */ + out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA); + + return 0; +} + +static int mv_reset_channel(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + /* Make sure edma is stopped */ + mv_stop_edma_engine(port); + + out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST); + udelay(25); /* allow reset propagation */ + out_le32(priv->regbase + EDMA_CMD, 0); + mdelay(10); + + return 0; +} + +static void mv_reset_port(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + mv_reset_channel(port); + + out_le32(priv->regbase + EDMA_CMD, 0x0); + out_le32(priv->regbase + EDMA_CFG, 0x101f); + out_le32(priv->regbase + EDMA_IECR, 0x0); + out_le32(priv->regbase + EDMA_IEMR, 0x0); + out_le32(priv->regbase + EDMA_RQBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RQIPR, 0x0); + out_le32(priv->regbase + EDMA_RQOPR, 0x0); + out_le32(priv->regbase + EDMA_RSBA_HI, 0x0); + out_le32(priv->regbase + EDMA_RSIPR, 0x0); + out_le32(priv->regbase + EDMA_RSOPR, 0x0); + out_le32(priv->regbase + EDMA_IORTO, 0xfa); +} + +static void mv_reset_one_hc(void) +{ + out_le32(SATAHC_BASE + SATAHC_ICT, 0x00); + out_le32(SATAHC_BASE + SATAHC_ITT, 0x00); + out_le32(SATAHC_BASE + SATAHC_ICR, 0x00); +} + +static int probe_port(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + int tries, tries2, set15 = 0; + u32 tmp; + + debug("Probe port: %d\n", port); + + for (tries = 0; tries < 2; tries++) { + /* Clear SError */ + out_le32(priv->regbase + SIR_SERROR, 0x0); + + /* trigger com-init */ + tmp = in_le32(priv->regbase + SIR_SCONTROL); + tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN; + out_le32(priv->regbase + SIR_SCONTROL, tmp); + + mdelay(1); + + tmp = in_le32(priv->regbase + SIR_SCONTROL); + tries2 = 5; + do { + tmp = (tmp & 0x0f0) | 0x300; + out_le32(priv->regbase + SIR_SCONTROL, tmp); + mdelay(10); + tmp = in_le32(priv->regbase + SIR_SCONTROL); + } while ((tmp & 0xf0f) != 0x300 && tries2--); + + mdelay(10); + + for (tries2 = 0; tries2 < 200; tries2++) { + tmp = in_le32(priv->regbase + SIR_SSTATUS); + if ((tmp & SSTATUS_DET_MASK) == 0x03) { + debug("Found device on port\n"); + return 0; + } + mdelay(1); + } + + if ((tmp & SSTATUS_DET_MASK) == 0) { + debug("No device attached on port %d\n", port); + return -ENODEV; + } + + if (!set15) { + /* Try on 1.5Gb/S */ + debug("Try 1.5Gb link\n"); + set15 = 1; + out_le32(priv->regbase + SIR_SCONTROL, 0x304); + + tmp = in_le32(priv->regbase + SIR_ICFG); + tmp &= ~SIR_CFG_GEN2EN; + out_le32(priv->regbase + SIR_ICFG, tmp); + + mv_reset_channel(port); + } + } + + debug("Failed to probe port\n"); + return -1; +} + +/* Get request queue in pointer */ +static int get_reqip(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK; + tmp = tmp >> EDMA_RQIPR_IPSHIFT; + + return tmp; +} + +static void set_reqip(int port, int reqin) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK; + tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK); + out_le32(priv->regbase + EDMA_RQIPR, tmp); +} + +/* Get next available slot, ignoring possible overwrite */ +static int get_next_reqip(int port) +{ + int slot = get_reqip(port); + slot = (slot + 1) % REQUEST_QUEUE_SIZE; + return slot; +} + +/* Get response queue in pointer */ +static int get_rspip(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK; + tmp = tmp >> EDMA_RSIPR_IPSHIFT; + + return tmp; +} + +/* Get response queue out pointer */ +static int get_rspop(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK; + tmp = tmp >> EDMA_RSOPR_OPSHIFT; + return tmp; +} + +/* Get next response queue pointer */ +static int get_next_rspop(int port) +{ + return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE; +} + +/* Set response queue pointer */ +static void set_rspop(int port, int reqin) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + u32 tmp; + + tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK; + tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK); + + out_le32(priv->regbase + EDMA_RSOPR, tmp); +} + +static int wait_dma_completion(int port, int index, u32 timeout_msec) +{ + u32 tmp, res; + + tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1; + res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp, + tmp, timeout_msec); + if (res) + printf("Failed to wait for completion on port %d\n", port); + + return res; +} + +static void process_responses(int port) +{ +#ifdef DEBUG + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; +#endif + u32 tmp; + u32 outind = get_rspop(port); + + /* Ack interrupts */ + tmp = in_le32(SATAHC_BASE + SATAHC_ICR); + if (port == 0) + tmp &= ~(BIT(0) | BIT(8)); + else + tmp &= ~(BIT(1) | BIT(9)); + tmp &= ~(BIT(4)); + out_le32(SATAHC_BASE + SATAHC_ICR, tmp); + + while (get_rspip(port) != outind) { +#ifdef DEBUG + debug("Response index %d flags %08x on port %d\n", outind, + priv->response[outind].flags, port); +#endif + outind = get_next_rspop(port); + set_rspop(port, outind); + } +} + +static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis, + u8 *buffer, u32 len, u32 iswrite) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + struct crqb *req; + int slot; + + if (len >= 64 * 1024) { + printf("We only support <64K transfers for now\n"); + return -1; + } + + /* Initialize request */ + slot = get_reqip(port); + memset(&priv->request[slot], 0, sizeof(struct crqb)); + req = &priv->request[slot]; + + req->dtb_low = (u32)buffer; + + /* Dont use PRDs */ + req->control_flags = CRQB_CNTRLFLAGS_PRDMODE; + req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR; + req->control_flags |= + ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT) + & CRQB_CNTRLFLAGS_PMPORTMASK); + + req->drb_count = len; + + req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) & + CRQB_CMDFEAT_CMDMASK; + req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) & + CRQB_CMDFEAT_FEATMASK; + + req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) & + CRQB_ADDR_LBA_LOWMASK; + req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) & + CRQB_ADDR_LBA_MIDMASK; + req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) & + CRQB_ADDR_LBA_HIGHMASK; + req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) & + CRQB_ADDR_DEVICE_MASK; + + req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) & + CRQB_ADDR_LBA_LOW_EXP_MASK; + req->ata_addr_exp |= + (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) & + CRQB_ADDR_LBA_MID_EXP_MASK; + req->ata_addr_exp |= + (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) & + CRQB_ADDR_LBA_HIGH_EXP_MASK; + req->ata_addr_exp |= + (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) & + CRQB_ADDR_FEATURE_EXP_MASK; + + req->ata_sect_count = + (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) & + CRQB_SECTCOUNT_COUNT_MASK; + req->ata_sect_count |= + (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) & + CRQB_SECTCOUNT_COUNT_EXP_MASK; + + /* Flush data */ + flush_dcache_range((u32)req, (u32)req + sizeof(*req)); + + /* Trigger operation */ + slot = get_next_reqip(port); + set_reqip(port, slot); + + /* Wait for completion */ + if (wait_dma_completion(port, slot, 10000)) { + printf("ATA operation timed out\n"); + return -1; + } + + process_responses(port); + + /* Invalidate data on read */ + if (buffer && len) + invalidate_dcache_range((u32)buffer, (u32)buffer + len); + + return len; +} + +static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt, + u8 *buffer, int is_write) +{ + struct sata_fis_h2d cfis; + u32 res; + u64 block; + + block = (u64)start; + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; + + cfis.lba_high_exp = (block >> 40) & 0xff; + cfis.lba_mid_exp = (block >> 32) & 0xff; + cfis.lba_low_exp = (block >> 24) & 0xff; + cfis.lba_high = (block >> 16) & 0xff; + cfis.lba_mid = (block >> 8) & 0xff; + cfis.lba_low = block & 0xff; + cfis.device = ATA_LBA; + cfis.sector_count_exp = (blkcnt >> 8) & 0xff; + cfis.sector_count = blkcnt & 0xff; + + res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt, + is_write); + + return res >= 0 ? blkcnt : res; +} + +static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer, + int is_write) +{ + struct sata_fis_h2d cfis; + lbaint_t block; + u32 res; + + block = start; + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; + cfis.device = ATA_LBA; + + cfis.device |= (block >> 24) & 0xf; + cfis.lba_high = (block >> 16) & 0xff; + cfis.lba_mid = (block >> 8) & 0xff; + cfis.lba_low = block & 0xff; + cfis.sector_count = (u8)(blkcnt & 0xff); + + res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt, + is_write); + + return res >= 0 ? blkcnt : res; +} + +static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer, int is_write) +{ + lbaint_t start, blks; + u8 *addr; + int max_blks; + + debug("%s: %ld %ld\n", __func__, blknr, blkcnt); + + start = blknr; + blks = blkcnt; + addr = (u8 *)buffer; + + max_blks = MV_ATA_MAX_SECTORS; + do { + if (blks > max_blks) { + if (sata_dev_desc[dev].lba48) { + mv_sata_rw_cmd_ext(dev, start, max_blks, addr, + is_write); + } else { + mv_sata_rw_cmd(dev, start, max_blks, addr, + is_write); + } + start += max_blks; + blks -= max_blks; + addr += ATA_SECT_SIZE * max_blks; + } else { + if (sata_dev_desc[dev].lba48) { + mv_sata_rw_cmd_ext(dev, start, blks, addr, + is_write); + } else { + mv_sata_rw_cmd(dev, start, blks, addr, + is_write); + } + start += blks; + blks = 0; + addr += ATA_SECT_SIZE * blks; + } + } while (blks != 0); + + return blkcnt; +} + +static int mv_ata_exec_ata_cmd_nondma(int port, + struct sata_fis_h2d *cfis, u8 *buffer, + u32 len, u32 iswrite) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + int i; + u16 *tp; + + debug("%s\n", __func__); + + out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count); + out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high); + out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid); + out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low); + out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features); + out_le32(priv->regbase + PIO_DEVICE, cfis->device); + out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command); + + if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS), + ATA_BUSY, 0x0, 10000)) { + debug("Failed to wait for completion\n"); + return -1; + } + + if (len > 0) { + tp = (u16 *)buffer; + for (i = 0; i < len / 2; i++) { + if (iswrite) + out_le16(priv->regbase + PIO_DATA, *tp++); + else + *tp++ = in_le16(priv->regbase + PIO_DATA); + } + } + + return len; +} + +static int mv_sata_identify(int port, u16 *id) +{ + struct sata_fis_h2d h2d; + + memset(&h2d, 0, sizeof(struct sata_fis_h2d)); + + h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + h2d.command = ATA_CMD_ID_ATA; + + /* Give device time to get operational */ + mdelay(10); + + return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id, + ATA_ID_WORDS * 2, READ_CMD); +} + +static void mv_sata_xfer_mode(int port, u16 *id) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + priv->pio = id[ATA_ID_PIO_MODES]; + priv->mwdma = id[ATA_ID_MWDMA_MODES]; + priv->udma = id[ATA_ID_UDMA_MODES]; + debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma, + priv->udma); +} + +static void mv_sata_set_features(int port) +{ + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + struct sata_fis_h2d cfis; + u8 udma_cap; + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = ATA_CMD_SET_FEATURES; + cfis.features = SETFEATURES_XFER; + + /* First check the device capablity */ + udma_cap = (u8) (priv->udma & 0xff); + + if (udma_cap == ATA_UDMA6) + cfis.sector_count = XFER_UDMA_6; + if (udma_cap == ATA_UDMA5) + cfis.sector_count = XFER_UDMA_5; + if (udma_cap == ATA_UDMA4) + cfis.sector_count = XFER_UDMA_4; + if (udma_cap == ATA_UDMA3) + cfis.sector_count = XFER_UDMA_3; + + mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD); +} + +int mv_sata_spin_down(int dev) +{ + struct sata_fis_h2d cfis; + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv; + + if (priv->link == 0) { + debug("No device on port: %d\n", dev); + return 1; + } + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = ATA_CMD_STANDBY; + + return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD); +} + +int mv_sata_spin_up(int dev) +{ + struct sata_fis_h2d cfis; + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv; + + if (priv->link == 0) { + debug("No device on port: %d\n", dev); + return 1; + } + + memset(&cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis.command = ATA_CMD_IDLE; + + return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD); +} + +ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) +{ + return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD); +} + +ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) +{ + return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD); +} + +/* + * Initialize SATA memory windows + */ +static void mvsata_ide_conf_mbus_windows(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + /* Disable windows, Set Size/Base to 0 */ + for (i = 0; i < 4; i++) { + writel(0, MVSATA_WIN_CONTROL(i)); + writel(0, MVSATA_WIN_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + MVSATA_WIN_CONTROL(i)); + writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); + } +} + +int init_sata(int dev) +{ + struct mv_priv *priv; + + debug("Initialize sata dev: %d\n", dev); + + if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) { + printf("Invalid sata device %d\n", dev); + return -1; + } + + priv = (struct mv_priv *)malloc(sizeof(struct mv_priv)); + if (!priv) { + printf("Failed to allocate memory for private sata data\n"); + return -ENOMEM; + } + + memset((void *)priv, 0, sizeof(struct mv_priv)); + + /* Allocate and align request buffer */ + priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE + + CRQB_ALIGN); + if (!priv->crqb_alloc) { + printf("Unable to allocate memory for request queue\n"); + return -ENOMEM; + } + memset(priv->crqb_alloc, 0, + sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN); + priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) & + ~(CRQB_ALIGN - 1)); + + /* Allocate and align response buffer */ + priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE + + CRPB_ALIGN); + if (!priv->crpb_alloc) { + printf("Unable to allocate memory for response queue\n"); + return -ENOMEM; + } + memset(priv->crpb_alloc, 0, + sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN); + priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) & + ~(CRPB_ALIGN - 1)); + + sata_dev_desc[dev].priv = (void *)priv; + + sprintf(priv->name, "SATA%d", dev); + + priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE; + + if (!hw_init) { + debug("Initialize sata hw\n"); + hw_init = 1; + mv_reset_one_hc(); + mvsata_ide_conf_mbus_windows(); + } + + mv_reset_port(dev); + + if (probe_port(dev)) { + priv->link = 0; + return -ENODEV; + } + priv->link = 1; + + return 0; +} + +int reset_sata(int dev) +{ + return 0; +} + +int scan_sata(int port) +{ + unsigned char serial[ATA_ID_SERNO_LEN + 1]; + unsigned char firmware[ATA_ID_FW_REV_LEN + 1]; + unsigned char product[ATA_ID_PROD_LEN + 1]; + u64 n_sectors; + u16 *id; + struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; + + if (!priv->link) + return -ENODEV; + + id = (u16 *)malloc(ATA_ID_WORDS * 2); + if (!id) { + printf("Failed to malloc id data\n"); + return -ENOMEM; + } + + mv_sata_identify(port, id); + ata_swap_buf_le16(id, ATA_ID_WORDS); +#ifdef DEBUG + ata_dump_id(id); +#endif + + /* Serial number */ + ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); + memcpy(sata_dev_desc[port].product, serial, sizeof(serial)); + + /* Firmware version */ + ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); + memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware)); + + /* Product model */ + ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); + memcpy(sata_dev_desc[port].vendor, product, sizeof(product)); + + /* Total sectors */ + n_sectors = ata_id_n_sectors(id); + sata_dev_desc[port].lba = n_sectors; + + /* Check if support LBA48 */ + if (ata_id_has_lba48(id)) { + sata_dev_desc[port].lba48 = 1; + debug("Device support LBA48\n"); + } + + /* Get the NCQ queue depth from device */ + priv->queue_depth = ata_id_queue_depth(id); + + /* Get the xfer mode from device */ + mv_sata_xfer_mode(port, id); + + /* Set the xfer mode to highest speed */ + mv_sata_set_features(port); + + /* Start up */ + mv_start_edma_engine(port); + + return 0; +} diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c index fdf75b5abf..b974e80167 100644 --- a/drivers/block/systemace.c +++ b/drivers/block/systemace.c @@ -69,8 +69,9 @@ static u16 ace_readw(unsigned off) return in16(base + off); } -static unsigned long systemace_read(int dev, unsigned long start, - lbaint_t blkcnt, void *buffer); +static unsigned long systemace_read(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + void *buffer); static block_dev_desc_t systemace_dev = { 0 }; @@ -136,8 +137,9 @@ block_dev_desc_t *systemace_get_dev(int dev) * the dev_desc) to read blocks of data. The return value is the * number of blocks read. A zero return indicates an error. */ -static unsigned long systemace_read(int dev, unsigned long start, - lbaint_t blkcnt, void *buffer) +static unsigned long systemace_read(block_dev_desc_t *block_dev, + unsigned long start, lbaint_t blkcnt, + void *buffer) { int retry; unsigned blk_countdown; diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index f332480e1d..c5c9d2a42e 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -60,6 +60,15 @@ config DM_SEQ_ALIAS help Most boards will have a '/aliases' node containing the path to numbered devices (e.g. serial0 = &serial0). This feature can be + disabled if it is not required. + +config SPL_DM_SEQ_ALIAS + bool "Support numbered aliases in device tree in SPL" + depends on DM + default n + help + Most boards will have a '/aliases' node containing the path to + numbered devices (e.g. serial0 = &serial0). This feature can be disabled if it is not required, to save code space in SPL. config REGMAP diff --git a/drivers/core/device.c b/drivers/core/device.c index 758f39064c..818d03fac1 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -64,7 +64,7 @@ int device_bind(struct udevice *parent, const struct driver *drv, dev->seq = -1; dev->req_seq = -1; - if (CONFIG_IS_ENABLED(OF_CONTROL) && IS_ENABLED(CONFIG_DM_SEQ_ALIAS)) { + if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS)) { /* * Some devices, such as a SPI bus, I2C bus and serial ports * are numbered using aliases. @@ -581,38 +581,65 @@ const char *dev_get_uclass_name(struct udevice *dev) return dev->uclass->uc_drv->name; } -fdt_addr_t dev_get_addr(struct udevice *dev) +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index) { #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr; if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { const fdt32_t *reg; + int len = 0; + int na, ns; + + na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset); + if (na < 1) { + debug("bad #address-cells\n"); + return FDT_ADDR_T_NONE; + } + + ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset); + if (ns < 0) { + debug("bad #size-cells\n"); + return FDT_ADDR_T_NONE; + } - reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL); - if (!reg) + reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) { + debug("Req index out of range\n"); return FDT_ADDR_T_NONE; + } + + reg += index * (na + ns); /* * Use the full-fledged translate function for complex * bus setups. */ - return fdt_translate_address((void *)gd->fdt_blob, + addr = fdt_translate_address((void *)gd->fdt_blob, dev->of_offset, reg); + } else { + /* + * Use the "simple" translate function for less complex + * bus setups. + */ + addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, + dev->parent->of_offset, + dev->of_offset, "reg", + index, NULL); + if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { + if (device_get_uclass_id(dev->parent) == + UCLASS_SIMPLE_BUS) + addr = simple_bus_translate(dev->parent, addr); + } } /* - * Use the "simple" translate function for less complex - * bus setups. + * Some platforms need a special address translation. Those + * platforms (e.g. mvebu in SPL) can configure a translation + * offset in the DM by calling dm_set_translation_offset() that + * will get added to all addresses returned by dev_get_addr(). */ - addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, - dev->parent->of_offset, - dev->of_offset, "reg", - 0, NULL); - if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { - if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) - addr = simple_bus_translate(dev->parent, addr); - } + addr += dm_get_translation_offset(); return addr; #else @@ -620,6 +647,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev) #endif } +fdt_addr_t dev_get_addr(struct udevice *dev) +{ + return dev_get_addr_index(dev, 0); +} + bool device_has_children(struct udevice *dev) { return !list_empty(&dev->child_head); diff --git a/drivers/core/root.c b/drivers/core/root.c index e7b1f24968..13c2713e61 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -23,6 +23,10 @@ DECLARE_GLOBAL_DATA_PTR; +struct root_priv { + fdt_addr_t translation_offset; /* optional translation offset */ +}; + static const struct driver_info root_info = { .name = "root_driver", }; @@ -37,6 +41,22 @@ struct udevice *dm_root(void) return gd->dm_root; } +fdt_addr_t dm_get_translation_offset(void) +{ + struct udevice *root = dm_root(); + struct root_priv *priv = dev_get_priv(root); + + return priv->translation_offset; +} + +void dm_set_translation_offset(fdt_addr_t offs) +{ + struct udevice *root = dm_root(); + struct root_priv *priv = dev_get_priv(root); + + priv->translation_offset = offs; +} + #if defined(CONFIG_NEEDS_MANUAL_RELOC) void fix_drivers(void) { @@ -228,6 +248,7 @@ int dm_init_and_scan(bool pre_reloc_only) U_BOOT_DRIVER(root_driver) = { .name = "root_driver", .id = UCLASS_ROOT, + .priv_auto_alloc_size = sizeof(struct root_priv), }; /* This is the root uclass */ diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 1d72bc569e..12b5b04109 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -165,21 +165,6 @@ int ddr3_tip_init_config_func(u32 dev_num, } /* - * Read training result table - */ -int hws_ddr3_tip_read_training_result( - u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) -{ - dev_num = dev_num; - - if (result == NULL) - return MV_BAD_PARAM; - memcpy(result, training_result, sizeof(result)); - - return MV_OK; -} - -/* * Get training result info pointer */ enum hws_result *ddr3_tip_get_result_ptr(u32 stage) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h index 76a1b6a06d..ed92873697 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h @@ -171,8 +171,6 @@ int hws_ddr3_tip_load_topology_map(u32 dev_num, struct hws_topology_map *topology); int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type); int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info); -int hws_ddr3_tip_read_training_result(u32 dev_num, - enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]); int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode); u8 ddr3_tip_get_buf_min(u8 *buf_ptr); u8 ddr3_tip_get_buf_max(u8 *buf_ptr); diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index d9e33f7c6e..75d315a35e 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -33,7 +33,10 @@ #define SAR1_CPU_CORE_MASK 0x00000018 #define SAR1_CPU_CORE_OFFSET 3 +/* Only enable ECC if the board selects it */ +#ifdef CONFIG_BOARD_ECC_SUPPORT #define ECC_SUPPORT +#endif #define NEW_FABRIC_TWSI_ADDR 0x4E #ifdef CONFIG_DB_784MP_GP #define BUS_WIDTH_ECC_TWSI_ADDR 0x4E diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index a6720442ff..8549fe8bab 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -44,9 +44,14 @@ * DDR3_TRAINING_DEBUG - Debug prints of internal code */ #define DDR_TARGET_FABRIC 5 +/* Only enable ECC if the board selects it */ +#ifdef CONFIG_BOARD_ECC_SUPPORT #define DRAM_ECC 1 +#else +#define DRAM_ECC 0 +#endif -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT #define BUS_WIDTH 32 #else #define BUS_WIDTH 64 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h index 2c0e9075e9..71794ad312 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h @@ -8,9 +8,9 @@ #define __AXP_MC_STATIC_H MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -66,9 +66,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -124,9 +124,9 @@ MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /* MV_DDR_64BIT */ +#else /* CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B840}, /*Dunit Control Low Register */ @@ -176,9 +176,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B040}, /*Dunit Control Low Register */ @@ -233,9 +233,9 @@ MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */ #endif diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c b/drivers/ddr/marvell/axp/ddr3_write_leveling.c index df3a3df4a6..da384f321c 100644 --- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c +++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c @@ -22,6 +22,8 @@ DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n") #ifdef MV_DEBUG_WL +#define DEBUG_WL_S(s) puts(s) +#define DEBUG_WL_D(d, l) printf("%x", d) #define DEBUG_RL_S(s) \ debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s) #define DEBUG_RL_D(d, l) \ @@ -1229,8 +1231,6 @@ static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, DEBUG_WL_FULL_D((u32) phase, 1); DEBUG_WL_FULL_S(", Delay = "); DEBUG_WL_FULL_D((u32) delay, 1); - DEBUG_WL_FULL_S(", Counter = "); - DEBUG_WL_FULL_D((u32) i, 1); DEBUG_WL_FULL_S("\n"); /* Drive DQS high for one cycle - All data PUPs */ diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 5a9fb4a6e2..395d472e0b 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -20,23 +20,6 @@ static unsigned char *dfu_file_buf; static long dfu_file_buf_len; static long dfu_file_buf_filled; -static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part) -{ - int ret; - - if (part == mmc->part_num) - return 0; - - ret = mmc_switch_part(dfu->data.mmc.dev_num, part); - if (ret) { - error("Cannot switch to partition %d\n", part); - return ret; - } - mmc->part_num = part; - - return 0; -} - static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { @@ -66,8 +49,9 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, } if (dfu->data.mmc.hw_partition >= 0) { - part_num_bkp = mmc->part_num; - ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition); + part_num_bkp = mmc->block_dev.hwpart; + ret = mmc_select_hwpart(dfu->data.mmc.dev_num, + dfu->data.mmc.hw_partition); if (ret) return ret; } @@ -77,11 +61,11 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, dfu->data.mmc.dev_num, blk_start, blk_count, buf); switch (op) { case DFU_OP_READ: - n = mmc->block_dev.block_read(dfu->data.mmc.dev_num, blk_start, + n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_count, buf); break; case DFU_OP_WRITE: - n = mmc->block_dev.block_write(dfu->data.mmc.dev_num, blk_start, + n = mmc->block_dev.block_write(&mmc->block_dev, blk_start, blk_count, buf); break; default: @@ -91,12 +75,12 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, if (n != blk_count) { error("MMC operation failed"); if (dfu->data.mmc.hw_partition >= 0) - mmc_access_part(dfu, mmc, part_num_bkp); + mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp); return -EIO; } if (dfu->data.mmc.hw_partition >= 0) { - ret = mmc_access_part(dfu, mmc, part_num_bkp); + ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp); if (ret) return ret; } diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index f20d1b2291..5dc4fbba1f 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -20,7 +20,7 @@ #if defined(CONFIG_ORION5X) #include <asm/arch/orion5x.h> -#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP)) +#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) #include <asm/arch/soc.h> #elif defined(CONFIG_SUNXI) #include <asm/arch/i2c.h> diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index b1cb4b3534..301d9b3ab9 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -38,7 +38,8 @@ void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst) blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; - err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst); + err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, + vdst); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); hang(); @@ -85,7 +86,8 @@ void __noreturn mmc_boot(void) /* * Read source addr from sd card */ - err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); + err = mmc->block_dev.block_read(&mmc->block_dev, + CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); if (err != 1) { puts("spl: mmc read failed!!\n"); free(tmp_buf); @@ -126,7 +128,7 @@ void __noreturn mmc_boot(void) #endif blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; - err = mmc->block_dev.block_read(0, blk_start, blk_cnt, + err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 3a34028c91..e6028d503f 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -234,8 +234,11 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, return blkcnt; } -static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) +static ulong mmc_bread(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, void *dst) { + int dev_num = block_dev->dev; + int err; lbaint_t cur, blocks_todo = blkcnt; if (blkcnt == 0) @@ -245,6 +248,10 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) if (!mmc) return 0; + err = mmc_select_hwpart(dev_num, block_dev->hwpart); + if (err < 0) + return 0; + if ((start + blkcnt) > mmc->block_dev.lba) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", @@ -579,7 +586,7 @@ int mmc_select_hwpart(int dev_num, int hwpart) if (!mmc) return -ENODEV; - if (mmc->part_num == hwpart) + if (mmc->block_dev.hwpart == hwpart) return 0; if (mmc->part_config == MMCPART_NOAVAILABLE) { @@ -591,8 +598,6 @@ int mmc_select_hwpart(int dev_num, int hwpart) if (ret) return ret; - mmc->part_num = hwpart; - return 0; } @@ -613,8 +618,10 @@ int mmc_switch_part(int dev_num, unsigned int part_num) * Set the capacity if the switch succeeded or was intended * to return to representing the raw device. */ - if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) + if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { ret = mmc_set_capacity(mmc, part_num); + mmc->block_dev.hwpart = part_num; + } return ret; } @@ -1324,7 +1331,7 @@ static int mmc_startup(struct mmc *mmc) mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; } - err = mmc_set_capacity(mmc, mmc->part_num); + err = mmc_set_capacity(mmc, mmc->block_dev.hwpart); if (err) return err; @@ -1465,6 +1472,7 @@ static int mmc_startup(struct mmc *mmc) /* fill in device description */ mmc->block_dev.lun = 0; + mmc->block_dev.hwpart = 0; mmc->block_dev.type = 0; mmc->block_dev.blksz = mmc->read_bl_len; mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); @@ -1624,7 +1632,7 @@ int mmc_start_init(struct mmc *mmc) return err; /* The internal partition reset to user partition(0) at every CMD0*/ - mmc->part_num = 0; + mmc->block_dev.hwpart = 0; /* Test for SD version 2 */ err = mmc_send_if_cond(mmc); diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 447a7001db..6a7063976c 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -22,23 +22,24 @@ void mmc_adapter_card_type_ident(void); #ifndef CONFIG_SPL_BUILD -extern unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt); +unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt); -extern ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, - const void *src); +unsigned long mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, const void *src); #else /* CONFIG_SPL_BUILD */ /* SPL will never write or erase, declare dummies to reduce code size. */ -static inline unsigned long mmc_berase(int dev_num, lbaint_t start, - lbaint_t blkcnt) +static inline unsigned long mmc_berase(block_dev_desc_t *block_dev, + lbaint_t start, lbaint_t blkcnt) { return 0; } -static inline ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, - const void *src) +static inline ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt, const void *src) { return 0; } diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index 221bf306cc..79b8c4d808 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -65,8 +65,10 @@ err_out: return err; } -unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt) +unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start, + lbaint_t blkcnt) { + int dev_num = block_dev->dev; int err = 0; u32 start_rem, blkcnt_rem; struct mmc *mmc = find_mmc_device(dev_num); @@ -76,6 +78,10 @@ unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt) if (!mmc) return -1; + err = mmc_select_hwpart(dev_num, block_dev->hwpart); + if (err < 0) + return -1; + /* * We want to see if the requested start or total block count are * unaligned. We discard the whole numbers and only care about the @@ -165,14 +171,21 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, return blkcnt; } -ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src) +ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt, + const void *src) { + int dev_num = block_dev->dev; lbaint_t cur, blocks_todo = blkcnt; + int err; struct mmc *mmc = find_mmc_device(dev_num); if (!mmc) return 0; + err = mmc_select_hwpart(dev_num, block_dev->hwpart); + if (err < 0) + return 0; + if (mmc_set_blocklen(mmc, mmc->write_bl_len)) return 0; diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 37171bfa71..5fb71518c4 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -11,26 +11,25 @@ #include <sdhci.h> #include <asm/pci.h> -int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported, - int num_ids) +int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported) { struct sdhci_host *mmc_host; - pci_dev_t devbusfn; u32 iobase; int ret; int i; - for (i = 0; i < num_ids; i++) { - devbusfn = pci_find_devices(mmc_supported, i); - if (devbusfn == -1) - return -ENODEV; + for (i = 0; ; i++) { + struct udevice *dev; + ret = pci_find_device_id(mmc_supported, i, &dev); + if (ret) + return ret; mmc_host = malloc(sizeof(struct sdhci_host)); if (!mmc_host) return -ENOMEM; mmc_host->name = (char *)name; - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); mmc_host->ioaddr = (void *)iobase; mmc_host->quirks = 0; ret = add_sdhci(mmc_host, 0, 0); diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index e717c44216..7b33094d84 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -454,7 +454,7 @@ int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc) panic("Failed to allocate memory\n"); if (mmc_getcd(mmc) && mmc_init(mmc) == 0 && - mmc->block_dev.block_read(mmc->block_dev.dev, 16, 1, buf) == 1 && + mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 && strncmp(&buf[4], "eGON.BT0", 8) == 0) valid_signature = 1; diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 72e0f6b3fb..95ffad476d 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -46,7 +46,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, void spi_flash_free(struct spi_flash *flash) { - spi_flash_remove(flash->spi->dev); + device_remove(flash->spi->dev); } int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, @@ -69,11 +69,6 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, return 0; } -int spi_flash_remove(struct udevice *dev) -{ - return device_remove(dev); -} - static int spi_flash_post_bind(struct udevice *dev) { #if defined(CONFIG_NEEDS_MANUAL_RELOC) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index ed5c391dc2..007a5a085c 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -16,18 +16,18 @@ /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ enum spi_dual_flash { SF_SINGLE_FLASH = 0, - SF_DUAL_STACKED_FLASH = 1 << 0, - SF_DUAL_PARALLEL_FLASH = 1 << 1, + SF_DUAL_STACKED_FLASH = BIT(0), + SF_DUAL_PARALLEL_FLASH = BIT(1), }; /* Enum list - Full read commands */ enum spi_read_cmds { - ARRAY_SLOW = 1 << 0, - ARRAY_FAST = 1 << 1, - DUAL_OUTPUT_FAST = 1 << 2, - DUAL_IO_FAST = 1 << 3, - QUAD_OUTPUT_FAST = 1 << 4, - QUAD_IO_FAST = 1 << 5, + ARRAY_SLOW = BIT(0), + ARRAY_FAST = BIT(1), + DUAL_OUTPUT_FAST = BIT(2), + QUAD_OUTPUT_FAST = BIT(3), + DUAL_IO_FAST = BIT(4), + QUAD_IO_FAST = BIT(5), }; /* Normal - Extended - Full command set */ @@ -37,20 +37,20 @@ enum spi_read_cmds { /* sf param flags */ enum { -#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS - SECT_4K = 1 << 0, +#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS + SECT_4K = 0, #else - SECT_4K = 0 << 0, + SECT_4K = BIT(0), #endif - SECT_32K = 1 << 1, - E_FSR = 1 << 2, - SST_WR = 1 << 3, - WR_QPP = 1 << 4, + SECT_32K = BIT(1), + E_FSR = BIT(2), + SST_WR = BIT(3), + WR_QPP = BIT(4), }; enum spi_nor_option_flags { - SNOR_F_SST_WR = (1 << 0), - SNOR_F_USE_FSR = (1 << 1), + SNOR_F_SST_WR = BIT(0), + SNOR_F_USE_FSR = BIT(1), }; #define SPI_FLASH_3B_ADDR_LEN 3 @@ -75,12 +75,9 @@ enum spi_nor_option_flags { #define CMD_WRITE_STATUS 0x01 #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 -#define CMD_READ_STATUS 0x05 -#define CMD_QUAD_PAGE_PROGRAM 0x32 -#define CMD_READ_STATUS1 0x35 #define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_CONFIG 0x35 -#define CMD_FLAG_STATUS 0x70 +#define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -90,6 +87,11 @@ enum spi_nor_option_flags { #define CMD_READ_QUAD_OUTPUT_FAST 0x6b #define CMD_READ_QUAD_IO_FAST 0xeb #define CMD_READ_ID 0x9f +#define CMD_READ_STATUS 0x05 +#define CMD_READ_STATUS1 0x35 +#define CMD_READ_CONFIG 0x35 +#define CMD_FLAG_STATUS 0x70 +#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -100,10 +102,11 @@ enum spi_nor_option_flags { #endif /* Common status */ -#define STATUS_WIP (1 << 0) -#define STATUS_QEB_WINSPAN (1 << 1) -#define STATUS_QEB_MXIC (1 << 6) -#define STATUS_PEC (1 << 7) +#define STATUS_WIP BIT(0) +#define STATUS_QEB_WINSPAN BIT(1) +#define STATUS_QEB_MXIC BIT(6) +#define STATUS_PEC BIT(7) +#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 0cafc29123..daa1d5b249 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -128,7 +128,7 @@ static int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len, #if defined(CONFIG_SPI_FLASH_SST) if (flash->flags & SNOR_F_SST_WR) { - if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + if (flash->spi->mode & SPI_TX_BYTE) return sst_write_bp(flash, offset, len, buf); else return sst_write_wp(flash, offset, len, buf); diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index b7b7f0044e..a567414669 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -29,16 +29,6 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -/* Read commands array */ -static u8 spi_read_cmds_array[] = { - CMD_READ_ARRAY_SLOW, - CMD_READ_ARRAY_FAST, - CMD_READ_DUAL_OUTPUT_FAST, - CMD_READ_DUAL_IO_FAST, - CMD_READ_QUAD_OUTPUT_FAST, - CMD_READ_QUAD_IO_FAST, -}; - static int read_sr(struct spi_flash *flash, u8 *rs) { int ret; @@ -121,6 +111,37 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int read_evcr(struct spi_flash *flash, u8 *evcr) +{ + int ret; + const u8 cmd = CMD_READ_EVCR; + + ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); + if (ret < 0) { + debug("SF: error reading EVCR\n"); + return ret; + } + + return 0; +} + +static int write_evcr(struct spi_flash *flash, u8 evcr) +{ + u8 cmd; + int ret; + + cmd = CMD_WRITE_EVCR; + ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); + if (ret < 0) { + debug("SF: error while writing EVCR register\n"); + return ret; + } + + return 0; +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) { @@ -149,7 +170,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) int ret; if (flash->size <= SPI_FLASH_16MB_BOUN) - goto bank_end; + goto bar_end; switch (idcode0) { case SPI_FLASH_CFI_MFR_SPANSION: @@ -168,7 +189,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) return ret; } -bank_end: +bar_end: flash->bank_curr = curr_bank; return 0; } @@ -177,13 +198,15 @@ bank_end: #ifdef CONFIG_SF_DUAL_FLASH static void spi_flash_dual(struct spi_flash *flash, u32 *addr) { + struct spi_slave *spi = flash->spi; + switch (flash->dual_flash) { case SF_DUAL_STACKED_FLASH: if (*addr >= (flash->size >> 1)) { *addr -= flash->size >> 1; - flash->spi->flags |= SPI_XFER_U_PAGE; + spi->flags |= SPI_XFER_U_PAGE; } else { - flash->spi->flags &= ~SPI_XFER_U_PAGE; + spi->flags &= ~SPI_XFER_U_PAGE; } break; case SF_DUAL_PARALLEL_FLASH: @@ -268,7 +291,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, if (buf == NULL) timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: unable to claim SPI bus\n"); return ret; @@ -353,6 +376,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { + struct spi_slave *spi = flash->spi; unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; @@ -385,9 +409,9 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, byte_addr = offset % page_size; chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); - if (flash->spi->max_write_size) + if (spi->max_write_size) chunk_len = min(chunk_len, - (size_t)flash->spi->max_write_size); + (size_t)spi->max_write_size); spi_flash_addr(write_addr, cmd); @@ -413,7 +437,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, struct spi_slave *spi = flash->spi; int ret; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: unable to claim SPI bus\n"); return ret; @@ -438,6 +462,7 @@ void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { + struct spi_slave *spi = flash->spi; u8 *cmd, cmdsz; u32 remain_len, read_len, read_addr; int bank_sel = 0; @@ -445,15 +470,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, /* Handle memory-mapped SPI */ if (flash->memory_map) { - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: unable to claim SPI bus\n"); return ret; } - spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP); + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); spi_flash_copy_mmap(data, flash->memory_map + offset, len); - spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END); - spi_release_bus(flash->spi); + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); + spi_release_bus(spi); return 0; } @@ -505,6 +530,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, #ifdef CONFIG_SPI_FLASH_SST static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) { + struct spi_slave *spi = flash->spi; int ret; u8 cmd[4] = { CMD_SST_BP, @@ -514,13 +540,13 @@ static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) }; debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); + spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); ret = spi_flash_cmd_write_enable(flash); if (ret) return ret; - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); + ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); if (ret) return ret; @@ -530,11 +556,12 @@ static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { + struct spi_slave *spi = flash->spi; size_t actual, cmd_len; int ret; u8 cmd[4]; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: Unable to claim SPI bus\n"); return ret; @@ -561,10 +588,10 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, for (; actual < len - 1; actual += 2) { debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, + spi_w8r8(spi, CMD_READ_STATUS), buf + actual, cmd[0], offset); - ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, + ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf + actual, 2); if (ret) { debug("SF: sst word program failed\n"); @@ -590,17 +617,18 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, debug("SF: sst: program %s %zu bytes @ 0x%zx\n", ret ? "failure" : "success", len, offset - actual); - spi_release_bus(flash->spi); + spi_release_bus(spi); return ret; } int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { + struct spi_slave *spi = flash->spi; size_t actual; int ret; - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(spi); if (ret) { debug("SF: Unable to claim SPI bus\n"); return ret; @@ -621,7 +649,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, debug("SF: sst: program %s %zu bytes @ 0x%zx\n", ret ? "failure" : "success", len, offset - actual); - spi_release_bus(flash->spi); + spi_release_bus(spi); return ret; } #endif @@ -803,7 +831,7 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) #ifdef CONFIG_SPI_FLASH_MACRONIX -static int spi_flash_set_qeb_mxic(struct spi_flash *flash) +static int macronix_quad_enable(struct spi_flash *flash) { u8 qeb_status; int ret; @@ -812,12 +840,18 @@ static int spi_flash_set_qeb_mxic(struct spi_flash *flash) if (ret < 0) return ret; - if (qeb_status & STATUS_QEB_MXIC) { - debug("SF: mxic: QEB is already set\n"); - } else { - ret = write_sr(flash, STATUS_QEB_MXIC); - if (ret < 0) - return ret; + if (qeb_status & STATUS_QEB_MXIC) + return 0; + + ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC); + if (ret < 0) + return ret; + + /* read SR and check it */ + ret = read_sr(flash, &qeb_status); + if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) { + printf("SF: Macronix SR Quad bit not clear\n"); + return -EINVAL; } return ret; @@ -825,7 +859,7 @@ static int spi_flash_set_qeb_mxic(struct spi_flash *flash) #endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) -static int spi_flash_set_qeb_winspan(struct spi_flash *flash) +static int spansion_quad_enable(struct spi_flash *flash) { u8 qeb_status; int ret; @@ -834,34 +868,67 @@ static int spi_flash_set_qeb_winspan(struct spi_flash *flash) if (ret < 0) return ret; - if (qeb_status & STATUS_QEB_WINSPAN) { - debug("SF: winspan: QEB is already set\n"); - } else { - ret = write_cr(flash, STATUS_QEB_WINSPAN); - if (ret < 0) - return ret; + if (qeb_status & STATUS_QEB_WINSPAN) + return 0; + + ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN); + if (ret < 0) + return ret; + + /* read CR and check it */ + ret = read_cr(flash, &qeb_status); + if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) { + printf("SF: Spansion CR Quad bit not clear\n"); + return -EINVAL; + } + + return ret; +} +#endif + +#ifdef CONFIG_SPI_FLASH_STMICRO +static int micron_quad_enable(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_evcr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (!(qeb_status & STATUS_QEB_MICRON)) + return 0; + + ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); + if (ret < 0) + return ret; + + /* read EVCR and check it */ + ret = read_evcr(flash, &qeb_status); + if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) { + printf("SF: Micron EVCR Quad bit not clear\n"); + return -EINVAL; } return ret; } #endif -static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) +static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { #ifdef CONFIG_SPI_FLASH_MACRONIX case SPI_FLASH_CFI_MFR_MACRONIX: - return spi_flash_set_qeb_mxic(flash); + return macronix_quad_enable(flash); #endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) case SPI_FLASH_CFI_MFR_SPANSION: case SPI_FLASH_CFI_MFR_WINBOND: - return spi_flash_set_qeb_winspan(flash); + return spansion_quad_enable(flash); #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); @@ -902,9 +969,15 @@ int spi_flash_scan(struct spi_flash *flash) struct spi_slave *spi = flash->spi; const struct spi_flash_params *params; u16 jedec, ext_jedec; - u8 idcode[5]; - u8 cmd; + u8 cmd, idcode[5]; int ret; + static u8 spi_read_cmds_array[] = { + CMD_READ_ARRAY_SLOW, + CMD_READ_ARRAY_FAST, + CMD_READ_DUAL_OUTPUT_FAST, + CMD_READ_QUAD_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, + CMD_READ_QUAD_IO_FAST }; /* Read the ID codes */ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); @@ -950,7 +1023,7 @@ int spi_flash_scan(struct spi_flash *flash) /* Assign spi data */ flash->name = params->name; flash->memory_map = spi->memory_map; - flash->dual_flash = flash->spi->option; + flash->dual_flash = spi->option; /* Assign spi flash flags */ if (params->flags & SST_WR) @@ -961,7 +1034,7 @@ int spi_flash_scan(struct spi_flash *flash) flash->write = spi_flash_cmd_write_ops; #if defined(CONFIG_SPI_FLASH_SST) if (flash->flags & SNOR_F_SST_WR) { - if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + if (spi->mode & SPI_TX_BYTE) flash->write = sst_write_bp; else flash->write = sst_write_wp; @@ -1025,7 +1098,7 @@ int spi_flash_scan(struct spi_flash *flash) flash->sector_size = flash->erase_size; /* Look for the fastest read cmd */ - cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); + cmd = fls(params->e_rd_cmd & spi->mode_rx); if (cmd) { cmd = spi_read_cmds_array[cmd - 1]; flash->read_cmd = cmd; @@ -1035,7 +1108,7 @@ int spi_flash_scan(struct spi_flash *flash) } /* Not require to look for fastest only two write cmds yet */ - if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) + if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD) flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; else /* Go for default supported write cmd */ @@ -1045,7 +1118,7 @@ int spi_flash_scan(struct spi_flash *flash) if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { - ret = spi_flash_set_qeb(flash, idcode[0]); + ret = set_quad_mode(flash, idcode[0]); if (ret) { debug("SF: Fail to set QEB for %02x\n", idcode[0]); return -EINVAL; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 04114a1244..0fccbc0040 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -584,7 +584,7 @@ static int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in platdata before we probe the hardware. */ if (device_is_on_pci_bus(dev)) { - pci_dev_t bdf = pci_get_bdf(dev); + pci_dev_t bdf = dm_pci_get_bdf(dev); dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 6124bf0ab3..70fc02ee5c 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -551,43 +551,6 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->use_eerd = true; eeprom->use_eewr = false; break; - - /* ich8lan does not support currently. if needed, please - * add corresponding code and functions. - */ -#if 0 - case e1000_ich8lan: - { - int32_t i = 0; - - eeprom->type = e1000_eeprom_ich8; - eeprom->use_eerd = false; - eeprom->use_eewr = false; - eeprom->word_size = E1000_SHADOW_RAM_WORDS; - uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, - ICH_FLASH_GFPREG); - /* Zero the shadow RAM structure. But don't load it from NVM - * so as to save time for driver init */ - if (hw->eeprom_shadow_ram != NULL) { - for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = false; - hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; - } - } - - hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * - ICH_FLASH_SECTOR_SIZE; - - hw->flash_bank_size = ((flash_size >> 16) - & ICH_GFPREG_BASE_MASK) + 1; - hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); - - hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; - - hw->flash_bank_size /= 2 * sizeof(uint16_t); - break; - } -#endif default: break; } @@ -838,14 +801,6 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, if (eeprom->use_eerd == true) return e1000_read_eeprom_eerd(hw, offset, words, data); - /* ich8lan does not support currently. if needed, please - * add corresponding code and functions. - */ -#if 0 - /* ICH EEPROM access is done via the ICH flash controller */ - if (eeprom->type == e1000_eeprom_ich8) - return e1000_read_eeprom_ich8(hw, offset, words, data); -#endif /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have * acquired the EEPROM at this point, so any returns should relase it */ if (eeprom->type == e1000_eeprom_spi) { @@ -1732,17 +1687,7 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) * occuring when accessing our register space */ E1000_WRITE_FLUSH(hw); } -#if 0 - /* Set the PCI priority bit correctly in the CTRL register. This - * determines if the adapter gives priority to receives, or if it - * gives equal priority to transmits and receives. Valid only on - * 82542 and 82543 silicon. - */ - if (hw->dma_fairness && hw->mac_type <= e1000_82543) { - ctrl = E1000_READ_REG(hw, CTRL); - E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); - } -#endif + switch (hw->mac_type) { case e1000_82545_rev_3: case e1000_82546_rev_3: @@ -1842,20 +1787,6 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) break; } -#if 0 - /* Clear all of the statistics registers (clear on read). It is - * important that we do this after we have tried to establish link - * because the symbol error count will increment wildly if there - * is no link. - */ - e1000_clear_hw_cntrs(hw); - - /* ICH8 No-snoop bits are opposite polarity. - * Set to snoop by default after reset. */ - if (hw->mac_type == e1000_ich8lan) - e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); -#endif - if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); @@ -5230,10 +5161,6 @@ _e1000_disable(struct e1000_hw *hw) E1000_WRITE_REG(hw, RDH, 0); E1000_WRITE_REG(hw, RDT, 0); - /* put the card in its initial state */ -#if 0 - E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); -#endif mdelay(10); } @@ -5359,7 +5286,6 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, #ifndef CONFIG_E1000_NO_NVM /* Validate the EEPROM and get chipset information */ -#if !defined(CONFIG_MVBC_1G) if (e1000_init_eeprom_params(hw)) { E1000_ERR(hw, "EEPROM is invalid!\n"); return -EINVAL; @@ -5367,7 +5293,6 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && e1000_validate_eeprom_checksum(hw)) return -ENXIO; -#endif e1000_read_mac_addr(hw, enetaddr); #endif e1000_get_bus_type(hw); @@ -5628,8 +5553,8 @@ static int e1000_eth_probe(struct udevice *dev) int ret; hw->name = dev->name; - ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev), - plat->enetaddr); + ret = e1000_init_one(hw, trailing_strtol(dev->name), + dm_pci_get_bdf(dev), plat->enetaddr); if (ret < 0) { printf(pr_fmt("failed to initialize card: %d\n"), ret); return ret; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index c851922ae5..e46edcd4e1 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1093,11 +1093,6 @@ struct e1000_hw { e1000_media_type media_type; e1000_fc_type fc; e1000_bus_type bus_type; -#if 0 - e1000_bus_speed bus_speed; - e1000_bus_width bus_width; - uint32_t io_base; -#endif uint32_t asf_firmware_present; #ifndef CONFIG_E1000_NO_NVM uint32_t eeprom_semaphore_present; @@ -1116,29 +1111,11 @@ struct e1000_hw { uint32_t original_fc; uint32_t txcw; uint32_t autoneg_failed; -#if 0 - uint32_t max_frame_size; - uint32_t min_frame_size; - uint32_t mc_filter_type; - uint32_t num_mc_addrs; - uint32_t collision_delta; - uint32_t tx_packet_delta; - uint32_t ledctl_default; - uint32_t ledctl_mode1; - uint32_t ledctl_mode2; -#endif uint16_t autoneg_advertised; uint16_t pci_cmd_word; uint16_t fc_high_water; uint16_t fc_low_water; uint16_t fc_pause_time; -#if 0 - uint16_t current_ifs_val; - uint16_t ifs_min_val; - uint16_t ifs_max_val; - uint16_t ifs_step_size; - uint16_t ifs_ratio; -#endif uint16_t device_id; uint16_t vendor_id; uint16_t subsystem_id; @@ -1149,9 +1126,6 @@ struct e1000_hw { uint8_t forced_speed_duplex; uint8_t wait_autoneg_complete; uint8_t dma_fairness; -#if 0 - uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; -#endif bool disable_polarity_correction; bool speed_downgraded; bool get_link_status; @@ -1162,11 +1136,6 @@ struct e1000_hw { bool report_tx_early; bool phy_reset_disable; bool initialize_hw_bits_disable; -#if 0 - bool adaptive_ifs; - bool ifs_params_forced; - bool in_ifs_mode; -#endif e1000_smart_speed smart_speed; e1000_dsp_config dsp_config_state; }; diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index df72375238..576ddb8b24 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -182,22 +182,21 @@ static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr) * These have been tested to perform correctly, but they are not used by any * of the EEPROM commands at this time. */ -#if 0 -static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr) +static __maybe_unused int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, + bool intr) { u8 op[] = { SPI_EEPROM_DISABLE_WR }; e1000_standby_eeprom(hw); return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr); } -static int e1000_spi_eeprom_write_status(struct e1000_hw *hw, - u8 status, bool intr) +static __maybe_unused int e1000_spi_eeprom_write_status(struct e1000_hw *hw, + u8 status, bool intr) { u8 op[] = { SPI_EEPROM_WRITE_STATUS, status }; e1000_standby_eeprom(hw); return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr); } -#endif static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr) { diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index df5db723ba..40fbf19c75 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -395,7 +395,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) printf("\nMMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + addr); /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index e76e9bc2b5..3ba5b4b1f9 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -304,6 +304,13 @@ static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; } + /* write the phy and reg addressse into the MII address reg */ + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), + ®s->madr); + + /* write data to the MII write register */ + writel(data, ®s->mwtd); + /* wait till the MII is not busy */ timeout = MII_TIMEOUT; do { @@ -319,13 +326,6 @@ static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; } - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - ®s->madr); - - /* write data to the MII write register */ - writel(data, ®s->mwtd); - /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, reg_ofs, data);*/ diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 38ad14eff9..fa20f548e5 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -2,7 +2,7 @@ * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. * * U-Boot version: - * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> * * Based on the Linux version which is: * Copyright (C) 2012 Marvell @@ -14,6 +14,7 @@ */ #include <common.h> +#include <dm.h> #include <net.h> #include <netdev.h> #include <config.h> @@ -28,6 +29,8 @@ #include <linux/compat.h> #include <linux/mbus.h> +DECLARE_GLOBAL_DATA_PTR; + #if !defined(CONFIG_PHYLIB) # error Marvell mvneta requires PHYLIB #endif @@ -1115,9 +1118,9 @@ static void mvneta_start_dev(struct mvneta_port *pp) mvneta_port_enable(pp); } -static void mvneta_adjust_link(struct eth_device *dev) +static void mvneta_adjust_link(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); struct phy_device *phydev = pp->phydev; int status_change = 0; @@ -1171,9 +1174,9 @@ static void mvneta_adjust_link(struct eth_device *dev) } } -static int mvneta_open(struct eth_device *dev) +static int mvneta_open(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); int ret; ret = mvneta_setup_rxqs(pp); @@ -1192,7 +1195,7 @@ static int mvneta_open(struct eth_device *dev) } /* Initialize hw */ -static int mvneta_init(struct mvneta_port *pp) +static int mvneta_init2(struct mvneta_port *pp) { int queue; @@ -1314,23 +1317,22 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) } /* Device initialization routine */ -static int mvneta_probe(struct eth_device *dev) +static int mvneta_init(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct mvneta_port *pp = dev_get_priv(dev); int err; pp->tx_ring_size = MVNETA_MAX_TXD; pp->rx_ring_size = MVNETA_MAX_RXD; - err = mvneta_init(pp); + err = mvneta_init2(pp); if (err < 0) { dev_err(&pdev->dev, "can't init eth hal\n"); return err; } - mvneta_conf_mbus_windows(pp); - - mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def); + mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def); err = mvneta_port_power_up(pp, pp->phy_interface); if (err < 0) { @@ -1367,25 +1369,24 @@ static int smi_wait_ready(struct mvneta_port *pp) } /* - * smi_reg_read - miiphy_read callback function. + * mvneta_mdio_read - miiphy_read callback function. * * Returns 16bit phy register value, or 0xffff on error */ -static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) +static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { - struct eth_device *dev = eth_get_dev_by_name(devname); - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = bus->priv; u32 smi_reg; u32 timeout; /* check parameters */ - if (phy_adr > MVNETA_PHY_ADDR_MASK) { - printf("Error: Invalid PHY address %d\n", phy_adr); + if (addr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", addr); return -EFAULT; } - if (reg_ofs > MVNETA_PHY_REG_MASK) { - printf("Err: Invalid register offset %d\n", reg_ofs); + if (reg > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg); return -EFAULT; } @@ -1394,14 +1395,14 @@ static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) return -EFAULT; /* fill the phy address and regiser offset and read opcode */ - smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) - | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS) + smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg << MVNETA_SMI_REG_ADDR_OFFS) | MVNETA_SMI_OPCODE_READ; /* write the smi register */ mvreg_write(pp, MVNETA_SMI, smi_reg); - /*wait till read value is ready */ + /* wait till read value is ready */ timeout = MVNETA_SMI_TIMEOUT; do { @@ -1417,31 +1418,29 @@ static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) ; - *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK); - - return 0; + return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK; } /* - * smi_reg_write - imiiphy_write callback function. + * mvneta_mdio_write - miiphy_write callback function. * * Returns 0 if write succeed, -EINVAL on bad parameters * -ETIME on timeout */ -static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { - struct eth_device *dev = eth_get_dev_by_name(devname); - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = bus->priv; u32 smi_reg; /* check parameters */ - if (phy_adr > MVNETA_PHY_ADDR_MASK) { - printf("Error: Invalid PHY address %d\n", phy_adr); + if (addr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", addr); return -EFAULT; } - if (reg_ofs > MVNETA_PHY_REG_MASK) { - printf("Err: Invalid register offset %d\n", reg_ofs); + if (reg > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg); return -EFAULT; } @@ -1450,9 +1449,9 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; /* fill the phy addr and reg offset and write opcode and data */ - smi_reg = (data << MVNETA_SMI_DATA_OFFS); - smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) - | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS); + smi_reg = value << MVNETA_SMI_DATA_OFFS; + smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg << MVNETA_SMI_REG_ADDR_OFFS); smi_reg &= ~MVNETA_SMI_OPCODE_READ; /* write the smi register */ @@ -1461,9 +1460,9 @@ static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return 0; } -static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) +static int mvneta_start(struct udevice *dev) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); struct phy_device *phydev; mvneta_port_power_up(pp, pp->phy_interface); @@ -1483,7 +1482,7 @@ static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) } /* Full init on first call */ - mvneta_probe(dev); + mvneta_init(dev); pp->init = 1; } else { /* Upon all following calls, this is enough */ @@ -1494,9 +1493,9 @@ static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) return 0; } -static int mvneta_send(struct eth_device *dev, void *ptr, int len) +static int mvneta_send(struct udevice *dev, void *packet, int length) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); struct mvneta_tx_queue *txq = &pp->txqs[0]; struct mvneta_tx_desc *tx_desc; int sent_desc; @@ -1505,9 +1504,9 @@ static int mvneta_send(struct eth_device *dev, void *ptr, int len) /* Get a descriptor for the first part of the packet */ tx_desc = mvneta_txq_next_desc_get(txq); - tx_desc->buf_phys_addr = (u32)ptr; - tx_desc->data_size = len; - flush_dcache_range((u32)ptr, (u32)ptr + len); + tx_desc->buf_phys_addr = (u32)packet; + tx_desc->data_size = length; + flush_dcache_range((u32)packet, (u32)packet + length); /* First and Last descriptor */ tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; @@ -1525,28 +1524,25 @@ static int mvneta_send(struct eth_device *dev, void *ptr, int len) /* txDone has increased - hw sent packet */ mvneta_txq_sent_desc_dec(pp, txq, sent_desc); - return 0; return 0; } -static int mvneta_recv(struct eth_device *dev) +static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) { - struct mvneta_port *pp = dev->priv; + struct mvneta_port *pp = dev_get_priv(dev); int rx_done; - int packets_done; struct mvneta_rx_queue *rxq; + int rx_bytes = 0; /* get rx queue */ rxq = mvneta_rxq_handle_get(pp, rxq_def); rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); - packets_done = rx_done; - while (packets_done--) { + if (rx_done) { struct mvneta_rx_desc *rx_desc; unsigned char *data; u32 rx_status; - int rx_bytes; /* * No cache invalidation needed here, since the desc's are @@ -1559,7 +1555,7 @@ static int mvneta_recv(struct eth_device *dev) (rx_status & MVNETA_RXD_ERR_SUMMARY)) { mvneta_rx_error(pp, rx_desc); /* leave the descriptor untouched */ - continue; + return -EIO; } /* 2 bytes for marvell header. 4 bytes for crc */ @@ -1571,40 +1567,24 @@ static int mvneta_recv(struct eth_device *dev) * No cache invalidation needed here, since the rx_buffer's are * located in a uncached memory region */ - net_process_received_packet(data, rx_bytes); - } + *packetp = data; - /* Update rxq management counters */ - if (rx_done) mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); + } - return 0; -} - -static void mvneta_halt(struct eth_device *dev) -{ - struct mvneta_port *pp = dev->priv; - - mvneta_port_down(pp); - mvneta_port_disable(pp); + return rx_bytes; } -int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) +static int mvneta_probe(struct udevice *dev) { - struct eth_device *dev; - struct mvneta_port *pp; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct mvneta_port *pp = dev_get_priv(dev); + void *blob = (void *)gd->fdt_blob; + int node = dev->of_offset; + struct mii_dev *bus; + unsigned long addr; void *bd_space; - dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -ENOMEM; - - pp = calloc(1, sizeof(*pp)); - if (pp == NULL) - return -ENOMEM; - - dev->priv = pp; - /* * Allocate buffer area for descs and rx_buffers. This is only * done once for all interfaces. As only one interface can @@ -1625,28 +1605,82 @@ int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); } - sprintf(dev->name, "neta%d", devnum); + pp->base = (void __iomem *)pdata->iobase; - pp->base = (void __iomem *)base_addr; - dev->iobase = base_addr; - dev->init = mvneta_init_u_boot; - dev->halt = mvneta_halt; - dev->send = mvneta_send; - dev->recv = mvneta_recv; - dev->write_hwaddr = NULL; + /* Configure MBUS address windows */ + mvneta_conf_mbus_windows(pp); - /* - * The PHY interface type is configured via the - * board specific CONFIG_SYS_NETA_INTERFACE_TYPE - * define. - */ - pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE; + /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ + pp->phy_interface = pdata->phy_interface; + + /* Now read phyaddr from DT */ + addr = fdtdec_get_int(blob, node, "phy", 0); + addr = fdt_node_offset_by_phandle(blob, addr); + pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mvneta_mdio_read; + bus->write = mvneta_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)pp; + pp->bus = bus; - eth_register(dev); + return mdio_register(bus); +} - pp->phyaddr = phy_addr; - miiphy_register(dev->name, smi_reg_read, smi_reg_write); - pp->bus = miiphy_get_dev_by_name(dev->name); +static void mvneta_stop(struct udevice *dev) +{ + struct mvneta_port *pp = dev_get_priv(dev); - return 1; + mvneta_port_down(pp); + mvneta_port_disable(pp); } + +static const struct eth_ops mvneta_ops = { + .start = mvneta_start, + .send = mvneta_send, + .recv = mvneta_recv, + .stop = mvneta_stop, +}; + +static int mvneta_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + + pdata->iobase = dev_get_addr(dev); + + /* Get phy-mode / phy_interface from DT */ + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + return 0; +} + +static const struct udevice_id mvneta_ids[] = { + { .compatible = "marvell,armada-370-neta" }, + { .compatible = "marvell,armada-xp-neta" }, + { } +}; + +U_BOOT_DRIVER(mvneta) = { + .name = "mvneta", + .id = UCLASS_ETH, + .of_match = mvneta_ids, + .ofdata_to_platdata = mvneta_ofdata_to_platdata, + .probe = mvneta_probe, + .ops = &mvneta_ops, + .priv_auto_alloc_size = sizeof(struct mvneta_port), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index dfc01000fc..1b4dd56d52 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -424,7 +424,7 @@ int pch_gbe_probe(struct udevice *dev) pci_dev_t devno; u32 iobase; - devno = pci_get_bdf(dev); + devno = dm_pci_get_bdf(dev); /* * The priv structure contains the descriptors and frame buffers which diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 3a2b3bba99..447ecfbeb6 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -174,7 +174,8 @@ void cs4340_upload_firmware(struct phy_device *phydev) printf("MMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + addr); /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 19422c4a2a..9e60adf61a 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -513,8 +513,13 @@ static void rtl_flush_buffer(void *buf, size_t size) /************************************************************************** RECV - Receive a frame ***************************************************************************/ -static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase, +#ifdef CONFIG_DM_ETH +static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, + uchar **packetp) +#else +static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase, uchar **packetp) +#endif { /* return true if there's an ethernet packet ready to read */ /* nic->packet should contain data on return */ @@ -545,9 +550,16 @@ static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase, else tpc->RxDescArray[cur_rx].status = cpu_to_le32(OWNbit + RX_BUF_SIZE); +#ifdef CONFIG_DM_ETH tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( - pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long) + dm_pci_mem_to_phys(dev, + (pci_addr_t)(unsigned long) + tpc->RxBufferRing[cur_rx])); +#else + tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( + pci_mem_to_phys(dev, (pci_addr_t)(unsigned long) tpc->RxBufferRing[cur_rx])); +#endif rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); #ifdef CONFIG_DM_ETH *packetp = rxdata; @@ -576,7 +588,7 @@ int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) { struct rtl8169_private *priv = dev_get_priv(dev); - return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp); + return rtl_recv_common(dev, priv->iobase, packetp); } #else static int rtl_recv(struct eth_device *dev) @@ -590,8 +602,13 @@ static int rtl_recv(struct eth_device *dev) /************************************************************************** SEND - Transmit a frame ***************************************************************************/ -static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase, +#ifdef CONFIG_DM_ETH +static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, void *packet, int length) +#else +static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, + void *packet, int length) +#endif { /* send the packet to destination */ @@ -618,8 +635,13 @@ static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase, ptxb[len++] = '\0'; tpc->TxDescArray[entry].buf_Haddr = 0; +#ifdef CONFIG_DM_ETH tpc->TxDescArray[entry].buf_addr = cpu_to_le32( - pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb)); + dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); +#else + tpc->TxDescArray[entry].buf_addr = cpu_to_le32( + pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); +#endif if (entry != (NUM_TX_DESC - 1)) { tpc->TxDescArray[entry].status = cpu_to_le32((OWNbit | FSbit | LSbit) | @@ -661,7 +683,7 @@ int rtl8169_eth_send(struct udevice *dev, void *packet, int length) { struct rtl8169_private *priv = dev_get_priv(dev); - return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length); + return rtl_send_common(dev, priv->iobase, packet, length); } #else @@ -695,7 +717,11 @@ static void rtl8169_set_rx_mode(void) RTL_W32(MAR0 + 4, mc_filter[1]); } -static void rtl8169_hw_start(pci_dev_t bdf) +#ifdef CONFIG_DM_ETH +static void rtl8169_hw_start(struct udevice *dev) +#else +static void rtl8169_hw_start(pci_dev_t dev) +#endif { u32 i; @@ -740,11 +766,21 @@ static void rtl8169_hw_start(pci_dev_t bdf) tpc->cur_rx = 0; - RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf, +#ifdef CONFIG_DM_ETH + RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)tpc->TxDescArray)); +#else + RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev, + (pci_addr_t)(unsigned long)tpc->TxDescArray)); +#endif RTL_W32(TxDescStartAddrHigh, (unsigned long)0); +#ifdef CONFIG_DM_ETH + RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys( + dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); +#else RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( - bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray)); + dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); +#endif RTL_W32(RxDescStartAddrHigh, (unsigned long)0); /* RTL-8169sc/8110sc or later version */ @@ -766,7 +802,11 @@ static void rtl8169_hw_start(pci_dev_t bdf) #endif } -static void rtl8169_init_ring(pci_dev_t bdf) +#ifdef CONFIG_DM_ETH +static void rtl8169_init_ring(struct udevice *dev) +#else +static void rtl8169_init_ring(pci_dev_t dev) +#endif { int i; @@ -794,8 +834,13 @@ static void rtl8169_init_ring(pci_dev_t bdf) cpu_to_le32(OWNbit + RX_BUF_SIZE); tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; +#ifdef CONFIG_DM_ETH + tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys( + dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); +#else tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( - bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); + dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); +#endif rtl_flush_rx_desc(&tpc->RxDescArray[i]); } @@ -804,7 +849,11 @@ static void rtl8169_init_ring(pci_dev_t bdf) #endif } -static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr) +#ifdef CONFIG_DM_ETH +static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr) +#else +static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr) +#endif { int i; @@ -813,8 +862,8 @@ static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr) printf ("%s\n", __FUNCTION__); #endif - rtl8169_init_ring(bdf); - rtl8169_hw_start(bdf); + rtl8169_init_ring(dev); + rtl8169_hw_start(dev); /* Construct a perfect filter frame with the mac address as first match * and broadcast for all others */ for (i = 0; i < 192; i++) @@ -837,7 +886,7 @@ static int rtl8169_eth_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_platdata(dev); - rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr); + rtl8169_common_start(dev, plat->enetaddr); return 0; } @@ -1130,10 +1179,9 @@ static int rtl8169_eth_probe(struct udevice *dev) region = 1; break; } - pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4, - &iobase); + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase); iobase &= ~0xf; - priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase); + priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase); ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); if (ret < 0) { diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 6b761b453d..f8be9bf1ea 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -6,15 +6,16 @@ # ifneq ($(CONFIG_DM_PCI),) -obj-$(CONFIG_PCI) += pci-uclass.o +obj-y += pci_rom.o +obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o obj-$(CONFIG_X86) += pci_x86.o else -obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_PCI) += pci.o pci_auto_old.o endif -obj-$(CONFIG_PCI) += pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o +obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 5fe30723c2..685df9d274 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -11,12 +11,14 @@ #include <fdtdec.h> #include <inttypes.h> #include <pci.h> +#include <asm/io.h> #include <dm/lists.h> #include <dm/root.h> #include <dm/device-internal.h> #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) #include <asm/fsp/fsp_support.h> #endif +#include "pci_internal.h" DECLARE_GLOBAL_DATA_PTR; @@ -61,7 +63,7 @@ struct udevice *pci_get_controller(struct udevice *dev) return dev; } -pci_dev_t pci_get_bdf(struct udevice *dev) +pci_dev_t dm_pci_get_bdf(struct udevice *dev) { struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); struct udevice *bus = dev->parent; @@ -128,7 +130,7 @@ int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, return -ENODEV; } -int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp) +int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp) { struct udevice *bus; int ret; @@ -194,6 +196,65 @@ int pci_find_device_id(struct pci_device_id *ids, int index, return -ENODEV; } +static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor, + unsigned int device, int *indexp, + struct udevice **devp) +{ + struct pci_child_platdata *pplat; + struct udevice *dev; + + for (device_find_first_child(bus, &dev); + dev; + device_find_next_child(&dev)) { + pplat = dev_get_parent_platdata(dev); + if (pplat->vendor == vendor && pplat->device == device) { + if (!(*indexp)--) { + *devp = dev; + return 0; + } + } + } + + return -ENODEV; +} + +int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, + struct udevice **devp) +{ + struct udevice *bus; + + /* Scan all known buses */ + for (uclass_first_device(UCLASS_PCI, &bus); + bus; + uclass_next_device(&bus)) { + if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp)) + return device_probe(*devp); + } + *devp = NULL; + + return -ENODEV; +} + +int dm_pci_find_class(uint find_class, int index, struct udevice **devp) +{ + struct udevice *dev; + + /* Scan all known buses */ + for (pci_find_first_device(&dev); + dev; + pci_find_next_device(&dev)) { + struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); + + if (pplat->class == find_class && !index--) { + *devp = dev; + return device_probe(*devp); + } + } + *devp = NULL; + + return -ENODEV; +} + int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, unsigned long value, enum pci_size_t size) { @@ -225,7 +286,8 @@ int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; - return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size); + return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value, + size); } @@ -290,7 +352,7 @@ int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; - return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep, + return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep, size); } @@ -403,7 +465,7 @@ int pci_auto_config_devices(struct udevice *bus) int ret; debug("%s: device %s\n", __func__, dev->name); - ret = pciauto_config_device(hose, pci_get_bdf(dev)); + ret = dm_pciauto_config_device(dev); if (ret < 0) return ret; max_bus = ret; @@ -418,26 +480,16 @@ int pci_auto_config_devices(struct udevice *bus) return sub_bus; } -int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) +int dm_pci_hose_probe_bus(struct udevice *bus) { - struct udevice *parent, *bus; int sub_bus; int ret; debug("%s\n", __func__); - parent = hose->bus; - - /* Find the bus within the parent */ - ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus); - if (ret) { - debug("%s: Cannot find device %x on bus %s: %d\n", __func__, - bdf, parent->name, ret); - return ret; - } sub_bus = pci_get_bus_max() + 1; debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); - pciauto_prescan_setup_bridge(hose, bdf, sub_bus); + dm_pciauto_prescan_setup_bridge(bus, sub_bus); ret = device_probe(bus); if (ret) { @@ -451,7 +503,7 @@ int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) return -EPIPE; } sub_bus = pci_get_bus_max(); - pciauto_postscan_setup_bridge(hose, bdf, sub_bus); + dm_pciauto_postscan_setup_bridge(bus, sub_bus); return sub_bus; } @@ -622,9 +674,7 @@ int pci_bind_bus_devices(struct udevice *bus) /* Find this device in the device tree */ ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev); - /* Search for a driver */ - - /* If nothing in the device tree, bind a generic device */ + /* If nothing in the device tree, bind a device */ if (ret == -ENODEV) { struct pci_device_id find_id; ulong val; @@ -1004,6 +1054,154 @@ int pci_get_regions(struct udevice *dev, struct pci_region **iop, return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL); } +u32 dm_pci_read_bar32(struct udevice *dev, int barnum) +{ + u32 addr; + int bar; + + bar = PCI_BASE_ADDRESS_0 + barnum * 4; + dm_pci_read_config32(dev, bar, &addr); + if (addr & PCI_BASE_ADDRESS_SPACE_IO) + return addr & PCI_BASE_ADDRESS_IO_MASK; + else + return addr & PCI_BASE_ADDRESS_MEM_MASK; +} + +static int _dm_pci_bus_to_phys(struct udevice *ctlr, + pci_addr_t bus_addr, unsigned long flags, + unsigned long skip_mask, phys_addr_t *pa) +{ + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + struct pci_region *res; + int i; + + for (i = 0; i < hose->region_count; i++) { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + if (res->flags & skip_mask) + continue; + + if (bus_addr >= res->bus_start && + (bus_addr - res->bus_start) < res->size) { + *pa = (bus_addr - res->bus_start + res->phys_start); + return 0; + } + } + + return 1; +} + +phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr, + unsigned long flags) +{ + phys_addr_t phys_addr = 0; + struct udevice *ctlr; + int ret; + + /* The root controller has the region information */ + ctlr = pci_get_controller(dev); + + /* + * if PCI_REGION_MEM is set we do a two pass search with preference + * on matches that don't have PCI_REGION_SYS_MEMORY set + */ + if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { + ret = _dm_pci_bus_to_phys(ctlr, bus_addr, + flags, PCI_REGION_SYS_MEMORY, + &phys_addr); + if (!ret) + return phys_addr; + } + + ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr); + + if (ret) + puts("pci_hose_bus_to_phys: invalid physical address\n"); + + return phys_addr; +} + +int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, + unsigned long flags, unsigned long skip_mask, + pci_addr_t *ba) +{ + struct pci_region *res; + struct udevice *ctlr; + pci_addr_t bus_addr; + int i; + struct pci_controller *hose; + + /* The root controller has the region information */ + ctlr = pci_get_controller(dev); + hose = dev_get_uclass_priv(ctlr); + + for (i = 0; i < hose->region_count; i++) { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + if (res->flags & skip_mask) + continue; + + bus_addr = phys_addr - res->phys_start + res->bus_start; + + if (bus_addr >= res->bus_start && + (bus_addr - res->bus_start) < res->size) { + *ba = bus_addr; + return 0; + } + } + + return 1; +} + +pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, + unsigned long flags) +{ + pci_addr_t bus_addr = 0; + int ret; + + /* + * if PCI_REGION_MEM is set we do a two pass search with preference + * on matches that don't have PCI_REGION_SYS_MEMORY set + */ + if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { + ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, + PCI_REGION_SYS_MEMORY, &bus_addr); + if (!ret) + return bus_addr; + } + + ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr); + + if (ret) + puts("pci_hose_phys_to_bus: invalid physical address\n"); + + return bus_addr; +} + +void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) +{ + pci_addr_t pci_bus_addr; + u32 bar_response; + + /* read BAR address */ + dm_pci_read_config32(dev, bar, &bar_response); + pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); + + /* + * Pass "0" as the length argument to pci_bus_to_virt. The arg + * isn't actualy used on any platform because u-boot assumes a static + * linear mapping. In the future, this could read the BAR size + * and pass that as the size if needed. + */ + return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); +} + UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 645ecd423f..461908941d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,7 +9,10 @@ */ /* - * PCI routines + * Old PCI routines + * + * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI + * and change pci-uclass.c. */ #include <common.h> diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c new file mode 100644 index 0000000000..842eafc4f8 --- /dev/null +++ b/drivers/pci/pci_auto.c @@ -0,0 +1,386 @@ +/* + * PCI autoconfiguration library + * + * Author: Matt Porter <mporter@mvista.com> + * + * Copyright 2000 MontaVista Software Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <pci.h> + +/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE +#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 +#endif + +void dm_pciauto_setup_device(struct udevice *dev, int bars_num, + struct pci_region *mem, + struct pci_region *prefetch, struct pci_region *io, + bool enum_only) +{ + u32 bar_response; + pci_size_t bar_size; + u16 cmdstat = 0; + int bar, bar_nr = 0; + u8 header_type; + int rom_addr; + pci_addr_t bar_value; + struct pci_region *bar_res; + int found_mem64 = 0; + u16 class; + + dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); + cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | + PCI_COMMAND_MASTER; + + for (bar = PCI_BASE_ADDRESS_0; + bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { + /* Tickle the BAR and get the response */ + if (!enum_only) + dm_pci_write_config32(dev, bar, 0xffffffff); + dm_pci_read_config32(dev, bar, &bar_response); + + /* If BAR is not implemented go to the next BAR */ + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) + & 0xffff) + 1; + if (!enum_only) + bar_res = io; + + debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", + bar_nr, (unsigned long long)bar_size); + } else { + if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) { + u32 bar_response_upper; + u64 bar64; + + if (!enum_only) { + dm_pci_write_config32(dev, bar + 4, + 0xffffffff); + } + dm_pci_read_config32(dev, bar + 4, + &bar_response_upper); + + bar64 = ((u64)bar_response_upper << 32) | + bar_response; + + bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + + 1; + if (!enum_only) + found_mem64 = 1; + } else { + bar_size = (u32)(~(bar_response & + PCI_BASE_ADDRESS_MEM_MASK) + 1); + } + if (!enum_only) { + if (prefetch && (bar_response & + PCI_BASE_ADDRESS_MEM_PREFETCH)) { + bar_res = prefetch; + } else { + bar_res = mem; + } + } + + debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", + bar_nr, bar_res == prefetch ? "Prf" : "Mem", + (unsigned long long)bar_size); + } + + if (!enum_only && pciauto_region_allocate(bar_res, bar_size, + &bar_value) == 0) { + /* Write it out and update our limit */ + dm_pci_write_config32(dev, bar, (u32)bar_value); + + if (found_mem64) { + bar += 4; +#ifdef CONFIG_SYS_PCI_64BIT + dm_pci_write_config32(dev, bar, + (u32)(bar_value >> 32)); +#else + /* + * If we are a 64-bit decoder then increment to + * the upper 32 bits of the bar and force it to + * locate in the lower 4GB of memory. + */ + dm_pci_write_config32(dev, bar, 0x00000000); +#endif + } + } + + cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? + PCI_COMMAND_IO : PCI_COMMAND_MEMORY; + + debug("\n"); + + bar_nr++; + } + + if (!enum_only) { + /* Configure the expansion ROM address */ + dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + header_type &= 0x7f; + if (header_type != PCI_HEADER_TYPE_CARDBUS) { + rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? + PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; + dm_pci_write_config32(dev, rom_addr, 0xfffffffe); + dm_pci_read_config32(dev, rom_addr, &bar_response); + if (bar_response) { + bar_size = -(bar_response & ~1); + debug("PCI Autoconfig: ROM, size=%#x, ", + (unsigned int)bar_size); + if (pciauto_region_allocate(mem, bar_size, + &bar_value) == 0) { + dm_pci_write_config32(dev, rom_addr, + bar_value); + } + cmdstat |= PCI_COMMAND_MEMORY; + debug("\n"); + } + } + } + + /* PCI_COMMAND_IO must be set for VGA device */ + dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); + if (class == PCI_CLASS_DISPLAY_VGA) + cmdstat |= PCI_COMMAND_IO; + + dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); + dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, + CONFIG_SYS_PCI_CACHE_LINE_SIZE); + dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); +} + +void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) +{ + struct pci_region *pci_mem; + struct pci_region *pci_prefetch; + struct pci_region *pci_io; + u16 cmdstat, prefechable_64; + /* The root controller has the region information */ + struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + + pci_mem = ctlr_hose->pci_mem; + pci_prefetch = ctlr_hose->pci_prefetch; + pci_io = ctlr_hose->pci_io; + + dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); + dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); + prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; + + /* Configure bus number registers */ + dm_pci_write_config8(dev, PCI_PRIMARY_BUS, + PCI_BUS(dm_pci_get_bdf(dev))); + dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus); + dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); + + if (pci_mem) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + /* + * Set up memory and I/O filter limits, assume 32-bit + * I/O space + */ + dm_pci_write_config16(dev, PCI_MEMORY_BASE, + (pci_mem->bus_lower & 0xfff00000) >> 16); + + cmdstat |= PCI_COMMAND_MEMORY; + } + + if (pci_prefetch) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_prefetch, 0x100000); + + /* + * Set up memory and I/O filter limits, assume 32-bit + * I/O space + */ + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, + (pci_prefetch->bus_lower & 0xfff00000) >> 16); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) +#ifdef CONFIG_SYS_PCI_64BIT + dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, + pci_prefetch->bus_lower >> 32); +#else + dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); +#endif + + cmdstat |= PCI_COMMAND_MEMORY; + } else { + /* We don't support prefetchable memory for now, so disable */ + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { + dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); + dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); + } + } + + if (pci_io) { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + dm_pci_write_config8(dev, PCI_IO_BASE, + (pci_io->bus_lower & 0x0000f000) >> 8); + dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, + (pci_io->bus_lower & 0xffff0000) >> 16); + + cmdstat |= PCI_COMMAND_IO; + } + + /* Enable memory and I/O accesses, enable bus master */ + dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); +} + +void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) +{ + struct pci_region *pci_mem; + struct pci_region *pci_prefetch; + struct pci_region *pci_io; + + /* The root controller has the region information */ + struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + + pci_mem = ctlr_hose->pci_mem; + pci_prefetch = ctlr_hose->pci_prefetch; + pci_io = ctlr_hose->pci_io; + + /* Configure bus number registers */ + dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus); + + if (pci_mem) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, + (pci_mem->bus_lower - 1) >> 16); + } + + if (pci_prefetch) { + u16 prefechable_64; + + dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT, + &prefechable_64); + prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; + + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_prefetch, 0x100000); + + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, + (pci_prefetch->bus_lower - 1) >> 16); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) +#ifdef CONFIG_SYS_PCI_64BIT + dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, + (pci_prefetch->bus_lower - 1) >> 32); +#else + dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0); +#endif + } + + if (pci_io) { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + dm_pci_write_config8(dev, PCI_IO_LIMIT, + ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); + dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, + ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); + } +} + +/* + * HJF: Changed this to return int. I think this is required + * to get the correct result when scanning bridges + */ +int dm_pciauto_config_device(struct udevice *dev) +{ + struct pci_region *pci_mem; + struct pci_region *pci_prefetch; + struct pci_region *pci_io; + unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); + unsigned short class; + bool enum_only = false; + int n; + +#ifdef CONFIG_PCI_ENUM_ONLY + enum_only = true; +#endif + /* The root controller has the region information */ + struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + + pci_mem = ctlr_hose->pci_mem; + pci_prefetch = ctlr_hose->pci_prefetch; + pci_io = ctlr_hose->pci_io; + + dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); + + switch (class) { + case PCI_CLASS_BRIDGE_PCI: + debug("PCI Autoconfig: Found P2P bridge, device %d\n", + PCI_DEV(dm_pci_get_bdf(dev))); + + dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io, + enum_only); + + n = dm_pci_hose_probe_bus(dev); + if (n < 0) + return n; + sub_bus = (unsigned int)n; + break; + + case PCI_CLASS_BRIDGE_CARDBUS: + /* + * just do a minimal setup of the bridge, + * let the OS take care of the rest + */ + dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io, + enum_only); + + debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", + PCI_DEV(dm_pci_get_bdf(dev))); + + break; + +#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) + case PCI_CLASS_BRIDGE_OTHER: + debug("PCI Autoconfig: Skipping bridge device %d\n", + PCI_DEV(dm_pci_get_bdf(dev))); + break; +#endif +#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) + case PCI_CLASS_BRIDGE_OTHER: + /* + * The host/PCI bridge 1 seems broken in 8349 - it presents + * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ + * device claiming resources io/mem/irq.. we only allow for + * the PIMMR window to be allocated (BAR0 - 1MB size) + */ + debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); + dm_pciauto_setup_device(dev, 0, hose->pci_mem, + hose->pci_prefetch, hose->pci_io, + enum_only); + break; +#endif + + case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ + debug("PCI AutoConfig: Found PowerPC device\n"); + + default: + dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io, + enum_only); + break; + } + + return sub_bus; +} diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 932eab85bf..edc9a7b3c1 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -1,7 +1,5 @@ /* - * arch/powerpc/kernel/pci_auto.c - * - * PCI autoconfiguration library + * PCI autoconfiguration library (legacy version, do not change) * * Author: Matt Porter <mporter@mvista.com> * @@ -14,6 +12,11 @@ #include <errno.h> #include <pci.h> +/* + * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI + * and change pci_auto.c. + */ + /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 @@ -98,11 +101,11 @@ void pciauto_setup_device(struct pci_controller *hose, bar_res = prefetch; else bar_res = mem; -#endif debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", bar_nr, bar_res == prefetch ? "Prf" : "Mem", (unsigned long long)bar_size); +#endif } #ifndef CONFIG_PCI_ENUM_ONLY @@ -177,18 +180,9 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, struct pci_region *pci_io; u16 cmdstat, prefechable_64; -#ifdef CONFIG_DM_PCI - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); - - pci_mem = ctlr_hose->pci_mem; - pci_prefetch = ctlr_hose->pci_prefetch; - pci_io = ctlr_hose->pci_io; -#else pci_mem = hose->pci_mem; pci_prefetch = hose->pci_prefetch; pci_io = hose->pci_io; -#endif pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, @@ -196,15 +190,10 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; /* Configure bus number registers */ -#ifdef CONFIG_DM_PCI - pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); - pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); -#else pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev) - hose->first_busno); pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus - hose->first_busno); -#endif pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { @@ -271,26 +260,13 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose, struct pci_region *pci_prefetch; struct pci_region *pci_io; -#ifdef CONFIG_DM_PCI - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); - - pci_mem = ctlr_hose->pci_mem; - pci_prefetch = ctlr_hose->pci_prefetch; - pci_io = ctlr_hose->pci_io; -#else pci_mem = hose->pci_mem; pci_prefetch = hose->pci_prefetch; pci_io = hose->pci_io; -#endif /* Configure bus number registers */ -#ifdef CONFIG_DM_PCI - pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); -#else pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus - hose->first_busno); -#endif if (pci_mem) { /* Round memory allocator to 1MB boundary */ @@ -350,18 +326,9 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) unsigned short class; int n; -#ifdef CONFIG_DM_PCI - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); - - pci_mem = ctlr_hose->pci_mem; - pci_prefetch = ctlr_hose->pci_prefetch; - pci_io = ctlr_hose->pci_io; -#else pci_mem = hose->pci_mem; pci_prefetch = hose->pci_prefetch; pci_io = hose->pci_io; -#endif pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); @@ -373,12 +340,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) pciauto_setup_device(hose, dev, 2, pci_mem, pci_prefetch, pci_io); -#ifdef CONFIG_DM_PCI - n = dm_pci_hose_probe_bus(hose, dev); - if (n < 0) - return n; - sub_bus = (unsigned int)n; -#else /* Passing in current_busno allows for sibling P2P bridges */ hose->current_busno++; pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); @@ -393,7 +354,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) pciauto_postscan_setup_bridge(hose, dev, sub_bus); sub_bus = hose->current_busno; -#endif break; case PCI_CLASS_BRIDGE_CARDBUS: @@ -407,9 +367,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev)); -#ifndef CONFIG_DM_PCI hose->current_busno++; -#endif break; #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index 2a149022e2..1755914b4e 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -79,48 +79,6 @@ const char *pci_class_str(u8 class) }; } -pci_dev_t pci_find_class(uint find_class, int index) -{ - int bus; - int devnum; - pci_dev_t bdf; - uint32_t class; - - for (bus = 0; bus <= pci_last_busno(); bus++) { - for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) { - pci_read_config_dword(PCI_BDF(bus, devnum, 0), - PCI_CLASS_REVISION, &class); - if (class >> 16 == 0xffff) - continue; - - for (bdf = PCI_BDF(bus, devnum, 0); - bdf <= PCI_BDF(bus, devnum, - PCI_MAX_PCI_FUNCTIONS - 1); - bdf += PCI_BDF(0, 0, 1)) { - pci_read_config_dword(bdf, PCI_CLASS_REVISION, - &class); - class >>= 8; - - if (class != find_class) - continue; - /* - * Decrement the index. We want to return the - * correct device, so index is 0 for the first - * matching device, 1 for the second, etc. - */ - if (index) { - index--; - continue; - } - /* Return index'th controller. */ - return bdf; - } - } - } - - return -ENODEV; -} - __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) { /* @@ -141,6 +99,7 @@ __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) return 0; } +#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /* Get a virtual address associated with a BAR region */ void *pci_map_bar(pci_dev_t pdev, int bar, int flags) { @@ -363,3 +322,46 @@ pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, return -1; } + +pci_dev_t pci_find_class(uint find_class, int index) +{ + int bus; + int devnum; + pci_dev_t bdf; + uint32_t class; + + for (bus = 0; bus <= pci_last_busno(); bus++) { + for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) { + pci_read_config_dword(PCI_BDF(bus, devnum, 0), + PCI_CLASS_REVISION, &class); + if (class >> 16 == 0xffff) + continue; + + for (bdf = PCI_BDF(bus, devnum, 0); + bdf <= PCI_BDF(bus, devnum, + PCI_MAX_PCI_FUNCTIONS - 1); + bdf += PCI_BDF(0, 0, 1)) { + pci_read_config_dword(bdf, PCI_CLASS_REVISION, + &class); + class >>= 8; + + if (class != find_class) + continue; + /* + * Decrement the index. We want to return the + * correct device, so index is 0 for the first + * matching device, 1 for the second, etc. + */ + if (index) { + index--; + continue; + } + /* Return index'th controller. */ + return bdf; + } + } + } + + return -ENODEV; +} +#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index 712c48f28f..dd15eb19f8 100644 --- a/drivers/pci/pci_compat.c +++ b/drivers/pci/pci_compat.c @@ -34,5 +34,5 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) if (pci_find_device_id(ids, index, &dev)) return -1; - return pci_get_bdf(dev); + return dm_pci_get_bdf(dev); } diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h new file mode 100644 index 0000000000..0867575a58 --- /dev/null +++ b/drivers/pci/pci_internal.h @@ -0,0 +1,50 @@ +/* + * Internal PCI functions, not exported outside drivers/pci + * + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __pci_internal_h +#define __pci_internal_h + +/** + * dm_pciauto_prescan_setup_bridge() - Set up a bridge for scanning + * + * This gets a bridge ready so that its downstream devices can be scanned. + * It sets up the bus number and memory range registers. Once the scan is + * completed, dm_pciauto_postscan_setup_bridge() should be called. + * + * @dev: Bridge device to be scanned + * @sub_bus: Bus number of the 'other side' of the bridge + */ +void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus); + +/** + * dm_pciauto_postscan_setup_bridge() - Finish set up of a bridge after scanning + * + * This should be called after a bus scan is complete. It adjusts the memory + * ranges to fit with the devices actually found on the other side (downstream) + * of the bridge. + * + * @dev: Bridge device that was scanned + * @sub_bus: Bus number of the 'other side' of the bridge + */ +void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus); + +/** + * dm_pciauto_config_device() - Configure a PCI device ready for use + * + * If the device is a bridge, downstream devices will be probed. + * + * @dev: Device to configure + * @return the maximum PCI bus number found by this device. If there are no + * bridges, this just returns the device's bus number. If the device is a + * bridge then it will return a larger number, depending on the devices on + * that bridge. On error, returns a -ve error number. + */ +int dm_pciauto_config_device(struct udevice *dev); + +#endif diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index fd2744dbd4..4eedfe1cbb 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -155,6 +155,14 @@ static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, } #endif +static int mvebu_pex_unit_is_x4(int pex_idx) +{ + int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3; + u32 mask = (0x0f << (pex_unit * 8)); + + return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask; +} + static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) { u32 val; @@ -419,5 +427,11 @@ void pci_init_board(void) writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); bus = hose->last_busno + 1; + + /* need to skip more for X4 links, otherwise scan will hang */ + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + if (mvebu_pex_unit_is_x4(i)) + i += 3; + } } } diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index ad1167e2b6..2cb81b66b7 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -25,6 +25,7 @@ #include <common.h> #include <bios_emul.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <pci.h> @@ -33,12 +34,12 @@ #include <video_fb.h> #include <linux/screen_info.h> -__weak bool board_should_run_oprom(pci_dev_t dev) +__weak bool board_should_run_oprom(struct udevice *dev) { return true; } -static bool should_load_oprom(pci_dev_t dev) +static bool should_load_oprom(struct udevice *dev) { if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return 1; @@ -53,21 +54,18 @@ __weak uint32_t board_map_oprom_vendev(uint32_t vendev) return vendev; } -static int pci_rom_probe(pci_dev_t dev, uint class, - struct pci_rom_header **hdrp) +static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp) { + struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); struct pci_rom_header *rom_header; struct pci_rom_data *rom_data; - u16 vendor, device; u16 rom_vendor, rom_device; u32 rom_class; u32 vendev; u32 mapped_vendev; u32 rom_address; - pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); - pci_read_config_word(dev, PCI_DEVICE_ID, &device); - vendev = vendor << 16 | device; + vendev = pplat->vendor << 16 | pplat->device; mapped_vendev = board_map_oprom_vendev(vendev); if (vendev != mapped_vendev) debug("Device ID mapped to %#08x\n", mapped_vendev); @@ -76,15 +74,15 @@ static int pci_rom_probe(pci_dev_t dev, uint class, rom_address = CONFIG_VGA_BIOS_ADDR; #else - pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address); + dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { debug("%s: rom_address=%x\n", __func__, rom_address); return -ENOENT; } /* Enable expansion ROM address decoding. */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, - rom_address | PCI_ROM_ADDRESS_ENABLE); + dm_pci_write_config32(dev, PCI_ROM_ADDRESS, + rom_address | PCI_ROM_ADDRESS_ENABLE); #endif debug("Option ROM address %x\n", rom_address); rom_header = (struct pci_rom_header *)(unsigned long)rom_address; @@ -98,7 +96,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class, le16_to_cpu(rom_header->signature)); #ifndef CONFIG_VGA_BIOS_ADDR /* Disable expansion ROM address decoding */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address); + dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address); #endif return -EINVAL; } @@ -111,7 +109,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class, rom_vendor, rom_device); /* If the device id is mapped, a mismatch is expected */ - if ((vendor != rom_vendor || device != rom_device) && + if ((pplat->vendor != rom_vendor || pplat->device != rom_device) && (vendev == mapped_vendev)) { printf("ID mismatch: vendor ID %04x, device ID %04x\n", rom_vendor, rom_device); @@ -122,9 +120,9 @@ static int pci_rom_probe(pci_dev_t dev, uint class, debug("PCI ROM image, Class Code %06x, Code Type %02x\n", rom_class, rom_data->type); - if (class != rom_class) { + if (pplat->class != rom_class) { debug("Class Code mismatch ROM %06x, dev %06x\n", - rom_class, class); + rom_class, pplat->class); } *hdrp = rom_header; @@ -251,27 +249,26 @@ void setup_video(struct screen_info *screen_info) screen_info->rsvd_pos = vesa->reserved_mask_pos; } -int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method) +int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), + int exec_method) { + struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); struct pci_rom_header *rom, *ram; int vesa_mode = -1; - uint class; bool emulate; int ret; /* Only execute VGA ROMs */ - pci_read_config_dword(dev, PCI_REVISION_ID, &class); - if (((class >> 16) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) { - debug("%s: Class %#x, should be %#x\n", __func__, class, + if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) { + debug("%s: Class %#x, should be %#x\n", __func__, pplat->class, PCI_CLASS_DISPLAY_VGA); return -ENODEV; } - class >>= 8; if (!should_load_oprom(dev)) return -ENXIO; - ret = pci_rom_probe(dev, class, &rom); + ret = pci_rom_probe(dev, &rom); if (ret) return ret; @@ -314,12 +311,12 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method) #ifdef CONFIG_BIOSEMU BE_VGAInfo *info; - ret = biosemu_setup(dev, &info); + ret = biosemu_setup(dm_pci_get_bdf(dev), &info); if (ret) return ret; biosemu_set_interrupt_handler(0x15, int15_handler); - ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true, - vesa_mode, &mode_info); + ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16, + info, true, vesa_mode, &mode_info); if (ret) return ret; #endif diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287ee98..04541c9ff3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -15,6 +15,26 @@ config REQUIRE_SERIAL_CONSOLE during serial port initialization (default y). Set this to n on boards which have no debug serial port whatsoever. +config SERIAL_PRESENT + bool "Provide a serial driver" + depends on DM_SERIAL + default y + help + In very space-constrained devices even the full UART driver is too + large. In this case the debug UART can still be used in some cases. + This option enables the full UART in U-Boot, so if is it disabled, + the full UART driver will be omitted, thus saving space. + +config SPL_SERIAL_PRESENT + bool "Provide a serial driver in SPL" + depends on DM_SERIAL + default y + help + In very space-constrained devices even the full UART driver is too + large. In this case the debug UART can still be used in some cases. + This option enables the full UART in SPL, so if is it disabled, + the full UART driver will be omitted, thus saving space. + config DM_SERIAL bool "Enable Driver Model for serial drivers" depends on DM diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c index c8926a8945..b42537529d 100644 --- a/drivers/serial/lpc32xx_hsuart.c +++ b/drivers/serial/lpc32xx_hsuart.c @@ -1,89 +1,114 @@ /* - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clk.h> -#include <asm/arch/uart.h> -#include <asm/io.h> +#include <dm.h> #include <serial.h> +#include <dm/platform_data/lpc32xx_hsuart.h> + +#include <asm/arch/uart.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; -static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE; +struct lpc32xx_hsuart_priv { + struct hsuart_regs *hsuart; +}; -static void lpc32xx_serial_setbrg(void) +static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate) { + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; u32 div; /* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */ - div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1; + div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1; if (div > 255) div = 255; writel(div, &hsuart->rate); + + return 0; } -static int lpc32xx_serial_getc(void) +static int lpc32xx_serial_getc(struct udevice *dev) { - while (!(readl(&hsuart->level) & HSUART_LEVEL_RX)) - /* NOP */; + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; + + if (!(readl(&hsuart->level) & HSUART_LEVEL_RX)) + return -EAGAIN; return readl(&hsuart->rx) & HSUART_RX_DATA; } -static void lpc32xx_serial_putc(const char c) +static int lpc32xx_serial_putc(struct udevice *dev, const char c) { - if (c == '\n') - serial_putc('\r'); + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; + + /* Wait for empty FIFO */ + if (readl(&hsuart->level) & HSUART_LEVEL_TX) + return -EAGAIN; writel(c, &hsuart->tx); - /* Wait for character to be sent */ - while (readl(&hsuart->level) & HSUART_LEVEL_TX) - /* NOP */; + return 0; } -static int lpc32xx_serial_tstc(void) +static int lpc32xx_serial_pending(struct udevice *dev, bool input) { - if (readl(&hsuart->level) & HSUART_LEVEL_RX) - return 1; + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + struct hsuart_regs *hsuart = priv->hsuart; + + if (input) { + if (readl(&hsuart->level) & HSUART_LEVEL_RX) + return 1; + } else { + if (readl(&hsuart->level) & HSUART_LEVEL_TX) + return 1; + } return 0; } -static int lpc32xx_serial_init(void) +static int lpc32xx_serial_init(struct hsuart_regs *hsuart) { - lpc32xx_serial_setbrg(); - /* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */ writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) | HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0, &hsuart->ctrl); + return 0; } -static struct serial_device lpc32xx_serial_drv = { - .name = "lpc32xx_serial", - .start = lpc32xx_serial_init, - .stop = NULL, +static int lpc32xx_hsuart_probe(struct udevice *dev) +{ + struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev); + struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); + + priv->hsuart = (struct hsuart_regs *)platdata->base; + + lpc32xx_serial_init(priv->hsuart); + + return 0; +} + +static const struct dm_serial_ops lpc32xx_hsuart_ops = { .setbrg = lpc32xx_serial_setbrg, - .putc = lpc32xx_serial_putc, - .puts = default_serial_puts, .getc = lpc32xx_serial_getc, - .tstc = lpc32xx_serial_tstc, + .putc = lpc32xx_serial_putc, + .pending = lpc32xx_serial_pending, }; -void lpc32xx_serial_initialize(void) -{ - serial_register(&lpc32xx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &lpc32xx_serial_drv; -} +U_BOOT_DRIVER(lpc32xx_hsuart) = { + .name = "lpc32xx_hsuart", + .id = UCLASS_SERIAL, + .probe = lpc32xx_hsuart_probe, + .ops = &lpc32xx_hsuart_ops, + .priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 3fab3f1efb..021b211ab4 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -368,7 +368,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) /* try Processor Local Bus device first */ addr = dev_get_addr(dev); -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI) if (addr == FDT_ADDR_T_NONE) { /* then try pci device */ struct fdt_pci_addr pci_addr; @@ -389,8 +389,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) return ret; } - ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset, - &pci_addr, &bar); + ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar); if (ret) return ret; @@ -440,6 +439,7 @@ static const struct udevice_id ns16550_serial_ids[] = { }; #endif +#if CONFIG_IS_ENABLED(SERIAL_PRESENT) U_BOOT_DRIVER(ns16550_serial) = { .name = "ns16550_serial", .id = UCLASS_SERIAL, @@ -453,4 +453,5 @@ U_BOOT_DRIVER(ns16550_serial) = { .ops = &ns16550_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; +#endif #endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 4bf9a5c681..1c447ff27a 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -204,7 +204,7 @@ void serial_stdio_init(void) { } -#ifdef CONFIG_DM_STDIO +#if defined(CONFIG_DM_STDIO) && CONFIG_IS_ENABLED(SERIAL_PRESENT) static void serial_stub_putc(struct stdio_dev *sdev, const char ch) { _serial_putc(sdev->priv, ch); @@ -287,6 +287,7 @@ static int on_baudrate(const char *name, const char *value, enum env_op op, } U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); +#if CONFIG_IS_ENABLED(SERIAL_PRESENT) static int serial_post_probe(struct udevice *dev) { struct dm_serial_ops *ops = serial_get_ops(dev); @@ -356,3 +357,4 @@ UCLASS_DRIVER(serial) = { .pre_remove = serial_pre_remove, .per_device_auto_alloc_size = sizeof(struct serial_dev_priv), }; +#endif diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f85af9c9fb..59eaaea693 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -752,8 +752,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev) * and byte program command for SST flash */ if (plat->ich_version == 7) { - slave->op_mode_rx = SPI_OPM_RX_AS; - slave->op_mode_tx = SPI_OPM_TX_BP; + slave->mode_rx = SPI_RX_SLOW; + slave->mode = SPI_TX_BYTE; } return 0; diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index e7b0982fb6..7890796b36 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <dm.h> #include <malloc.h> #include <spi.h> #include <asm/io.h> @@ -18,6 +19,83 @@ #endif #include <asm/arch-mvebu/spi.h> +static void _spi_cs_activate(struct kwspi_registers *reg) +{ + setbits_le32(®->ctrl, KWSPI_CSN_ACT); +} + +static void _spi_cs_deactivate(struct kwspi_registers *reg) +{ + clrbits_le32(®->ctrl, KWSPI_CSN_ACT); +} + +static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + unsigned int tmpdout, tmpdin; + int tm, isread = 0; + + debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen); + + if (flags & SPI_XFER_BEGIN) + _spi_cs_activate(reg); + + /* + * handle data in 8-bit chunks + * TBD: 2byte xfer mode to be enabled + */ + clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); + + while (bitlen > 4) { + debug("loopstart bitlen %d\n", bitlen); + tmpdout = 0; + + /* Shift data so it's msb-justified */ + if (dout) + tmpdout = *(u32 *)dout & 0xff; + + clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ); + writel(tmpdout, ®->dout); /* Write the data out */ + debug("*** spi_xfer: ... %08x written, bitlen %d\n", + tmpdout, bitlen); + + /* + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * The NE event must be read and cleared first + */ + for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) { + if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) { + isread = 1; + tmpdin = readl(®->din); + debug("spi_xfer: din %p..%08x read\n", + din, tmpdin); + + if (din) { + *((u8 *)din) = (u8)tmpdin; + din += 1; + } + if (dout) + dout += 1; + bitlen -= 8; + } + if (isread) + break; + } + if (tm >= KWSPI_TIMEOUT) + printf("*** spi_xfer: Time out during SPI transfer\n"); + + debug("loopend bitlen %d\n", bitlen); + } + + if (flags & SPI_XFER_END) + _spi_cs_deactivate(reg); + + return 0; +} + +#ifndef CONFIG_DM_SPI + static struct kwspi_registers *spireg = (struct kwspi_registers *)MVEBU_SPI_BASE; @@ -147,76 +225,109 @@ void spi_init(void) void spi_cs_activate(struct spi_slave *slave) { - setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT); + _spi_cs_activate(spireg); } void spi_cs_deactivate(struct spi_slave *slave) { - clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT); + _spi_cs_deactivate(spireg); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { - unsigned int tmpdout, tmpdin; - int tm, isread = 0; + return _spi_xfer(spireg, bitlen, dout, din, flags); +} - debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", - slave->bus, slave->cs, dout, din, bitlen); +#else - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); +/* Here now the DM part */ - /* - * handle data in 8-bit chunks - * TBD: 2byte xfer mode to be enabled - */ - clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); +struct mvebu_spi_platdata { + struct kwspi_registers *spireg; +}; - while (bitlen > 4) { - debug("loopstart bitlen %d\n", bitlen); - tmpdout = 0; +struct mvebu_spi_priv { + struct kwspi_registers *spireg; +}; - /* Shift data so it's msb-justified */ - if (dout) - tmpdout = *(u32 *)dout & 0xff; +static int mvebu_spi_set_speed(struct udevice *bus, uint hz) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; + u32 data; - clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ); - writel(tmpdout, &spireg->dout); /* Write the data out */ - debug("*** spi_xfer: ... %08x written, bitlen %d\n", - tmpdout, bitlen); + /* calculate spi clock prescaller using max_hz */ + data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10; + data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; + data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; - /* - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * The NE event must be read and cleared first - */ - for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) { - if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) { - isread = 1; - tmpdin = readl(&spireg->din); - debug("spi_xfer: din %p..%08x read\n", - din, tmpdin); + /* program spi clock prescaler using max_hz */ + writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg); + debug("data = 0x%08x\n", data); - if (din) { - *((u8 *)din) = (u8)tmpdin; - din += 1; - } - if (dout) - dout += 1; - bitlen -= 8; - } - if (isread) - break; - } - if (tm >= KWSPI_TIMEOUT) - printf("*** spi_xfer: Time out during SPI transfer\n"); + return 0; +} - debug("loopend bitlen %d\n", bitlen); - } +static int mvebu_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); +static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + + return _spi_xfer(plat->spireg, bitlen, dout, din, flags); +} + +static int mvebu_spi_probe(struct udevice *bus) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; + + writel(KWSPI_SMEMRDY, ®->ctrl); + writel(KWSPI_SMEMRDIRQ, ®->irq_cause); + writel(KWSPI_IRQMASK, ®->irq_mask); + + return 0; +} + +static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + + plat->spireg = (struct kwspi_registers *)dev_get_addr(bus); return 0; } + +static const struct dm_spi_ops mvebu_spi_ops = { + .xfer = mvebu_spi_xfer, + .set_speed = mvebu_spi_set_speed, + .set_mode = mvebu_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id mvebu_spi_ids[] = { + { .compatible = "marvell,armada-380-spi" }, + { .compatible = "marvell,armada-xp-spi" }, + { } +}; + +U_BOOT_DRIVER(mvebu_spi) = { + .name = "mvebu_spi", + .id = UCLASS_SPI, + .of_match = mvebu_spi_ids, + .ops = &mvebu_spi_ops, + .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata), + .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv), + .probe = mvebu_spi_probe, +}; +#endif diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index e0f6b25f30..677c020b11 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -157,6 +157,7 @@ static int spi_child_pre_probe(struct udevice *dev) slave->max_hz = plat->max_hz; slave->mode = plat->mode; + slave->mode_rx = plat->mode_rx; return 0; } @@ -368,7 +369,8 @@ void spi_free_slave(struct spi_slave *slave) int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) { - int mode = 0; + int mode = 0, mode_rx = 0; + int value; plat->cs = fdtdec_get_int(blob, node, "reg", -1); plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0); @@ -382,8 +384,42 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_3WIRE; if (fdtdec_get_bool(blob, node, "spi-half-duplex")) mode |= SPI_PREAMBLE; + + /* Device DUAL/QUAD mode */ + value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_TX_DUAL; + break; + case 4: + mode |= SPI_TX_QUAD; + break; + default: + error("spi-tx-bus-width %d not supported\n", value); + break; + } + plat->mode = mode; + value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode_rx |= SPI_RX_DUAL; + break; + case 4: + mode_rx |= SPI_RX_QUAD; + break; + default: + error("spi-rx-bus-width %d not supported\n", value); + break; + } + + plat->mode_rx = mode_rx; + return 0; } diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 5747ed1fa9..78d8b1368d 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -11,11 +11,14 @@ #include <asm/arch/omap.h> #include <malloc.h> #include <spi.h> +#include <dm.h> #include <asm/gpio.h> #include <asm/omap_gpio.h> #include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h> +DECLARE_GLOBAL_DATA_PTR; + /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 #define QSPI_FCLK 192000000 @@ -41,19 +44,21 @@ #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) #define QSPI_XFER_DONE QSPI_WC #define MM_SWITCH 0x01 -#define MEM_CS 0x100 +#define MEM_CS(cs) ((cs + 1) << 8) #define MEM_CS_UNSELECT 0xfffff0ff #define MMAP_START_ADDR_DRA 0x5c000000 #define MMAP_START_ADDR_AM43x 0x30000000 #define CORE_CTRL_IO 0x4a002558 #define QSPI_CMD_READ (0x3 << 0) +#define QSPI_CMD_READ_DUAL (0x6b << 0) #define QSPI_CMD_READ_QUAD (0x6b << 0) #define QSPI_CMD_READ_FAST (0x0b << 0) #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) +#define QSPI_SETUP0_READ_DUAL (0x1 << 12) #define QSPI_SETUP0_READ_QUAD (0x3 << 12) #define QSPI_CMD_WRITE (0x2 << 16) #define QSPI_NUM_DUMMY_BITS (0x0 << 24) @@ -85,50 +90,24 @@ struct ti_qspi_regs { u32 data3; }; -/* ti qspi slave */ -struct ti_qspi_slave { +/* ti qspi priv */ +struct ti_qspi_priv { +#ifndef CONFIG_DM_SPI struct spi_slave slave; +#else + void *memory_map; + uint max_hz; + u32 num_cs; +#endif struct ti_qspi_regs *base; + void *ctrl_mod_mmap; unsigned int mode; u32 cmd; u32 dc; }; -static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave) -{ - return container_of(slave, struct ti_qspi_slave, slave); -} - -static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) +static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) { - struct spi_slave *slave = &qslave->slave; - u32 memval = 0; - -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - slave->memory_map = (void *)MMAP_START_ADDR_DRA; -#else - slave->memory_map = (void *)MMAP_START_ADDR_AM43x; -#endif - -#ifdef CONFIG_QSPI_QUAD_SUPPORT - memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_8_BITS | - QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS); - slave->op_mode_rx = SPI_OPM_RX_QOF; -#else - memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_NO_BITS | - QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS; -#endif - - writel(memval, &qslave->base->setup0); -} - -static void ti_spi_set_speed(struct spi_slave *slave, uint hz) -{ - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); uint clk_div; debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); @@ -139,8 +118,8 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) clk_div = (QSPI_FCLK / hz) - 1; /* disable SCLK */ - writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN, - &qslave->base->clk_ctrl); + writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, + &priv->base->clk_ctrl); /* assign clk_div values */ if (clk_div < 0) @@ -149,135 +128,80 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) clk_div = QSPI_CLK_DIV_MAX; /* enable SCLK */ - writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return 1; + writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); } -void spi_cs_activate(struct spi_slave *slave) +static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) { - /* CS handled in xfer */ - return; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); - - debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); - - writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd); + writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); /* dummy readl to ensure bus sync */ - readl(&qslave->base->cmd); + readl(&priv->base->cmd); } -void spi_init(void) +static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) { - /* nothing to do */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct ti_qspi_slave *qslave; - -#ifdef CONFIG_AM43XX - gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); - gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); -#endif - - qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); - if (!qslave) { - printf("SPI_error: Fail to allocate ti_qspi_slave\n"); - return NULL; - } - - qslave->base = (struct ti_qspi_regs *)QSPI_BASE; - qslave->mode = mode; - - ti_spi_set_speed(&qslave->slave, max_hz); + priv->dc = 0; + if (mode & SPI_CPHA) + priv->dc |= QSPI_CKPHA(0); + if (mode & SPI_CPOL) + priv->dc |= QSPI_CKPOL(0); + if (mode & SPI_CS_HIGH) + priv->dc |= QSPI_CSPOL(0); -#ifdef CONFIG_TI_SPI_MMAP - ti_spi_setup_spi_register(qslave); -#endif - - return &qslave->slave; + return 0; } -void spi_free_slave(struct spi_slave *slave) +static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); - free(qslave); -} + writel(priv->dc, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data); -int spi_claim_bus(struct spi_slave *slave) -{ - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); - - debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); - - qslave->dc = 0; - if (qslave->mode & SPI_CPHA) - qslave->dc |= QSPI_CKPHA(slave->cs); - if (qslave->mode & SPI_CPOL) - qslave->dc |= QSPI_CKPOL(slave->cs); - if (qslave->mode & SPI_CS_HIGH) - qslave->dc |= QSPI_CSPOL(slave->cs); - - writel(qslave->dc, &qslave->base->dc); - writel(0, &qslave->base->cmd); - writel(0, &qslave->base->data); + priv->dc <<= cs * 8; + writel(priv->dc, &priv->base->dc); return 0; } -void spi_release_bus(struct spi_slave *slave) +static void __ti_qspi_release_bus(struct ti_qspi_priv *priv) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + writel(0, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data); +} - debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); +static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) +{ + u32 val; - writel(0, &qslave->base->dc); - writel(0, &qslave->base->cmd); - writel(0, &qslave->base->data); + val = readl(ctrl_mod_mmap); + if (enable) + val |= MEM_CS(cs); + else + val &= MEM_CS_UNSELECT; + writel(val, ctrl_mod_mmap); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, + const void *dout, void *din, unsigned long flags, + u32 cs) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); uint words = bitlen >> 3; /* fixed 8-bit word length */ const uchar *txp = dout; uchar *rxp = din; uint status; int timeout; -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - int val; -#endif - - debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", - slave->bus, slave->cs, bitlen, words, flags); - /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { - writel(MM_SWITCH, &qslave->base->memswitch); -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - val = readl(CORE_CTRL_IO); - val |= MEM_CS; - writel(val, CORE_CTRL_IO); -#endif + writel(MM_SWITCH, &priv->base->memswitch); + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true); return 0; } else if (flags & SPI_XFER_MMAP_END) { - writel(~MM_SWITCH, &qslave->base->memswitch); -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - val = readl(CORE_CTRL_IO); - val &= MEM_CS_UNSELECT; - writel(val, CORE_CTRL_IO); -#endif + writel(~MM_SWITCH, &priv->base->memswitch); + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false); return 0; } @@ -290,12 +214,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } /* Setup command reg */ - qslave->cmd = 0; - qslave->cmd |= QSPI_WLEN(8); - qslave->cmd |= QSPI_EN_CS(slave->cs); - if (qslave->mode & SPI_3WIRE) - qslave->cmd |= QSPI_3_PIN; - qslave->cmd |= 0xfff; + priv->cmd = 0; + priv->cmd |= QSPI_WLEN(8); + priv->cmd |= QSPI_EN_CS(cs); + if (priv->mode & SPI_3WIRE) + priv->cmd |= QSPI_3_PIN; + priv->cmd |= 0xfff; /* FIXME: This delay is required for successfull * completion of read/write/erase. Once its root @@ -307,39 +231,39 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, while (words--) { if (txp) { debug("tx cmd %08x dc %08x data %02x\n", - qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); - writel(*txp++, &qslave->base->data); - writel(qslave->cmd | QSPI_WR_SNGL, - &qslave->base->cmd); - status = readl(&qslave->base->status); + priv->cmd | QSPI_WR_SNGL, priv->dc, *txp); + writel(*txp++, &priv->base->data); + writel(priv->cmd | QSPI_WR_SNGL, + &priv->base->cmd); + status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { if (--timeout < 0) { printf("spi_xfer: TX timeout!\n"); return -1; } - status = readl(&qslave->base->status); + status = readl(&priv->base->status); } debug("tx done, status %08x\n", status); } if (rxp) { - qslave->cmd |= QSPI_RD_SNGL; + priv->cmd |= QSPI_RD_SNGL; debug("rx cmd %08x dc %08x\n", - qslave->cmd, qslave->dc); + priv->cmd, priv->dc); #ifdef CONFIG_DRA7XX udelay(500); #endif - writel(qslave->cmd, &qslave->base->cmd); - status = readl(&qslave->base->status); + writel(priv->cmd, &priv->base->cmd); + status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { if (--timeout < 0) { printf("spi_xfer: RX timeout!\n"); return -1; } - status = readl(&qslave->base->status); + status = readl(&priv->base->status); } - *rxp++ = readl(&qslave->base->data); + *rxp++ = readl(&priv->base->data); debug("rx done, status %08x, read %02x\n", status, *(rxp-1)); } @@ -347,7 +271,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Terminate frame */ if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + ti_qspi_cs_deactivate(priv); return 0; } @@ -374,3 +298,293 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len) *((unsigned int *)offset) += len; } #endif + +#ifndef CONFIG_DM_SPI + +static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) +{ + return container_of(slave, struct ti_qspi_priv, slave); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + ti_qspi_cs_deactivate(priv); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) +{ + u32 memval = 0; + +#ifdef CONFIG_QSPI_QUAD_SUPPORT + struct spi_slave *slave = &priv->slave; + memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | + QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS); + slave->mode_rx = SPI_RX_QUAD; +#else + memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_NO_BITS | + QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS; +#endif + + writel(memval, &priv->base->setup0); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ti_qspi_priv *priv; + +#ifdef CONFIG_AM43XX + gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); + gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); +#endif + + priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); + if (!priv) { + printf("SPI_error: Fail to allocate ti_qspi_priv\n"); + return NULL; + } + + priv->base = (struct ti_qspi_regs *)QSPI_BASE; + priv->mode = mode; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; + priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; +#else + priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; +#endif + + ti_spi_set_speed(priv, max_hz); + +#ifdef CONFIG_TI_SPI_MMAP + ti_spi_setup_spi_register(priv); +#endif + + return &priv->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + free(priv); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); + __ti_qspi_set_mode(priv, priv->mode); + return __ti_qspi_claim_bus(priv, priv->slave.cs); +} +void spi_release_bus(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); + __ti_qspi_release_bus(priv); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n", + priv->slave.bus, priv->slave.cs, bitlen, flags); + return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); +} + +#else /* CONFIG_DM_SPI */ + +static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, + struct spi_slave *slave, + bool enable) +{ + u32 memval; + u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL); + + if (!enable) { + writel(0, &priv->base->setup0); + return; + } + + memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; + + switch (mode) { + case SPI_RX_QUAD: + memval |= QSPI_CMD_READ_QUAD; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_QUAD; + slave->mode_rx = SPI_RX_QUAD; + break; + case SPI_RX_DUAL: + memval |= QSPI_CMD_READ_DUAL; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_DUAL; + break; + default: + memval |= QSPI_CMD_READ; + memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS; + memval |= QSPI_SETUP0_READ_NORMAL; + break; + } + + writel(memval, &priv->base->setup0); +} + + +static int ti_qspi_set_speed(struct udevice *bus, uint max_hz) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + + ti_spi_set_speed(priv, max_hz); + + return 0; +} + +static int ti_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + return __ti_qspi_set_mode(priv, mode); +} + +static int ti_qspi_claim_bus(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave_plat->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + + __ti_qspi_setup_memorymap(priv, slave, true); + + return __ti_qspi_claim_bus(priv, slave_plat->cs); +} + +static int ti_qspi_release_bus(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + __ti_qspi_setup_memorymap(priv, slave, false); + __ti_qspi_release_bus(priv); + + return 0; +} + +static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + + return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs); +} + +static int ti_qspi_probe(struct udevice *bus) +{ + /* Nothing to do in probe */ + return 0; +} + +static int ti_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + fdt_addr_t addr; + + priv->base = (struct ti_qspi_regs *)dev_get_addr(bus); + priv->memory_map = (void *)dev_get_addr_index(bus, 1); + addr = dev_get_addr_index(bus, 2); + priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr; + + priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); + if (priv->max_hz < 0) { + debug("Error: Max frequency missing\n"); + return -ENODEV; + } + priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + + debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__, + (int)priv->base, priv->max_hz); + + return 0; +} + +static int ti_qspi_child_pre_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + struct udevice *bus = dev_get_parent(dev); + struct ti_qspi_priv *priv = dev_get_priv(bus); + + slave->memory_map = priv->memory_map; + return 0; +} + +static const struct dm_spi_ops ti_qspi_ops = { + .claim_bus = ti_qspi_claim_bus, + .release_bus = ti_qspi_release_bus, + .xfer = ti_qspi_xfer, + .set_speed = ti_qspi_set_speed, + .set_mode = ti_qspi_set_mode, +}; + +static const struct udevice_id ti_qspi_ids[] = { + { .compatible = "ti,dra7xxx-qspi" }, + { .compatible = "ti,am4372-qspi" }, + { } +}; + +U_BOOT_DRIVER(ti_qspi) = { + .name = "ti_qspi", + .id = UCLASS_SPI, + .of_match = ti_qspi_ids, + .ops = &ti_qspi_ops, + .ofdata_to_platdata = ti_qspi_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct ti_qspi_priv), + .probe = ti_qspi_probe, + .child_pre_probe = ti_qspi_child_pre_probe, +}; +#endif /* CONFIG_DM_SPI */ diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index bbdad8b79a..9d6cf8ce7b 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <linux/mii.h> #include <malloc.h> @@ -83,19 +84,23 @@ struct mcs7830_regs { * @mchash: shadow for the network adapter's multicast hash registers */ struct mcs7830_private { +#ifdef CONFIG_DM_ETH + uint8_t rx_buf[MCS7830_RX_URB_SIZE]; + struct ueth_data ueth; +#endif uint8_t config; uint8_t mchash[8]; }; /* * mcs7830_read_reg() - read a register of the network adapter - * @dev: network device to read from + * @udev: network device to read from * @idx: index of the register to start reading from * @size: number of bytes to read * @data: buffer to read into * Return: zero upon success, negative upon error */ -static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx, +static int mcs7830_read_reg(struct usb_device *udev, uint8_t idx, uint16_t size, void *data) { int len; @@ -103,8 +108,8 @@ static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx, debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size); - len = usb_control_msg(dev->pusb_dev, - usb_rcvctrlpipe(dev->pusb_dev, 0), + len = usb_control_msg(udev, + usb_rcvctrlpipe(udev, 0), MCS7830_RD_BREQ, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 0, idx, buf, size, @@ -119,13 +124,13 @@ static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx, /* * mcs7830_write_reg() - write a register of the network adapter - * @dev: network device to write to + * @udev: network device to write to * @idx: index of the register to start writing to * @size: number of bytes to write * @data: buffer holding the data to write * Return: zero upon success, negative upon error */ -static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx, +static int mcs7830_write_reg(struct usb_device *udev, uint8_t idx, uint16_t size, void *data) { int len; @@ -134,8 +139,8 @@ static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx, debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size); memcpy(buf, data, size); - len = usb_control_msg(dev->pusb_dev, - usb_sndctrlpipe(dev->pusb_dev, 0), + len = usb_control_msg(udev, + usb_sndctrlpipe(udev, 0), MCS7830_WR_BREQ, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 0, idx, buf, size, @@ -149,12 +154,12 @@ static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx, /* * mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution - * @dev: network device to talk to + * @udev: network device to talk to * @rwflag: PHY_CMD1_READ or PHY_CMD1_WRITE opcode * @index: number of the PHY register to read or write * Return: zero upon success, negative upon error */ -static int mcs7830_phy_emit_wait(struct ueth_data *dev, +static int mcs7830_phy_emit_wait(struct usb_device *udev, uint8_t rwflag, uint8_t index) { int rc; @@ -164,14 +169,14 @@ static int mcs7830_phy_emit_wait(struct ueth_data *dev, /* send the PHY read/write request */ cmd[0] = rwflag | PHY_CMD1_PHYADDR; cmd[1] = PHY_CMD2_PEND | (index & 0x1f); - rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd); + rc = mcs7830_write_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd); if (rc < 0) return rc; /* wait for the response to become available (usually < 1ms) */ retry = 10; do { - rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd); + rc = mcs7830_read_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd); if (rc < 0) return rc; if (cmd[1] & PHY_CMD2_READY) @@ -185,50 +190,51 @@ static int mcs7830_phy_emit_wait(struct ueth_data *dev, /* * mcs7830_read_phy() - read a PHY register of the network adapter - * @dev: network device to read from + * @udev: network device to read from * @index: index of the PHY register to read from * Return: non-negative 16bit register content, negative upon error */ -static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index) +static int mcs7830_read_phy(struct usb_device *udev, uint8_t index) { int rc; uint16_t val; /* issue the PHY read request and wait for its execution */ - rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index); + rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_READ, index); if (rc < 0) return rc; /* fetch the PHY data which was read */ - rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val); + rc = mcs7830_read_reg(udev, REG_PHY_DATA, sizeof(val), &val); if (rc < 0) return rc; rc = le16_to_cpu(val); - debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc); + debug("%s(%d) => 0x%04X\n", __func__, index, rc); return rc; } /* * mcs7830_write_phy() - write a PHY register of the network adapter - * @dev: network device to write to + * @udev: network device to write to * @index: index of the PHY register to write to * @val: value to write to the PHY register * Return: zero upon success, negative upon error */ -static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val) +static int mcs7830_write_phy(struct usb_device *udev, uint8_t index, + uint16_t val) { int rc; - debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val); + debug("%s(%d, 0x%04X)\n", __func__, index, val); /* setup the PHY data which is to get written */ val = cpu_to_le16(val); - rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val); + rc = mcs7830_write_reg(udev, REG_PHY_DATA, sizeof(val), &val); if (rc < 0) return rc; /* issue the PHY write request and wait for its execution */ - rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index); + rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_WRITE, index); if (rc < 0) return rc; @@ -237,21 +243,21 @@ static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val) /* * mcs7830_write_config() - write to the network adapter's config register - * @eth: network device to write to + * @udev: network device to write to + * @priv: private data * Return: zero upon success, negative upon error * * the data which gets written is taken from the shadow config register * within the device driver's private data */ -static int mcs7830_write_config(struct ueth_data *dev) +static int mcs7830_write_config(struct usb_device *udev, + struct mcs7830_private *priv) { - struct mcs7830_private *priv; int rc; debug("%s()\n", __func__); - priv = dev->dev_priv; - rc = mcs7830_write_reg(dev, REG_CONFIG, + rc = mcs7830_write_reg(udev, REG_CONFIG, sizeof(priv->config), &priv->config); if (rc < 0) { debug("writing config to adapter failed\n"); @@ -263,21 +269,21 @@ static int mcs7830_write_config(struct ueth_data *dev) /* * mcs7830_write_mchash() - write the network adapter's multicast filter - * @eth: network device to write to + * @udev: network device to write to + * @priv: private data * Return: zero upon success, negative upon error * * the data which gets written is taken from the shadow multicast hashes * within the device driver's private data */ -static int mcs7830_write_mchash(struct ueth_data *dev) +static int mcs7830_write_mchash(struct usb_device *udev, + struct mcs7830_private *priv) { - struct mcs7830_private *priv; int rc; debug("%s()\n", __func__); - priv = dev->dev_priv; - rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH, + rc = mcs7830_write_reg(udev, REG_MULTICAST_HASH, sizeof(priv->mchash), &priv->mchash); if (rc < 0) { debug("writing multicast hash to adapter failed\n"); @@ -289,12 +295,12 @@ static int mcs7830_write_mchash(struct ueth_data *dev) /* * mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation - * @eth: network device to run link negotiation on + * @udev: network device to run link negotiation on * Return: zero upon success, negative upon error * * the routine advertises available media and starts autonegotiation */ -static int mcs7830_set_autoneg(struct ueth_data *dev) +static int mcs7830_set_autoneg(struct usb_device *udev) { int adv, flg; int rc; @@ -310,39 +316,39 @@ static int mcs7830_set_autoneg(struct ueth_data *dev) */ adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA; - rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv); + rc = mcs7830_write_phy(udev, MII_ADVERTISE, adv); flg = 0; if (!rc) - rc = mcs7830_write_phy(dev, MII_BMCR, flg); + rc = mcs7830_write_phy(udev, MII_BMCR, flg); flg |= BMCR_ANENABLE; if (!rc) - rc = mcs7830_write_phy(dev, MII_BMCR, flg); + rc = mcs7830_write_phy(udev, MII_BMCR, flg); flg |= BMCR_ANRESTART; if (!rc) - rc = mcs7830_write_phy(dev, MII_BMCR, flg); + rc = mcs7830_write_phy(udev, MII_BMCR, flg); return rc; } /* * mcs7830_get_rev() - identify a network adapter's chip revision - * @eth: network device to identify + * @udev: network device to identify * Return: non-negative number, reflecting the revision number * * currently, only "rev C and higher" and "below rev C" are needed, so * the return value is #1 for "below rev C", and #2 for "rev C and above" */ -static int mcs7830_get_rev(struct ueth_data *dev) +static int mcs7830_get_rev(struct usb_device *udev) { uint8_t buf[2]; int rc; int rev; /* register 22 is readable in rev C and higher */ - rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf); + rc = mcs7830_read_reg(udev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf); if (rc < 0) rev = 1; else @@ -353,19 +359,19 @@ static int mcs7830_get_rev(struct ueth_data *dev) /* * mcs7830_apply_fixup() - identify an adapter and potentially apply fixups - * @eth: network device to identify and apply fixups to + * @udev: network device to identify and apply fixups to * Return: zero upon success (no errors emitted from here) * * this routine identifies the network adapter's chip revision, and applies * fixups for known issues */ -static int mcs7830_apply_fixup(struct ueth_data *dev) +static int mcs7830_apply_fixup(struct usb_device *udev) { int rev; int i; uint8_t thr; - rev = mcs7830_get_rev(dev); + rev = mcs7830_get_rev(udev); debug("%s() rev=%d\n", __func__, rev); /* @@ -374,10 +380,10 @@ static int mcs7830_apply_fixup(struct ueth_data *dev) * exactly", the introductory comment says "rev C and above") */ if (rev == 2) { - debug("%s: applying rev C fixup\n", dev->eth_dev.name); + debug("%s: applying rev C fixup\n", __func__); thr = PAUSE_THRESHOLD_DEFAULT; for (i = 0; i < 2; i++) { - (void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD, + (void)mcs7830_write_reg(udev, REG_PAUSE_THRESHOLD, sizeof(thr), &thr); mdelay(1); } @@ -395,13 +401,12 @@ static int mcs7830_apply_fixup(struct ueth_data *dev) * of the interface callbacks can exchange ethernet frames; link negotiation is * triggered from here already and continues in background */ -static int mcs7830_basic_reset(struct ueth_data *dev) +static int mcs7830_basic_reset(struct usb_device *udev, + struct mcs7830_private *priv) { - struct mcs7830_private *priv; int rc; debug("%s()\n", __func__); - priv = dev->dev_priv; /* * comment from the respective Linux driver, which @@ -411,25 +416,25 @@ static int mcs7830_basic_reset(struct ueth_data *dev) priv->config = CONF_TXENABLE; priv->config |= CONF_ALLMULTICAST; - rc = mcs7830_set_autoneg(dev); + rc = mcs7830_set_autoneg(udev); if (rc < 0) { error("setting autoneg failed\n"); return rc; } - rc = mcs7830_write_mchash(dev); + rc = mcs7830_write_mchash(udev, priv); if (rc < 0) { error("failed to set multicast hash\n"); return rc; } - rc = mcs7830_write_config(dev); + rc = mcs7830_write_config(udev, priv); if (rc < 0) { error("failed to set configuration\n"); return rc; } - rc = mcs7830_apply_fixup(dev); + rc = mcs7830_apply_fixup(udev); if (rc < 0) { error("fixup application failed\n"); return rc; @@ -440,51 +445,38 @@ static int mcs7830_basic_reset(struct ueth_data *dev) /* * mcs7830_read_mac() - read an ethernet adapter's MAC address - * @eth: network device to read from + * @udev: network device to read from + * @enetaddr: place to put ethernet MAC address * Return: zero upon success, negative upon error * * this routine fetches the MAC address stored within the ethernet adapter, * and stores it in the ethernet interface's data structure */ -static int mcs7830_read_mac(struct eth_device *eth) +static int mcs7830_read_mac(struct usb_device *udev, unsigned char enetaddr[]) { - struct ueth_data *dev; int rc; uint8_t buf[ETH_ALEN]; debug("%s()\n", __func__); - dev = eth->priv; - rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf); + rc = mcs7830_read_reg(udev, REG_ETHER_ADDR, ETH_ALEN, buf); if (rc < 0) { debug("reading MAC from adapter failed\n"); return rc; } - memcpy(ð->enetaddr[0], buf, ETH_ALEN); + memcpy(enetaddr, buf, ETH_ALEN); return 0; } -/* - * mcs7830_write_mac() - write an ethernet adapter's MAC address - * @eth: network device to write to - * Return: zero upon success, negative upon error - * - * this routine takes the MAC address from the ethernet interface's data - * structure, and writes it into the ethernet adapter such that subsequent - * exchange of ethernet frames uses this address - */ -static int mcs7830_write_mac(struct eth_device *eth) +static int mcs7830_write_mac_common(struct usb_device *udev, + unsigned char enetaddr[]) { - struct ueth_data *dev; int rc; debug("%s()\n", __func__); - dev = eth->priv; - if (sizeof(eth->enetaddr) != ETH_ALEN) - return -EINVAL; - rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr); + rc = mcs7830_write_reg(udev, REG_ETHER_ADDR, ETH_ALEN, enetaddr); if (rc < 0) { debug("writing MAC to adapter failed\n"); return rc; @@ -492,28 +484,16 @@ static int mcs7830_write_mac(struct eth_device *eth) return 0; } -/* - * mcs7830_init() - network interface's init callback - * @eth: network device to initialize - * @bd: board information - * Return: zero upon success, negative upon error - * - * after initial setup during probe() and get_info(), this init() callback - * ensures that the link is up and subsequent send() and recv() calls can - * exchange ethernet frames - */ -static int mcs7830_init(struct eth_device *eth, bd_t *bd) +static int mcs7830_init_common(struct usb_device *udev) { - struct ueth_data *dev; int timeout; int have_link; debug("%s()\n", __func__); - dev = eth->priv; timeout = 0; do { - have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS; + have_link = mcs7830_read_phy(udev, MII_BMSR) & BMSR_LSTATUS; if (have_link) break; udelay(LINKSTATUS_TIMEOUT_RES * 1000); @@ -526,28 +506,18 @@ static int mcs7830_init(struct eth_device *eth, bd_t *bd) return 0; } -/* - * mcs7830_send() - network interface's send callback - * @eth: network device to send the frame from - * @packet: ethernet frame content - * @length: ethernet frame length - * Return: zero upon success, negative upon error - * - * this routine send an ethernet frame out of the network interface - */ -static int mcs7830_send(struct eth_device *eth, void *packet, int length) +static int mcs7830_send_common(struct ueth_data *ueth, void *packet, + int length) { - struct ueth_data *dev; + struct usb_device *udev = ueth->pusb_dev; int rc; int gotlen; /* there is a status byte after the ethernet frame */ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t)); - dev = eth->priv; - memcpy(buf, packet, length); - rc = usb_bulk_msg(dev->pusb_dev, - usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), + rc = usb_bulk_msg(udev, + usb_sndbulkpipe(udev, ueth->ep_out), &buf[0], length, &gotlen, USBCALL_TIMEOUT); debug("%s() TX want len %d, got len %d, rc %d\n", @@ -555,28 +525,17 @@ static int mcs7830_send(struct eth_device *eth, void *packet, int length) return rc; } -/* - * mcs7830_recv() - network interface's recv callback - * @eth: network device to receive frames from - * Return: zero upon success, negative upon error - * - * this routine checks for available ethernet frames that the network - * interface might have received, and notifies the network stack - */ -static int mcs7830_recv(struct eth_device *eth) +static int mcs7830_recv_common(struct ueth_data *ueth, uint8_t *buf) { - struct ueth_data *dev; - ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE); int rc, wantlen, gotlen; uint8_t sts; debug("%s()\n", __func__); - dev = eth->priv; /* fetch input data from the adapter */ wantlen = MCS7830_RX_URB_SIZE; - rc = usb_bulk_msg(dev->pusb_dev, - usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), + rc = usb_bulk_msg(ueth->pusb_dev, + usb_rcvbulkpipe(ueth->pusb_dev, ueth->ep_in), &buf[0], wantlen, &gotlen, USBCALL_TIMEOUT); debug("%s() RX want len %d, got len %d, rc %d\n", @@ -601,8 +560,7 @@ static int mcs7830_recv(struct eth_device *eth) if (sts == STAT_RX_FRAME_CORRECT) { debug("%s() got a frame, len=%d\n", __func__, gotlen); - net_process_received_packet(buf, gotlen); - return 0; + return gotlen; } debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n", @@ -615,6 +573,61 @@ static int mcs7830_recv(struct eth_device *eth) return -EIO; } +#ifndef CONFIG_DM_ETH +/* + * mcs7830_init() - network interface's init callback + * @udev: network device to initialize + * @bd: board information + * Return: zero upon success, negative upon error + * + * after initial setup during probe() and get_info(), this init() callback + * ensures that the link is up and subsequent send() and recv() calls can + * exchange ethernet frames + */ +static int mcs7830_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = eth->priv; + + return mcs7830_init_common(dev->pusb_dev); +} + +/* + * mcs7830_send() - network interface's send callback + * @eth: network device to send the frame from + * @packet: ethernet frame content + * @length: ethernet frame length + * Return: zero upon success, negative upon error + * + * this routine send an ethernet frame out of the network interface + */ +static int mcs7830_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev = eth->priv; + + return mcs7830_send_common(dev, packet, length); +} + +/* + * mcs7830_recv() - network interface's recv callback + * @eth: network device to receive frames from + * Return: zero upon success, negative upon error + * + * this routine checks for available ethernet frames that the network + * interface might have received, and notifies the network stack + */ +static int mcs7830_recv(struct eth_device *eth) +{ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE); + struct ueth_data *ueth = eth->priv; + int len; + + len = mcs7830_recv_common(ueth, buf); + if (len <= 0) + net_process_received_packet(buf, len); + + return 0; +} + /* * mcs7830_halt() - network interface's halt callback * @eth: network device to cease operation of @@ -629,6 +642,22 @@ static void mcs7830_halt(struct eth_device *eth) } /* + * mcs7830_write_mac() - write an ethernet adapter's MAC address + * @eth: network device to write to + * Return: zero upon success, negative upon error + * + * this routine takes the MAC address from the ethernet interface's data + * structure, and writes it into the ethernet adapter such that subsequent + * exchange of ethernet frames uses this address + */ +static int mcs7830_write_mac(struct eth_device *eth) +{ + struct ueth_data *ueth = eth->priv; + + return mcs7830_write_mac_common(ueth->pusb_dev, eth->enetaddr); +} + +/* * mcs7830_iface_idx - index of detected network interfaces * * this counter keeps track of identified supported interfaces, @@ -802,12 +831,111 @@ int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, eth->write_hwaddr = mcs7830_write_mac; eth->priv = ss; - if (mcs7830_basic_reset(ss)) + if (mcs7830_basic_reset(ss->pusb_dev, ss->dev_priv)) return 0; - if (mcs7830_read_mac(eth)) + if (mcs7830_read_mac(ss->pusb_dev, eth->enetaddr)) return 0; debug("MAC %pM\n", eth->enetaddr); return 1; } +#endif + + +#ifdef CONFIG_DM_ETH +static int mcs7830_eth_start(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + + return mcs7830_init_common(udev); +} + +void mcs7830_eth_stop(struct udevice *dev) +{ + debug("** %s()\n", __func__); +} + +int mcs7830_eth_send(struct udevice *dev, void *packet, int length) +{ + struct mcs7830_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + + return mcs7830_send_common(ueth, packet, length); +} + +int mcs7830_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct mcs7830_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + int len; + + len = mcs7830_recv_common(ueth, priv->rx_buf); + *packetp = priv->rx_buf; + + return len; +} + +static int mcs7830_free_pkt(struct udevice *dev, uchar *packet, int packet_len) +{ + struct mcs7830_private *priv = dev_get_priv(dev); + + packet_len = ALIGN(packet_len, 4); + usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len); + + return 0; +} + +int mcs7830_write_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + return mcs7830_write_mac_common(udev, pdata->enetaddr); +} + +static int mcs7830_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct mcs7830_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ueth_data *ueth = &priv->ueth; + + if (mcs7830_basic_reset(udev, priv)) + return 0; + + if (mcs7830_read_mac(udev, pdata->enetaddr)) + return 0; + + return usb_ether_register(dev, ueth, MCS7830_RX_URB_SIZE); +} + +static const struct eth_ops mcs7830_eth_ops = { + .start = mcs7830_eth_start, + .send = mcs7830_eth_send, + .recv = mcs7830_eth_recv, + .free_pkt = mcs7830_free_pkt, + .stop = mcs7830_eth_stop, + .write_hwaddr = mcs7830_write_hwaddr, +}; + +U_BOOT_DRIVER(mcs7830_eth) = { + .name = "mcs7830_eth", + .id = UCLASS_ETH, + .probe = mcs7830_eth_probe, + .ops = &mcs7830_eth_ops, + .priv_auto_alloc_size = sizeof(struct mcs7830_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static const struct usb_device_id mcs7830_eth_id_table[] = { + { USB_DEVICE(0x9710, 0x7832) }, /* Moschip 7832 */ + { USB_DEVICE(0x9710, 0x7830), }, /* Moschip 7830 */ + { USB_DEVICE(0x9710, 0x7730), }, /* Moschip 7730 */ + { USB_DEVICE(0x0df6, 0x0021), }, /* Sitecom LN 30 */ + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(mcs7830_eth, mcs7830_eth_id_table); +#endif diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index ec1f23a0cf..1ecb92ac6b 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -444,8 +444,9 @@ static void set_bulk_out_req_length(struct fsg_common *common, /*-------------------------------------------------------------------------*/ -struct ums *ums; -struct fsg_common *the_fsg_common; +static struct ums *ums; +static int ums_count; +static struct fsg_common *the_fsg_common; static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) { @@ -772,7 +773,7 @@ static int do_read(struct fsg_common *common) } /* Perform the read */ - rc = ums->read_sector(ums, + rc = ums[common->lun].read_sector(&ums[common->lun], file_offset / SECTOR_SIZE, amount / SECTOR_SIZE, (char __user *)bh->buf); @@ -946,7 +947,7 @@ static int do_write(struct fsg_common *common) amount = bh->outreq->actual; /* Perform the write */ - rc = ums->write_sector(ums, + rc = ums[common->lun].write_sector(&ums[common->lun], file_offset / SECTOR_SIZE, amount / SECTOR_SIZE, (char __user *)bh->buf); @@ -1062,7 +1063,7 @@ static int do_verify(struct fsg_common *common) } /* Perform the read */ - rc = ums->read_sector(ums, + rc = ums[common->lun].read_sector(&ums[common->lun], file_offset / SECTOR_SIZE, amount / SECTOR_SIZE, (char __user *)bh->buf); @@ -1117,7 +1118,7 @@ static int do_inquiry(struct fsg_common *common, struct fsg_buffhd *bh) buf[4] = 31; /* Additional length */ /* No special options */ sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id , - ums->name, (u16) 0xffff); + ums[common->lun].name, (u16) 0xffff); return 36; } @@ -2456,7 +2457,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, int nluns, i, rc; /* Find out how many LUNs there should be */ - nluns = 1; + nluns = ums_count; if (nluns < 1 || nluns > FSG_MAX_LUNS) { printf("invalid number of LUNs: %u\n", nluns); return ERR_PTR(-EINVAL); @@ -2501,7 +2502,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, for (i = 0; i < nluns; i++) { common->luns[i].removable = 1; - rc = fsg_lun_open(&common->luns[i], ""); + rc = fsg_lun_open(&common->luns[i], ums[i].num_sectors, ""); if (rc) goto error_luns; } @@ -2775,9 +2776,10 @@ int fsg_add(struct usb_configuration *c) return fsg_bind_config(c->cdev, c, fsg_common); } -int fsg_init(struct ums *ums_dev) +int fsg_init(struct ums *ums_devs, int count) { - ums = ums_dev; + ums = ums_devs; + ums_count = count; return 0; } diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index b55e40bbda..b6df130a14 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -564,7 +564,8 @@ static struct usb_gadget_strings fsg_stringtab = { * the caller must own fsg->filesem for writing. */ -static int fsg_lun_open(struct fsg_lun *curlun, const char *filename) +static int fsg_lun_open(struct fsg_lun *curlun, unsigned int num_sectors, + const char *filename) { int ro; @@ -572,8 +573,8 @@ static int fsg_lun_open(struct fsg_lun *curlun, const char *filename) ro = curlun->initially_ro; curlun->ro = ro; - curlun->file_length = ums->num_sectors << 9; - curlun->num_sectors = ums->num_sectors; + curlun->file_length = num_sectors << 9; + curlun->num_sectors = num_sectors; debug("open backing file: %s\n", filename); return 0; diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 0cb9fcc166..cda1c6d5f7 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -18,32 +18,34 @@ struct ehci_pci_priv { struct ehci_ctrl ehci; }; -static void ehci_pci_common_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr, - struct ehci_hcor **ret_hcor) +#ifdef CONFIG_DM_USB + +static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, + struct ehci_hcor **ret_hcor) { struct ehci_hccr *hccr; struct ehci_hcor *hcor; - uint32_t cmd; + u32 cmd; - hccr = (struct ehci_hccr *)pci_map_bar(pdev, + hccr = (struct ehci_hccr *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - hcor = (struct ehci_hcor *)((uint32_t) hccr + + hcor = (struct ehci_hcor *)((uintptr_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", - (uint32_t)hccr, (uint32_t)hcor, - (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); *ret_hccr = hccr; *ret_hcor = hcor; /* enable busmaster */ - pci_read_config_dword(pdev, PCI_COMMAND, &cmd); + dm_pci_read_config32(dev, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_MASTER; - pci_write_config_dword(pdev, PCI_COMMAND, cmd); + dm_pci_write_config32(dev, PCI_COMMAND, cmd); } -#ifndef CONFIG_DM_USB +#else #ifdef CONFIG_PCI_EHCI_DEVICE static struct pci_device_id ehci_pci_ids[] = { @@ -55,6 +57,31 @@ static struct pci_device_id ehci_pci_ids[] = { }; #endif +static void ehci_pci_legacy_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr, + struct ehci_hcor **ret_hcor) +{ + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + u32 cmd; + + hccr = (struct ehci_hccr *)pci_map_bar(pdev, + PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + hcor = (struct ehci_hcor *)((uintptr_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + *ret_hccr = hccr; + *ret_hcor = hcor; + + /* enable busmaster */ + pci_read_config_dword(pdev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pci_write_config_dword(pdev, PCI_COMMAND, cmd); +} + /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -73,7 +100,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, printf("EHCI host controller not found\n"); return -1; } - ehci_pci_common_init(pdev, ret_hccr, ret_hcor); + ehci_pci_legacy_init(pdev, ret_hccr, ret_hcor); return 0; } @@ -94,7 +121,7 @@ static int ehci_pci_probe(struct udevice *dev) struct ehci_hccr *hccr; struct ehci_hcor *hcor; - ehci_pci_common_init(pci_get_bdf(dev), &hccr, &hcor); + ehci_pci_init(dev, &hccr, &hcor); return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); } diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c index a19651f5f3..021c1d68ed 100644 --- a/drivers/video/vesa_fb.c +++ b/drivers/video/vesa_fb.c @@ -19,8 +19,8 @@ GraphicDevice ctfb; void *video_hw_init(void) { GraphicDevice *gdev = &ctfb; + struct udevice *dev; int bits_per_pixel; - pci_dev_t dev; int ret; printf("Video: "); @@ -33,14 +33,14 @@ void *video_hw_init(void) return NULL; } if (vbe_get_video_info(gdev)) { - dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0); - if (dev < 0) { + ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev); + if (ret) { printf("no card detected\n"); return NULL; } bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); - ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE | - PCI_ROM_ALLOW_FALLBACK); + ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE | + PCI_ROM_ALLOW_FALLBACK); bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); if (ret) { printf("failed to run video BIOS: %d\n", ret); |