diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/Kconfig | 15 | ||||
| -rw-r--r-- | drivers/net/fsl_enetc.h | 5 | ||||
| -rw-r--r-- | drivers/net/mscc_eswitch/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/net/mscc_eswitch/Makefile | 1 | ||||
| -rw-r--r-- | drivers/net/mscc_eswitch/felix_switch.c | 414 | ||||
| -rw-r--r-- | drivers/net/phy/fixed.c | 3 | ||||
| -rw-r--r-- | drivers/net/phy/phy.c | 31 | ||||
| -rw-r--r-- | drivers/tee/Makefile | 2 | ||||
| -rw-r--r-- | drivers/tee/optee/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/tee/optee/Makefile | 1 | ||||
| -rw-r--r-- | drivers/tee/optee/i2c.c | 90 | ||||
| -rw-r--r-- | drivers/tee/optee/optee_msg.h | 21 | ||||
| -rw-r--r-- | drivers/tee/optee/optee_msg_supplicant.h | 5 | ||||
| -rw-r--r-- | drivers/tee/optee/optee_private.h | 17 | ||||
| -rw-r--r-- | drivers/tee/optee/supplicant.c | 3 | ||||
| -rw-r--r-- | drivers/tee/sandbox.c | 142 |
16 files changed, 762 insertions, 5 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 971a572248..0e84c22b50 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -37,6 +37,21 @@ config DM_MDIO_MUX This is currently implemented in net/mdio-mux-uclass.c Look in include/miiphy.h for details. +config DM_DSA + bool "Enable Driver Model for DSA switches" + depends on DM_ETH && DM_MDIO + depends on PHY_FIXED + help + Enable driver model for DSA switches + + Adds UCLASS_DSA class supporting switches that follow the Distributed + Switch Architecture (DSA). These switches rely on the presence of a + management switch port connected to an Ethernet controller capable of + receiving frames from the switch. This host Ethernet controller is + called the "master" Ethernet interface in DSA terminology. + This is currently implemented in net/dsa-uclass.c, refer to + include/net/dsa.h for API details. + config MDIO_SANDBOX depends on DM_MDIO && SANDBOX default y diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index 37e7e85843..110c1d78fb 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -201,6 +201,11 @@ struct enetc_priv { /* PCS replicator block for USXGMII */ #define ENETC_PCS_DEVAD_REPL 0x1f +#define ENETC_PCS_REPL_LINK_TIMER_1 0x12 +#define ENETC_PCS_REPL_LINK_TIMER_1_DEF 0x0003 +#define ENETC_PCS_REPL_LINK_TIMER_2 0x13 +#define ENETC_PCS_REPL_LINK_TIMER_2_DEF 0x06a0 + /* ENETC external MDIO registers */ #define ENETC_MDIO_BASE 0x1c00 #define ENETC_MDIO_CFG 0x00 diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 80dd22f98b..ccf7822dbe 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -36,3 +36,11 @@ config MSCC_SERVAL_SWITCH select PHYLIB help This driver supports the Serval network switch device. + +config MSCC_FELIX_SWITCH + bool "Felix switch driver" + depends on DM_DSA && DM_PCI + select FSL_ENETC + help + This driver supports the Ethernet switch integrated in the + NXP LS1028A SoC. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index d583fe9fc4..22342ed114 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o m obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o mscc_miim.o obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o mscc_miim.o obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o mscc_miim.o +obj-$(CONFIG_MSCC_FELIX_SWITCH) += felix_switch.o diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c new file mode 100644 index 0000000000..f20e84e0f1 --- /dev/null +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Felix (VSC9959) Ethernet switch driver + * Copyright 2018-2021 NXP Semiconductors + */ + +/* + * This driver is used for the Ethernet switch integrated into NXP LS1028A. + * Felix switch is derived from Microsemi Ocelot but there are several NXP + * adaptations that makes the two U-Boot drivers largely incompatible. + * + * Felix on LS1028A has 4 front panel ports and two internal ports, connected + * to ENETC interfaces. We're using one of the ENETC interfaces to push traffic + * into the switch. Injection/extraction headers are used to identify + * egress/ingress ports in the switch for Tx/Rx. + */ + +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <net/dsa.h> +#include <asm/io.h> +#include <miiphy.h> +#include <pci.h> + +/* defines especially around PCS are reused from enetc */ +#include "../fsl_enetc.h" + +#define PCI_DEVICE_ID_FELIX_ETHSW 0xEEF0 + +/* Felix has in fact 6 ports, but we don't use the last internal one */ +#define FELIX_PORT_COUNT 5 +/* Front panel port mask */ +#define FELIX_FP_PORT_MASK 0xf + +/* Register map for BAR4 */ +#define FELIX_SYS 0x010000 +#define FELIX_ES0 0x040000 +#define FELIX_IS1 0x050000 +#define FELIX_IS2 0x060000 +#define FELIX_GMII(port) (0x100000 + (port) * 0x10000) +#define FELIX_QSYS 0x200000 + +#define FELIX_SYS_SYSTEM (FELIX_SYS + 0x00000E00) +#define FELIX_SYS_SYSTEM_EN BIT(0) +#define FELIX_SYS_RAM_CTRL (FELIX_SYS + 0x00000F24) +#define FELIX_SYS_RAM_CTRL_INIT BIT(1) +#define FELIX_SYS_SYSTEM_PORT_MODE(a) (FELIX_SYS_SYSTEM + 0xC + (a) * 4) +#define FELIX_SYS_SYSTEM_PORT_MODE_CPU 0x0000001e + +#define FELIX_ES0_TCAM_CTRL (FELIX_ES0 + 0x000003C0) +#define FELIX_ES0_TCAM_CTRL_EN BIT(0) +#define FELIX_IS1_TCAM_CTRL (FELIX_IS1 + 0x000003C0) +#define FELIX_IS1_TCAM_CTRL_EN BIT(0) +#define FELIX_IS2_TCAM_CTRL (FELIX_IS2 + 0x000003C0) +#define FELIX_IS2_TCAM_CTRL_EN BIT(0) + +#define FELIX_GMII_CLOCK_CFG(port) (FELIX_GMII(port) + 0x00000000) +#define FELIX_GMII_CLOCK_CFG_LINK_1G 1 +#define FELIX_GMII_CLOCK_CFG_LINK_100M 2 +#define FELIX_GMII_CLOCK_CFG_LINK_10M 3 +#define FELIX_GMII_MAC_ENA_CFG(port) (FELIX_GMII(port) + 0x0000001C) +#define FELIX_GMII_MAX_ENA_CFG_TX BIT(0) +#define FELIX_GMII_MAX_ENA_CFG_RX BIT(4) +#define FELIX_GMII_MAC_IFG_CFG(port) (FELIX_GMII(port) + 0x0000001C + 0x14) +#define FELIX_GMII_MAC_IFG_CFG_DEF 0x515 + +#define FELIX_QSYS_SYSTEM (FELIX_QSYS + 0x0000F460) +#define FELIX_QSYS_SYSTEM_SW_PORT_MODE(a) \ + (FELIX_QSYS_SYSTEM + 0x20 + (a) * 4) +#define FELIX_QSYS_SYSTEM_SW_PORT_ENA BIT(14) +#define FELIX_QSYS_SYSTEM_SW_PORT_LOSSY BIT(9) +#define FELIX_QSYS_SYSTEM_SW_PORT_SCH(a) (((a) & 0x3800) << 11) +#define FELIX_QSYS_SYSTEM_EXT_CPU_CFG (FELIX_QSYS_SYSTEM + 0x80) +#define FELIX_QSYS_SYSTEM_EXT_CPU_PORT(a) (((a) & 0xf) << 8 | 0xff) + +/* internal MDIO in BAR0 */ +#define FELIX_PM_IMDIO_BASE 0x8030 + +/* Serdes block on LS1028A */ +#define FELIX_SERDES_BASE 0x1ea0000L +#define FELIX_SERDES_LNATECR0(lane) (FELIX_SERDES_BASE + 0x818 + \ + (lane) * 0x40) +#define FELIX_SERDES_LNATECR0_ADPT_EQ 0x00003000 +#define FELIX_SERDES_SGMIICR1(lane) (FELIX_SERDES_BASE + 0x1804 + \ + (lane) * 0x10) +#define FELIX_SERDES_SGMIICR1_SGPCS BIT(11) +#define FELIX_SERDES_SGMIICR1_MDEV(a) (((a) & 0x1f) << 27) + +#define FELIX_PCS_CTRL 0 +#define FELIX_PCS_CTRL_RST BIT(15) + +/* + * The long prefix format used here contains two dummy MAC addresses, a magic + * value in place of a VLAN tag followed by the extraction/injection header and + * the original L2 frame. Out of all this we only use the port ID. + */ +#define FELIX_DSA_TAG_LEN sizeof(struct felix_dsa_tag) +#define FELIX_DSA_TAG_MAGIC 0x0a008088 +#define FELIX_DSA_TAG_INJ_PORT 7 +#define FELIX_DSA_TAG_INJ_PORT_SET(a) (0x1 << ((a) & FELIX_FP_PORT_MASK)) +#define FELIX_DSA_TAG_EXT_PORT 10 +#define FELIX_DSA_TAG_EXT_PORT_GET(a) ((a) >> 3) + +struct felix_dsa_tag { + uchar d_mac[6]; + uchar s_mac[6]; + u32 magic; + uchar meta[16]; +}; + +struct felix_priv { + void *regs_base; + void *imdio_base; + struct mii_dev imdio; +}; + +/* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */ +static int felix_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct enetc_mdio_priv priv; + + priv.regs_base = bus->priv; + return enetc_mdio_read_priv(&priv, addr, devad, reg); +} + +static int felix_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct enetc_mdio_priv priv; + + priv.regs_base = bus->priv; + return enetc_mdio_write_priv(&priv, addr, devad, reg, val); +} + +/* set up serdes for SGMII */ +static void felix_init_sgmii(struct mii_dev *imdio, int pidx, bool an) +{ + u16 reg; + + /* set up PCS lane address */ + out_le32(FELIX_SERDES_SGMIICR1(pidx), FELIX_SERDES_SGMIICR1_SGPCS | + FELIX_SERDES_SGMIICR1_MDEV(pidx)); + + /* + * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed. + * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based + * on PLL configuration. Setting 1G for 2.5G here is counter intuitive + * but intentional. + */ + reg = ENETC_PCS_IF_MODE_SGMII; + reg |= an ? ENETC_PCS_IF_MODE_SGMII_AN : ENETC_PCS_IF_MODE_SPEED_1G; + felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE, + ENETC_PCS_IF_MODE, reg); + + /* Dev ability - SGMII */ + felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE, + ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII); + + /* Adjust link timer for SGMII */ + felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE, + ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL); + felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE, + ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL); + + reg = ENETC_PCS_CR_DEF_VAL; + reg |= an ? ENETC_PCS_CR_RESET_AN : ENETC_PCS_CR_RST; + /* restart PCS AN */ + felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE, + ENETC_PCS_CR, reg); +} + +/* set up MAC and serdes for (Q)SXGMII */ +static int felix_init_sxgmii(struct mii_dev *imdio, int pidx) +{ + int timeout = 1000; + + /* set up transit equalization control on serdes lane */ + out_le32(FELIX_SERDES_LNATECR0(1), FELIX_SERDES_LNATECR0_ADPT_EQ); + + /*reset lane */ + felix_mdio_write(imdio, pidx, MDIO_MMD_PCS, FELIX_PCS_CTRL, + FELIX_PCS_CTRL_RST); + while (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS, + FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST && + --timeout) { + mdelay(10); + } + if (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS, + FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST) + return -ETIME; + + /* Dev ability - SXGMII */ + felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL, + ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII); + + /* Restart PCS AN */ + felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL, ENETC_PCS_CR, + ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN); + felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL, + ENETC_PCS_REPL_LINK_TIMER_1, + ENETC_PCS_REPL_LINK_TIMER_1_DEF); + felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL, + ENETC_PCS_REPL_LINK_TIMER_2, + ENETC_PCS_REPL_LINK_TIMER_2_DEF); + + return 0; +} + +/* Apply protocol specific configuration to MAC, serdes as needed */ +static void felix_start_pcs(struct udevice *dev, int port, + struct phy_device *phy, struct mii_dev *imdio) +{ + bool autoneg = true; + + if (phy->phy_id == PHY_FIXED_ID || + phy->interface == PHY_INTERFACE_MODE_SGMII_2500) + autoneg = false; + + switch (phy->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_QSGMII: + felix_init_sgmii(imdio, port, autoneg); + break; + case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_USXGMII: + if (felix_init_sxgmii(imdio, port)) + dev_err(dev, "PCS reset timeout on port %d\n", port); + break; + default: + break; + } +} + +void felix_init(struct udevice *dev) +{ + struct dsa_pdata *pdata = dev_get_uclass_plat(dev); + struct felix_priv *priv = dev_get_priv(dev); + void *base = priv->regs_base; + int timeout = 100; + + /* Init core memories */ + out_le32(base + FELIX_SYS_RAM_CTRL, FELIX_SYS_RAM_CTRL_INIT); + while (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT && + --timeout) + udelay(10); + if (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT) + dev_err(dev, "Timeout waiting for switch memories\n"); + + /* Start switch core, set up ES0, IS1, IS2 */ + out_le32(base + FELIX_SYS_SYSTEM, FELIX_SYS_SYSTEM_EN); + out_le32(base + FELIX_ES0_TCAM_CTRL, FELIX_ES0_TCAM_CTRL_EN); + out_le32(base + FELIX_IS1_TCAM_CTRL, FELIX_IS1_TCAM_CTRL_EN); + out_le32(base + FELIX_IS2_TCAM_CTRL, FELIX_IS2_TCAM_CTRL_EN); + udelay(20); + + priv->imdio.read = felix_mdio_read; + priv->imdio.write = felix_mdio_write; + priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE; + strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); + + /* set up CPU port */ + out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG, + FELIX_QSYS_SYSTEM_EXT_CPU_PORT(pdata->cpu_port)); + out_le32(base + FELIX_SYS_SYSTEM_PORT_MODE(pdata->cpu_port), + FELIX_SYS_SYSTEM_PORT_MODE_CPU); +} + +/* + * Probe Felix: + * - enable the PCI function + * - map BAR 4 + * - init switch core and port registers + */ +static int felix_probe(struct udevice *dev) +{ + struct felix_priv *priv = dev_get_priv(dev); + + if (ofnode_valid(dev_ofnode(dev)) && + !ofnode_is_available(dev_ofnode(dev))) { + dev_dbg(dev, "switch disabled\n"); + return -ENODEV; + } + + priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0); + if (!priv->imdio_base) { + dev_err(dev, "failed to map BAR0\n"); + return -EINVAL; + } + + priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0); + if (!priv->regs_base) { + dev_err(dev, "failed to map BAR4\n"); + return -EINVAL; + } + + /* register internal MDIO for debug */ + if (!miiphy_get_dev_by_name(dev->name)) { + struct mii_dev *mii_bus; + + mii_bus = mdio_alloc(); + mii_bus->read = felix_mdio_read; + mii_bus->write = felix_mdio_write; + mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE; + strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN); + mdio_register(mii_bus); + } + + dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); + + dsa_set_tagging(dev, FELIX_DSA_TAG_LEN, 0); + + /* set up registers */ + felix_init(dev); + + return 0; +} + +static int felix_port_enable(struct udevice *dev, int port, + struct phy_device *phy) +{ + int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; + struct felix_priv *priv = dev_get_priv(dev); + void *base = priv->regs_base; + + /* Set up MAC registers */ + out_le32(base + FELIX_GMII_CLOCK_CFG(port), + FELIX_GMII_CLOCK_CFG_LINK_1G); + + out_le32(base + FELIX_GMII_MAC_IFG_CFG(port), + FELIX_GMII_MAC_IFG_CFG_DEF); + + out_le32(base + FELIX_GMII_MAC_ENA_CFG(port), + FELIX_GMII_MAX_ENA_CFG_TX | FELIX_GMII_MAX_ENA_CFG_RX); + + out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(port), + FELIX_QSYS_SYSTEM_SW_PORT_ENA | + FELIX_QSYS_SYSTEM_SW_PORT_LOSSY | + FELIX_QSYS_SYSTEM_SW_PORT_SCH(1)); + + felix_start_pcs(dev, port, phy, &priv->imdio); + + phy->supported &= supported; + phy->advertising &= supported; + phy_config(phy); + + phy_startup(phy); + + return 0; +} + +static void felix_port_disable(struct udevice *dev, int pidx, + struct phy_device *phy) +{ + struct felix_priv *priv = dev_get_priv(dev); + void *base = priv->regs_base; + + out_le32(base + FELIX_GMII_MAC_ENA_CFG(pidx), 0); + + out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(pidx), + FELIX_QSYS_SYSTEM_SW_PORT_LOSSY | + FELIX_QSYS_SYSTEM_SW_PORT_SCH(1)); + + /* + * we don't call phy_shutdown here to avoid waiting next time we use + * the port, but the downside is that remote side will think we're + * actively processing traffic although we are not. + */ +} + +static int felix_xmit(struct udevice *dev, int pidx, void *packet, int length) +{ + struct felix_dsa_tag *tag = packet; + + tag->magic = FELIX_DSA_TAG_MAGIC; + tag->meta[FELIX_DSA_TAG_INJ_PORT] = FELIX_DSA_TAG_INJ_PORT_SET(pidx); + + return 0; +} + +static int felix_rcv(struct udevice *dev, int *pidx, void *packet, int length) +{ + struct felix_dsa_tag *tag = packet; + + if (tag->magic != FELIX_DSA_TAG_MAGIC) + return -EINVAL; + + *pidx = FELIX_DSA_TAG_EXT_PORT_GET(tag->meta[FELIX_DSA_TAG_EXT_PORT]); + + return 0; +} + +static const struct dsa_ops felix_dsa_ops = { + .port_enable = felix_port_enable, + .port_disable = felix_port_disable, + .xmit = felix_xmit, + .rcv = felix_rcv, +}; + +U_BOOT_DRIVER(felix_ethsw) = { + .name = "felix-switch", + .id = UCLASS_DSA, + .probe = felix_probe, + .ops = &felix_dsa_ops, + .priv_auto = sizeof(struct felix_priv), +}; + +static struct pci_device_id felix_ethsw_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_FELIX_ETHSW) }, + {} +}; + +U_BOOT_PCI_DEVICE(felix_ethsw, felix_ethsw_ids); diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 3228672fc4..1a38c29469 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -24,7 +24,8 @@ int fixedphy_probe(struct phy_device *phydev) /* check for mandatory properties within fixed-link node */ val = fdt_getprop_u32_default_node(gd->fdt_blob, ofnode, 0, "speed", 0); - if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000) { + if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000 && + val != SPEED_2500 && val != SPEED_10000) { printf("ERROR: no/invalid speed given in fixed-link node!"); return -EINVAL; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index a2be398736..89e3076bfd 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -977,6 +977,37 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, #endif #ifdef CONFIG_PHY_FIXED +/** + * fixed_phy_create() - create an unconnected fixed-link pseudo-PHY device + * @node: OF node for the container of the fixed-link node + * + * Description: Creates a struct phy_device based on a fixed-link of_node + * description. Can be used without phy_connect by drivers which do not expose + * a UCLASS_ETH udevice. + */ +struct phy_device *fixed_phy_create(ofnode node) +{ + phy_interface_t interface = PHY_INTERFACE_MODE_NONE; + const char *if_str; + ofnode subnode; + + if_str = ofnode_read_string(node, "phy-mode"); + if (!if_str) { + if_str = ofnode_read_string(node, "phy-interface-type"); + } + if (if_str) { + interface = phy_get_interface_by_name(if_str); + } + + subnode = ofnode_find_subnode(node, "fixed-link"); + if (!ofnode_valid(subnode)) { + return NULL; + } + + return phy_device_create(NULL, ofnode_to_offset(subnode), PHY_FIXED_ID, + false, interface); +} + #ifdef CONFIG_DM_ETH static struct phy_device *phy_connect_fixed(struct mii_dev *bus, struct udevice *dev, diff --git a/drivers/tee/Makefile b/drivers/tee/Makefile index 5c8ffdbce8..ff844195ae 100644 --- a/drivers/tee/Makefile +++ b/drivers/tee/Makefile @@ -2,5 +2,7 @@ obj-y += tee-uclass.o obj-$(CONFIG_SANDBOX) += sandbox.o +obj-$(CONFIG_OPTEE_TA_RPC_TEST) += optee/supplicant.o +obj-$(CONFIG_OPTEE_TA_RPC_TEST) += optee/i2c.o obj-$(CONFIG_OPTEE) += optee/ obj-y += broadcom/ diff --git a/drivers/tee/optee/Kconfig b/drivers/tee/optee/Kconfig index d489834df9..65622f30b1 100644 --- a/drivers/tee/optee/Kconfig +++ b/drivers/tee/optee/Kconfig @@ -22,6 +22,15 @@ config OPTEE_TA_AVB The TA can support the "avb" subcommands "read_rb", "write"rb" and "is_unlocked". +config OPTEE_TA_RPC_TEST + bool "Support RPC TEST TA" + depends on SANDBOX_TEE + default y + help + Enables support for RPC test trusted application emulation, which + permits to test reverse RPC calls to TEE supplicant. Should + be used only in sandbox env. + endmenu endif diff --git a/drivers/tee/optee/Makefile b/drivers/tee/optee/Makefile index 928d3f8002..068c6e7aa1 100644 --- a/drivers/tee/optee/Makefile +++ b/drivers/tee/optee/Makefile @@ -2,4 +2,5 @@ obj-y += core.o obj-y += supplicant.o +obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o diff --git a/drivers/tee/optee/i2c.c b/drivers/tee/optee/i2c.c new file mode 100644 index 0000000000..ef4e10f991 --- /dev/null +++ b/drivers/tee/optee/i2c.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (c) 2020 Foundries.io Ltd + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <tee.h> +#include "optee_msg.h" +#include "optee_private.h" + +static int check_xfer_flags(struct udevice *chip, uint tee_flags) +{ + uint flags; + int ret; + + ret = i2c_get_chip_flags(chip, &flags); + if (ret) + return ret; + + if (tee_flags & OPTEE_MSG_RPC_CMD_I2C_FLAGS_TEN_BIT) { + if (!(flags & DM_I2C_CHIP_10BIT)) + return -EINVAL; + } else { + if (flags & DM_I2C_CHIP_10BIT) + return -EINVAL; + } + + return 0; +} + +void optee_suppl_cmd_i2c_transfer(struct optee_msg_arg *arg) +{ + const u8 attr[] = { + OPTEE_MSG_ATTR_TYPE_VALUE_INPUT, + OPTEE_MSG_ATTR_TYPE_VALUE_INPUT, + OPTEE_MSG_ATTR_TYPE_RMEM_INOUT, + OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT, + }; + struct udevice *chip_dev; + struct tee_shm *shm; + u8 *buf; + int ret; + + if (arg->num_params != ARRAY_SIZE(attr) || + arg->params[0].attr != attr[0] || + arg->params[1].attr != attr[1] || + arg->params[2].attr != attr[2] || + arg->params[3].attr != attr[3]) { + goto bad; + } + + shm = (struct tee_shm *)(unsigned long)arg->params[2].u.rmem.shm_ref; + buf = shm->addr; + if (!buf) + goto bad; + + if (i2c_get_chip_for_busnum((int)arg->params[0].u.value.b, + (int)arg->params[0].u.value.c, + 0, &chip_dev)) + goto bad; + + if (check_xfer_flags(chip_dev, arg->params[1].u.value.a)) + goto bad; + + switch (arg->params[0].u.value.a) { + case OPTEE_MSG_RPC_CMD_I2C_TRANSFER_RD: + ret = dm_i2c_read(chip_dev, 0, buf, + (size_t)arg->params[2].u.rmem.size); + break; + case OPTEE_MSG_RPC_CMD_I2C_TRANSFER_WR: + ret = dm_i2c_write(chip_dev, 0, buf, + (size_t)arg->params[2].u.rmem.size); + break; + default: + goto bad; + } + + if (ret) { + arg->ret = TEE_ERROR_COMMUNICATION; + } else { + arg->params[3].u.value.a = arg->params[2].u.rmem.size; + arg->ret = TEE_SUCCESS; + } + + return; +bad: + arg->ret = TEE_ERROR_BAD_PARAMETERS; +} diff --git a/drivers/tee/optee/optee_msg.h b/drivers/tee/optee/optee_msg.h index 24c60960fc..8d40ce60c2 100644 --- a/drivers/tee/optee/optee_msg.h +++ b/drivers/tee/optee/optee_msg.h @@ -422,4 +422,25 @@ struct optee_msg_arg { */ #define OPTEE_MSG_RPC_CMD_SHM_FREE 7 +/* + * Access a device on an i2c bus + * + * [in] param[0].u.value.a mode: RD(0), WR(1) + * [in] param[0].u.value.b i2c adapter + * [in] param[0].u.value.c i2c chip + * + * [in] param[1].u.value.a i2c control flags + * + * [in/out] memref[2] buffer to exchange the transfer data + * with the secure world + * + * [out] param[3].u.value.a bytes transferred by the driver + */ +#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER 21 +/* I2C master transfer modes */ +#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER_RD 0 +#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER_WR 1 +/* I2C master control flags */ +#define OPTEE_MSG_RPC_CMD_I2C_FLAGS_TEN_BIT BIT(0) + #endif /* _OPTEE_MSG_H */ diff --git a/drivers/tee/optee/optee_msg_supplicant.h b/drivers/tee/optee/optee_msg_supplicant.h index a0fb8063c8..963cfd4782 100644 --- a/drivers/tee/optee/optee_msg_supplicant.h +++ b/drivers/tee/optee/optee_msg_supplicant.h @@ -148,6 +148,11 @@ #define OPTEE_MSG_RPC_CMD_SHM_FREE 7 /* + * I2C bus access + */ +#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER 21 + +/* * Was OPTEE_MSG_RPC_CMD_SQL_FS, which isn't supported any longer */ #define OPTEE_MSG_RPC_CMD_SQL_FS_RESERVED 8 diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index 9442d1c176..1f07a27ee4 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -60,6 +60,23 @@ static inline void optee_suppl_rpmb_release(struct udevice *dev) } #endif +#ifdef CONFIG_DM_I2C +/** + * optee_suppl_cmd_i2c_transfer() - route I2C requests to an I2C chip + * @arg: OP-TEE message (layout specified in optee_msg.h) defining the + * transfer mode (read/write), adapter, chip and control flags. + * + * Handles OP-TEE requests to transfer data to the I2C chip on the I2C adapter. + */ +void optee_suppl_cmd_i2c_transfer(struct optee_msg_arg *arg); +#else +static inline void optee_suppl_cmd_i2c_transfer(struct optee_msg_arg *arg) +{ + debug("OPTEE_MSG_RPC_CMD_I2C_TRANSFER not implemented\n"); + arg->ret = TEE_ERROR_NOT_IMPLEMENTED; +} +#endif + void *optee_alloc_and_init_page_list(void *buf, ulong len, u64 *phys_buf_ptr); #endif /* __OPTEE_PRIVATE_H */ diff --git a/drivers/tee/optee/supplicant.c b/drivers/tee/optee/supplicant.c index ae042b9a20..f9dd874b59 100644 --- a/drivers/tee/optee/supplicant.c +++ b/drivers/tee/optee/supplicant.c @@ -89,6 +89,9 @@ void optee_suppl_cmd(struct udevice *dev, struct tee_shm *shm_arg, case OPTEE_MSG_RPC_CMD_RPMB: optee_suppl_cmd_rpmb(dev, arg); break; + case OPTEE_MSG_RPC_CMD_I2C_TRANSFER: + optee_suppl_cmd_i2c_transfer(arg); + break; default: arg->ret = TEE_ERROR_NOT_IMPLEMENTED; } diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c index e1ba027fd6..3a1d34d6fc 100644 --- a/drivers/tee/sandbox.c +++ b/drivers/tee/sandbox.c @@ -7,11 +7,15 @@ #include <sandboxtee.h> #include <tee.h> #include <tee/optee_ta_avb.h> +#include <tee/optee_ta_rpc_test.h> + +#include "optee/optee_msg.h" +#include "optee/optee_private.h" /* * The sandbox tee driver tries to emulate a generic Trusted Exectution - * Environment (TEE) with the Trusted Application (TA) OPTEE_TA_AVB - * available. + * Environment (TEE) with the Trusted Applications (TA) OPTEE_TA_AVB and + * OPTEE_TA_RPC_TEST available. */ static const u32 pstorage_max = 16; @@ -32,7 +36,38 @@ struct ta_entry { struct tee_param *params); }; -#ifdef CONFIG_OPTEE_TA_AVB +static int get_msg_arg(struct udevice *dev, uint num_params, + struct tee_shm **shmp, struct optee_msg_arg **msg_arg) +{ + int rc; + struct optee_msg_arg *ma; + + rc = __tee_shm_add(dev, OPTEE_MSG_NONCONTIG_PAGE_SIZE, NULL, + OPTEE_MSG_GET_ARG_SIZE(num_params), TEE_SHM_ALLOC, + shmp); + if (rc) + return rc; + + ma = (*shmp)->addr; + memset(ma, 0, OPTEE_MSG_GET_ARG_SIZE(num_params)); + ma->num_params = num_params; + *msg_arg = ma; + + return 0; +} + +void *optee_alloc_and_init_page_list(void *buf, ulong len, + u64 *phys_buf_ptr) +{ + /* + * An empty stub is added just to fix linking issues. + * This function isn't supposed to be called in sandbox + * setup, otherwise replace this with a proper + * implementation from optee/core.c + */ + return NULL; +} + static u32 get_attr(uint n, uint num_params, struct tee_param *params) { if (n >= num_params) @@ -63,6 +98,7 @@ bad_params: return TEE_ERROR_BAD_PARAMETERS; } +#ifdef CONFIG_OPTEE_TA_AVB static u32 ta_avb_open_session(struct udevice *dev, uint num_params, struct tee_param *params) { @@ -214,7 +250,99 @@ static u32 ta_avb_invoke_func(struct udevice *dev, u32 func, uint num_params, return TEE_ERROR_NOT_SUPPORTED; } } -#endif /*OPTEE_TA_AVB*/ +#endif /* OPTEE_TA_AVB */ + +#ifdef CONFIG_OPTEE_TA_RPC_TEST +static u32 ta_rpc_test_open_session(struct udevice *dev, uint num_params, + struct tee_param *params) +{ + /* + * We don't expect additional parameters when opening a session to + * this TA. + */ + return check_params(TEE_PARAM_ATTR_TYPE_NONE, TEE_PARAM_ATTR_TYPE_NONE, + TEE_PARAM_ATTR_TYPE_NONE, TEE_PARAM_ATTR_TYPE_NONE, + num_params, params); +} + +static void fill_i2c_rpc_params(struct optee_msg_arg *msg_arg, u64 bus_num, + u64 chip_addr, u64 xfer_flags, u64 op, + struct tee_param_memref memref) +{ + msg_arg->params[0].attr = OPTEE_MSG_ATTR_TYPE_VALUE_INPUT; + msg_arg->params[1].attr = OPTEE_MSG_ATTR_TYPE_VALUE_INPUT; + msg_arg->params[2].attr = OPTEE_MSG_ATTR_TYPE_RMEM_INOUT; + msg_arg->params[3].attr = OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT; + + /* trigger I2C services of TEE supplicant */ + msg_arg->cmd = OPTEE_MSG_RPC_CMD_I2C_TRANSFER; + + msg_arg->params[0].u.value.a = op; + msg_arg->params[0].u.value.b = bus_num; + msg_arg->params[0].u.value.c = chip_addr; + msg_arg->params[1].u.value.a = xfer_flags; + + /* buffer to read/write data */ + msg_arg->params[2].u.rmem.shm_ref = (ulong)memref.shm; + msg_arg->params[2].u.rmem.size = memref.size; + msg_arg->params[2].u.rmem.offs = memref.shm_offs; + + msg_arg->num_params = 4; +} + +static u32 ta_rpc_test_invoke_func(struct udevice *dev, u32 func, + uint num_params, + struct tee_param *params) +{ + struct tee_shm *shm; + struct tee_param_memref memref_data; + struct optee_msg_arg *msg_arg; + int chip_addr, bus_num, op, xfer_flags; + int res; + + res = check_params(TEE_PARAM_ATTR_TYPE_VALUE_INPUT, + TEE_PARAM_ATTR_TYPE_MEMREF_INOUT, + TEE_PARAM_ATTR_TYPE_NONE, + TEE_PARAM_ATTR_TYPE_NONE, + num_params, params); + if (res) + return TEE_ERROR_BAD_PARAMETERS; + + bus_num = params[0].u.value.a; + chip_addr = params[0].u.value.b; + xfer_flags = params[0].u.value.c; + memref_data = params[1].u.memref; + + switch (func) { + case TA_RPC_TEST_CMD_I2C_READ: + op = OPTEE_MSG_RPC_CMD_I2C_TRANSFER_RD; + break; + case TA_RPC_TEST_CMD_I2C_WRITE: + op = OPTEE_MSG_RPC_CMD_I2C_TRANSFER_WR; + break; + default: + return TEE_ERROR_NOT_SUPPORTED; + } + + /* + * Fill params for an RPC call to tee supplicant + */ + res = get_msg_arg(dev, 4, &shm, &msg_arg); + if (res) + goto out; + + fill_i2c_rpc_params(msg_arg, bus_num, chip_addr, xfer_flags, op, + memref_data); + + /* Make an RPC call to tee supplicant */ + optee_suppl_cmd(dev, shm, 0); + res = msg_arg->ret; +out: + tee_shm_free(shm); + + return res; +} +#endif /* CONFIG_OPTEE_TA_RPC_TEST */ static const struct ta_entry ta_entries[] = { #ifdef CONFIG_OPTEE_TA_AVB @@ -223,6 +351,12 @@ static const struct ta_entry ta_entries[] = { .invoke_func = ta_avb_invoke_func, }, #endif +#ifdef CONFIG_OPTEE_TA_RPC_TEST + { .uuid = TA_RPC_TEST_UUID, + .open_session = ta_rpc_test_open_session, + .invoke_func = ta_rpc_test_invoke_func, + }, +#endif }; static void sandbox_tee_get_version(struct udevice *dev, |