aboutsummaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ata/mtk_ahci.c1
-rw-r--r--drivers/clk/clk_zynqmp.c251
-rw-r--r--drivers/mmc/mtk-sd.c3
-rw-r--r--drivers/mtd/nand/raw/fsl_ifc_nand.c17
-rw-r--r--drivers/net/zynq_gem.c25
-rw-r--r--drivers/nvme/nvme.c41
-rw-r--r--drivers/pci/pcie_layerscape_ep.c2
-rw-r--r--drivers/pci/pcie_layerscape_rc.c2
-rw-r--r--drivers/pinctrl/pinctrl-at91-pio4.c26
-rw-r--r--drivers/rtc/ds1307.c2
-rw-r--r--drivers/spi/xilinx_spi.c8
11 files changed, 262 insertions, 116 deletions
diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c
index 554175bc00..2c5227df30 100644
--- a/drivers/ata/mtk_ahci.c
+++ b/drivers/ata/mtk_ahci.c
@@ -21,6 +21,7 @@
#include <sata.h>
#include <scsi.h>
#include <syscon.h>
+#include <dm/device_compat.h>
#define SYS_CFG 0x14
#define SYS_CFG_SATA_MSK GENMASK(31, 30)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 609d8e3b2f..13a623fdb9 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -97,8 +97,7 @@ static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
#define CLK_CTRL_DIV0_SHIFT 8
#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
-#define CLK_CTRL_SRCSEL_SHIFT 0
-#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
+#define CLK_CTRL_SRCSEL_MASK 0x7
#define PLLCTRL_FBDIV_MASK 0x7f00
#define PLLCTRL_FBDIV_SHIFT 8
#define PLLCTRL_RESET_MASK 1
@@ -132,7 +131,7 @@ enum zynqmp_clk {
iou_switch,
gem_tsu_ref, gem_tsu,
gem0_ref, gem1_ref, gem2_ref, gem3_ref,
- gem0_rx, gem1_rx, gem2_rx, gem3_rx,
+ gem0_tx, gem1_tx, gem2_tx, gem3_tx,
qspi_ref,
sdio0_ref, sdio1_ref,
uart0_ref, uart1_ref,
@@ -152,7 +151,7 @@ static const char * const clk_names[clk_max] = {
"iopll", "rpll", "apll", "dpll",
"vpll", "iopll_to_fpd", "rpll_to_fpd",
"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
- "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
+ "acpu", "acpu_half", "dbg_fpd", "dbg_lpd",
"dbg_trace", "dbg_tstmp", "dp_video_ref",
"dp_audio_ref", "dp_stc_ref", "gdma_ref",
"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
@@ -172,6 +171,38 @@ static const char * const clk_names[clk_max] = {
"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
};
+static const u32 pll_src[][4] = {
+ {apll, 0xff, dpll, vpll}, /* acpu */
+ {dpll, vpll, 0xff, 0xff}, /* ddr_ref */
+ {rpll, iopll, 0xff, 0xff}, /* dll_ref */
+ {iopll, 0xff, rpll, dpll_to_lpd}, /* gem_tsu_ref */
+ {iopll, 0xff, rpll, dpll}, /* peripheral */
+ {apll, 0xff, iopll_to_fpd, dpll}, /* wdt */
+ {iopll_to_fpd, 0xff, dpll, apll}, /* dbg_fpd */
+ {iopll, 0xff, rpll, dpll_to_lpd}, /* timestamp_ref */
+ {iopll_to_fpd, 0xff, apll, dpll}, /* sata_ref */
+ {iopll_to_fpd, 0xff, rpll_to_fpd, dpll},/* pcie_ref */
+ {iopll_to_fpd, 0xff, vpll, dpll}, /* gpu_ref */
+ {apll, 0xff, vpll, dpll}, /* topsw_main_ref */
+ {rpll, 0xff, iopll, dpll_to_lpd}, /* cpu_r5_ref */
+};
+
+enum zynqmp_clk_pll_src {
+ ACPU_CLK_SRC = 0,
+ DDR_CLK_SRC,
+ DLL_CLK_SRC,
+ GEM_TSU_CLK_SRC,
+ PERI_CLK_SRC,
+ WDT_CLK_SRC,
+ DBG_FPD_CLK_SRC,
+ TIMESTAMP_CLK_SRC,
+ SATA_CLK_SRC,
+ PCIE_CLK_SRC,
+ GPU_CLK_SRC,
+ TOPSW_MAIN_CLK_SRC,
+ CPU_R5_CLK_SRC
+};
+
struct zynqmp_clk_priv {
unsigned long ps_clk_freq;
unsigned long video_clk;
@@ -195,12 +226,38 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRF_APB_VPLL_CTRL;
case acpu:
return CRF_APB_ACPU_CTRL;
+ case dbg_fpd:
+ return CRF_APB_DBG_FPD_CTRL;
+ case dbg_trace:
+ return CRF_APB_DBG_TRACE_CTRL;
+ case dbg_tstmp:
+ return CRF_APB_DBG_TSTMP_CTRL;
+ case gpu_ref ... gpu_pp1_ref:
+ return CRF_APB_GPU_REF_CTRL;
case ddr_ref:
return CRF_APB_DDR_CTRL;
+ case sata_ref:
+ return CRF_APB_SATA_REF_CTRL;
+ case pcie_ref:
+ return CRF_APB_PCIE_REF_CTRL;
+ case gdma_ref:
+ return CRF_APB_GDMA_REF_CTRL;
+ case dpdma_ref:
+ return CRF_APB_DPDMA_REF_CTRL;
+ case topsw_main:
+ return CRF_APB_TOPSW_MAIN_CTRL;
+ case topsw_lsbus:
+ return CRF_APB_TOPSW_LSBUS_CTRL;
+ case lpd_switch:
+ return CRL_APB_LPD_SWITCH_CTRL;
+ case lpd_lsbus:
+ return CRL_APB_LPD_LSBUS_CTRL;
case qspi_ref:
return CRL_APB_QSPI_REF_CTRL;
case usb3_dual_ref:
return CRL_APB_USB3_DUAL_REF_CTRL;
+ case gem_tsu_ref:
+ return CRL_APB_GEM_TSU_REF_CTRL;
case gem0_ref:
return CRL_APB_GEM0_REF_CTRL;
case gem1_ref:
@@ -213,6 +270,8 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRL_APB_USB0_BUS_REF_CTRL;
case usb1_bus_ref:
return CRL_APB_USB1_BUS_REF_CTRL;
+ case cpu_r5:
+ return CRL_APB_CPU_R5_CTRL;
case uart0_ref:
return CRL_APB_UART0_REF_CTRL;
case uart1_ref:
@@ -235,6 +294,14 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRL_APB_CAN0_REF_CTRL;
case can1_ref:
return CRL_APB_CAN1_REF_CTRL;
+ case dll_ref:
+ return CRL_APB_DLL_REF_CTRL;
+ case adma_ref:
+ return CRL_APB_ADMA_REF_CTRL;
+ case timestamp_ref:
+ return CRL_APB_TIMESTAMP_REF_CTRL;
+ case ams_ref:
+ return CRL_APB_AMS_REF_CTRL;
case pl0:
return CRL_APB_PL0_REF_CTRL;
case pl1:
@@ -253,68 +320,6 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return 0;
}
-static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
-{
- u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
- CLK_CTRL_SRCSEL_SHIFT;
-
- switch (srcsel) {
- case 2:
- return dpll;
- case 3:
- return vpll;
- case 0 ... 1:
- default:
- return apll;
- }
-}
-
-static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
-{
- u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
- CLK_CTRL_SRCSEL_SHIFT;
-
- switch (srcsel) {
- case 1:
- return vpll;
- case 0:
- default:
- return dpll;
- }
-}
-
-static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
-{
- u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
- CLK_CTRL_SRCSEL_SHIFT;
-
- switch (srcsel) {
- case 2:
- return rpll;
- case 3:
- return dpll;
- case 0 ... 1:
- default:
- return iopll;
- }
-}
-
-static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
-{
- u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
- CLK_CTRL_SRCSEL_SHIFT;
-
- switch (srcsel) {
- case 2:
- return iopll_to_fpd;
- case 3:
- return dpll;
- case 0 ... 1:
- default:
- return apll;
- }
-}
-
static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
struct zynqmp_clk_priv *priv,
bool is_pre_src)
@@ -378,7 +383,7 @@ static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
enum zynqmp_clk id)
{
- u32 clk_ctrl, div;
+ u32 clk_ctrl, div, srcsel;
enum zynqmp_clk pll;
int ret;
unsigned long pllrate;
@@ -391,7 +396,8 @@ static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
- pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
+ srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
+ pll = pll_src[ACPU_CLK_SRC][srcsel];
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pllrate))
return pllrate;
@@ -401,7 +407,7 @@ static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
{
- u32 clk_ctrl, div;
+ u32 clk_ctrl, div, srcsel;
enum zynqmp_clk pll;
int ret;
ulong pllrate;
@@ -414,7 +420,8 @@ static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
- pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
+ srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
+ pll = pll_src[DDR_CLK_SRC][srcsel];
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pllrate))
return pllrate;
@@ -422,11 +429,33 @@ static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
return DIV_ROUND_CLOSEST(pllrate, div);
}
+static ulong zynqmp_clk_get_dll_rate(struct zynqmp_clk_priv *priv)
+{
+ u32 clk_ctrl, srcsel;
+ enum zynqmp_clk pll;
+ ulong pllrate;
+ int ret;
+
+ ret = zynqmp_mmio_read(CRL_APB_DLL_REF_CTRL, &clk_ctrl);
+ if (ret) {
+ printf("%s mio read fail\n", __func__);
+ return -EIO;
+ }
+
+ srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
+ pll = pll_src[DLL_CLK_SRC][srcsel];
+ pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+ if (IS_ERR_VALUE(pllrate))
+ return pllrate;
+
+ return pllrate;
+}
+
static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
- enum zynqmp_clk id, bool two_divs)
+ enum zynqmp_clk id, bool two_divs)
{
enum zynqmp_clk pll;
- u32 clk_ctrl, div0;
+ u32 clk_ctrl, div0, srcsel;
u32 div1 = 1;
int ret;
ulong pllrate;
@@ -446,8 +475,13 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
if (!div1)
div1 = 1;
}
+ srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
+
+ if (id == gem_tsu_ref)
+ pll = pll_src[GEM_TSU_CLK_SRC][srcsel];
+ else
+ pll = pll_src[PERI_CLK_SRC][srcsel];
- pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pllrate))
return pllrate;
@@ -457,11 +491,11 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
DIV_ROUND_CLOSEST(pllrate, div0), div1);
}
-static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
- enum zynqmp_clk id, bool two_divs)
+static ulong zynqmp_clk_get_crf_crl_rate(struct zynqmp_clk_priv *priv,
+ enum zynqmp_clk id, bool two_divs)
{
enum zynqmp_clk pll;
- u32 clk_ctrl, div0;
+ u32 clk_ctrl, div0, srcsel;
u32 div1 = 1;
int ret;
ulong pllrate;
@@ -475,8 +509,45 @@ static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
if (!div0)
div0 = 1;
+ srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
- pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
+ switch (id) {
+ case wdt:
+ case dbg_trace:
+ case topsw_lsbus:
+ pll = pll_src[WDT_CLK_SRC][srcsel];
+ break;
+ case dbg_fpd:
+ case dbg_tstmp:
+ pll = pll_src[DBG_FPD_CLK_SRC][srcsel];
+ break;
+ case timestamp_ref:
+ pll = pll_src[TIMESTAMP_CLK_SRC][srcsel];
+ break;
+ case sata_ref:
+ pll = pll_src[SATA_CLK_SRC][srcsel];
+ break;
+ case pcie_ref:
+ pll = pll_src[PCIE_CLK_SRC][srcsel];
+ break;
+ case gpu_ref ... gpu_pp1_ref:
+ pll = pll_src[GPU_CLK_SRC][srcsel];
+ break;
+ case gdma_ref:
+ case dpdma_ref:
+ case topsw_main:
+ pll = pll_src[TOPSW_MAIN_CLK_SRC][srcsel];
+ break;
+ case cpu_r5:
+ case ams_ref:
+ case adma_ref:
+ case lpd_lsbus:
+ case lpd_switch:
+ pll = pll_src[CPU_R5_CLK_SRC][srcsel];
+ break;
+ default:
+ return -ENXIO;
+ }
if (two_divs) {
ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
if (ret) {
@@ -533,7 +604,7 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
enum zynqmp_clk pll;
u32 clk_ctrl, div0 = 0, div1 = 0;
ulong pll_rate, new_rate;
- u32 reg;
+ u32 reg, srcsel;
int ret;
u32 mask;
@@ -544,7 +615,8 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
return -EIO;
}
- pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
+ srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
+ pll = pll_src[PERI_CLK_SRC][srcsel];
pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pll_rate))
return pll_rate;
@@ -588,14 +660,31 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
return zynqmp_clk_get_cpu_rate(priv, id);
case ddr_ref:
return zynqmp_clk_get_ddr_rate(priv);
+ case dll_ref:
+ return zynqmp_clk_get_dll_rate(priv);
+ case gem_tsu_ref:
+ case pl0 ... pl3:
case gem0_ref ... gem3_ref:
case qspi_ref ... can1_ref:
- case pl0 ... pl3:
+ case usb0_bus_ref ... usb3_dual_ref:
two_divs = true;
return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
case wdt:
+ case topsw_lsbus:
+ case sata_ref ... gpu_pp1_ref:
two_divs = true;
- return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
+ case cpu_r5:
+ case dbg_fpd:
+ case ams_ref:
+ case adma_ref:
+ case lpd_lsbus:
+ case dbg_trace:
+ case dbg_tstmp:
+ case lpd_switch:
+ case topsw_main:
+ case timestamp_ref:
+ case gdma_ref ... dpdma_ref:
+ return zynqmp_clk_get_crf_crl_rate(priv, id, two_divs);
default:
return -ENXIO;
}
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 3b9c12266a..48a764be82 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -1639,7 +1639,8 @@ static int msdc_drv_probe(struct udevice *dev)
else
cfg->f_min = host->src_clk_freq / (4 * 4095);
- cfg->f_max = host->src_clk_freq;
+ if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq)
+ cfg->f_max = host->src_clk_freq;
cfg->b_max = 1024;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index cf20238782..e5ff937872 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -411,9 +411,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
/* READID must read all possible bytes while CEB is active */
case NAND_CMD_READID:
case NAND_CMD_PARAM: {
+ /*
+ * For READID, read 8 bytes that are currently used.
+ * For PARAM, read all 3 copies of 256-bytes pages.
+ */
+ int len = 8;
int timing = IFC_FIR_OP_RB;
- if (command == NAND_CMD_PARAM)
+ if (command == NAND_CMD_PARAM) {
timing = IFC_FIR_OP_RBCD;
+ len = 256 * 3;
+ }
ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
@@ -423,12 +430,8 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
command << IFC_NAND_FCR0_CMD0_SHIFT);
ifc_out32(&ifc->ifc_nand.row3, column);
- /*
- * although currently it's 8 bytes for READID, we always read
- * the maximum 256 bytes(for PARAM)
- */
- ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
- ctrl->read_bytes = 256;
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, len);
+ ctrl->read_bytes = len;
set_addr(mtd, 0, 0, 0);
fsl_ifc_run_command(mtd);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index baf06a2ad8..ff59982267 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -454,14 +454,6 @@ static int zynq_gem_init(struct udevice *dev)
priv->int_pcs) {
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
-#ifdef CONFIG_ARM64
- if (priv->phydev->phy_id != PHY_FIXED_ID)
- writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
- &regs->pcscntrl);
- else
- writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
- &regs->pcscntrl);
-#endif
}
switch (priv->phydev->speed) {
@@ -480,6 +472,23 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
+#ifdef CONFIG_ARM64
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
+ priv->int_pcs) {
+ /*
+ * Disable AN for fixed link configuration, enable otherwise.
+ * Must be written after PCS_SEL is set in nwconfig,
+ * otherwise writes will not take effect.
+ */
+ if (priv->phydev->phy_id != PHY_FIXED_ID)
+ writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ &regs->pcscntrl);
+ else
+ writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ &regs->pcscntrl);
+ }
+#endif
+
ret = clk_set_rate(&priv->tx_clk, clk_rate);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate\n");
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 5d6331ad34..c61dab20c5 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -22,6 +22,8 @@
#define NVME_AQ_DEPTH 2
#define NVME_SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
#define NVME_CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
+#define NVME_CQ_ALLOCATION ALIGN(NVME_CQ_SIZE(NVME_Q_DEPTH), \
+ ARCH_DMA_MINALIGN)
#define ADMIN_TIMEOUT 60
#define IO_TIMEOUT 30
#define MAX_PRP_POOL 512
@@ -144,8 +146,14 @@ static __le16 nvme_get_cmd_id(void)
static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index)
{
- u64 start = (ulong)&nvmeq->cqes[index];
- u64 stop = start + sizeof(struct nvme_completion);
+ /*
+ * Single CQ entries are always smaller than a cache line, so we
+ * can't invalidate them individually. However CQ entries are
+ * read only by the CPU, so it's safe to always invalidate all of them,
+ * as the cache line should never become dirty.
+ */
+ ulong start = (ulong)&nvmeq->cqes[0];
+ ulong stop = start + NVME_CQ_ALLOCATION;
invalidate_dcache_range(start, stop);
@@ -241,7 +249,7 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev,
return NULL;
memset(nvmeq, 0, sizeof(*nvmeq));
- nvmeq->cqes = (void *)memalign(4096, NVME_CQ_SIZE(depth));
+ nvmeq->cqes = (void *)memalign(4096, NVME_CQ_ALLOCATION);
if (!nvmeq->cqes)
goto free_nvmeq;
memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth));
@@ -339,7 +347,7 @@ static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(nvmeq->q_depth));
flush_dcache_range((ulong)nvmeq->cqes,
- (ulong)nvmeq->cqes + NVME_CQ_SIZE(nvmeq->q_depth));
+ (ulong)nvmeq->cqes + NVME_CQ_ALLOCATION);
dev->online_queues++;
}
@@ -481,6 +489,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
dma_addr_t dma_addr, u32 *result)
{
struct nvme_command c;
+ int ret;
memset(&c, 0, sizeof(c));
c.features.opcode = nvme_admin_get_features;
@@ -488,12 +497,20 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
c.features.prp1 = cpu_to_le64(dma_addr);
c.features.fid = cpu_to_le32(fid);
+ ret = nvme_submit_admin_cmd(dev, &c, result);
+
/*
- * TODO: add cache invalidate operation when the size of
- * the DMA buffer is known
+ * TODO: Add some cache invalidation when a DMA buffer is involved
+ * in the request, here and before the command gets submitted. The
+ * buffer size varies by feature, also some features use a different
+ * field in the command packet to hold the buffer address.
+ * Section 5.21.1 (Set Features command) in the NVMe specification
+ * details the buffer requirements for each feature.
+ *
+ * At the moment there is no user of this function.
*/
- return nvme_submit_admin_cmd(dev, &c, result);
+ return ret;
}
int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
@@ -508,8 +525,14 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
c.features.dword11 = cpu_to_le32(dword11);
/*
- * TODO: add cache flush operation when the size of
- * the DMA buffer is known
+ * TODO: Add a cache clean (aka flush) operation when a DMA buffer is
+ * involved in the request. The buffer size varies by feature, also
+ * some features use a different field in the command packet to hold
+ * the buffer address. Section 5.21.1 (Set Features command) in the
+ * NVMe specification details the buffer requirements for each
+ * feature.
+ * At the moment the only user of this function is not using
+ * any DMA buffer at all.
*/
return nvme_submit_admin_cmd(dev, &c, result);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 14983cce4f..c7231635e4 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -244,7 +244,7 @@ static int ls_pcie_ep_probe(struct udevice *dev)
int ret;
u32 svr;
- pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index b055ed5165..bd2c19f7f0 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -254,7 +254,7 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->bus = dev;
- pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index b7ae2f6ada..26fb5d61d5 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct atmel_pio4_plat {
struct atmel_pio4_port *reg_base;
+ unsigned int slew_rate_support;
};
static const struct pinconf_param conf_params[] = {
@@ -36,9 +37,11 @@ static const struct pinconf_param conf_params[] = {
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
{ "atmel,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+ { "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
};
-static u32 atmel_pinctrl_get_pinconf(struct udevice *config)
+static u32 atmel_pinctrl_get_pinconf(struct udevice *config,
+ struct atmel_pio4_plat *plat)
{
const struct pinconf_param *params;
u32 param, arg, conf = 0;
@@ -53,6 +56,10 @@ static u32 atmel_pinctrl_get_pinconf(struct udevice *config)
param = params->param;
arg = params->default_value;
+ /* Keep slew rate enabled by default. */
+ if (plat->slew_rate_support)
+ conf |= ATMEL_PIO_SR;
+
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
conf &= (~ATMEL_PIO_PUEN_MASK);
@@ -91,6 +98,15 @@ static u32 atmel_pinctrl_get_pinconf(struct udevice *config)
conf |= (val << ATMEL_PIO_DRVSTR_OFFSET)
& ATMEL_PIO_DRVSTR_MASK;
break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (!plat->slew_rate_support)
+ break;
+
+ dev_read_u32(config, params->property, &val);
+ /* And disable it if requested. */
+ if (val == 0)
+ conf &= ~ATMEL_PIO_SR;
+ break;
default:
printf("%s: Unsupported configuration parameter: %u\n",
__func__, param);
@@ -116,6 +132,7 @@ static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
struct atmel_pio4_port *bank_base;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(config);
@@ -124,7 +141,7 @@ static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
u32 i, conf;
int count;
- conf = atmel_pinctrl_get_pinconf(config);
+ conf = atmel_pinctrl_get_pinconf(config, plat);
count = fdtdec_get_int_array_count(blob, node, "pinmux",
cells, ARRAY_SIZE(cells));
@@ -164,6 +181,7 @@ const struct pinctrl_ops atmel_pinctrl_ops = {
static int atmel_pinctrl_probe(struct udevice *dev)
{
struct atmel_pio4_plat *plat = dev_get_plat(dev);
+ ulong priv = dev_get_driver_data(dev);
fdt_addr_t addr_base;
dev = dev_get_parent(dev);
@@ -172,13 +190,15 @@ static int atmel_pinctrl_probe(struct udevice *dev)
return -EINVAL;
plat->reg_base = (struct atmel_pio4_port *)addr_base;
+ plat->slew_rate_support = priv;
return 0;
}
static const struct udevice_id atmel_pinctrl_match[] = {
{ .compatible = "atmel,sama5d2-pinctrl" },
- { .compatible = "microchip,sama7g5-pinctrl" },
+ { .compatible = "microchip,sama7g5-pinctrl",
+ .data = (ulong)1, },
{}
};
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 17344d4d4f..2015ce9bbc 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -23,6 +23,7 @@
enum ds_type {
ds_1307,
ds_1337,
+ ds_1339,
ds_1340,
m41t11,
mcp794xx,
@@ -344,6 +345,7 @@ static const struct rtc_ops ds1307_rtc_ops = {
static const struct udevice_id ds1307_rtc_ids[] = {
{ .compatible = "dallas,ds1307", .data = ds_1307 },
{ .compatible = "dallas,ds1337", .data = ds_1337 },
+ { .compatible = "dallas,ds1339", .data = ds_1339 },
{ .compatible = "dallas,ds1340", .data = ds_1340 },
{ .compatible = "microchip,mcp7941x", .data = mcp794xx },
{ .compatible = "st,m41t11", .data = m41t11 },
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 0274afdc6e..b892cdae9b 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -314,8 +314,7 @@ static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
priv->freq = speed;
- debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
- priv->freq);
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
return 0;
}
@@ -324,7 +323,7 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
- uint32_t spicr;
+ u32 spicr;
spicr = readl(&regs->spicr);
if (mode & SPI_LSB_FIRST)
@@ -339,8 +338,7 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
writel(spicr, &regs->spicr);
priv->mode = mode;
- debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
- priv->mode);
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
return 0;
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 00:05:59 +0000