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-rw-r--r--drivers/clk/Kconfig1
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/tegra/Kconfig6
-rw-r--r--drivers/clk/tegra/Makefile5
-rw-r--r--drivers/clk/tegra/tegra186-clk.c104
-rw-r--r--drivers/i2c/Kconfig10
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/tegra186_bpmp_i2c.c129
-rw-r--r--drivers/i2c/tegra_i2c.c89
-rw-r--r--drivers/misc/Kconfig12
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/tegra186_bpmp.c257
-rw-r--r--drivers/mmc/tegra_mmc.c64
-rw-r--r--drivers/pci/Kconfig1
-rw-r--r--drivers/pci/pci_tegra.c163
-rw-r--r--drivers/power/domain/Kconfig7
-rw-r--r--drivers/power/domain/Makefile1
-rw-r--r--drivers/power/domain/tegra186-power-domain.c92
-rw-r--r--drivers/reset/Kconfig7
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/tegra186-reset.c81
21 files changed, 1016 insertions, 18 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 6eee8eb369..7dd56738b0 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,6 +20,7 @@ config SPL_CLK
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
+source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3cbdd54f4f..463b1d647d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,5 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+
+obj-y += tegra/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
new file mode 100644
index 0000000000..659fe022c2
--- /dev/null
+++ b/drivers/clk/tegra/Kconfig
@@ -0,0 +1,6 @@
+config TEGRA186_CLOCK
+ bool "Enable Tegra186 BPMP-based clock driver"
+ depends on TEGRA186_BPMP
+ help
+ Enable support for manipulating Tegra's on-SoC clocks via IPC
+ requests to the BPMP (Boot and Power Management Processor).
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
new file mode 100644
index 0000000000..f32998ccc2
--- /dev/null
+++ b/drivers/clk/tegra/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o
diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c
new file mode 100644
index 0000000000..075cb464cf
--- /dev/null
+++ b/drivers/clk/tegra/tegra186-clk.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+static ulong tegra186_clk_get_rate(struct clk *clk)
+{
+ struct mrq_clk_request req;
+ struct mrq_clk_response resp;
+ int ret;
+
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
+
+ ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ return resp.clk_get_rate.rate;
+}
+
+static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct mrq_clk_request req;
+ struct mrq_clk_response resp;
+ int ret;
+
+ debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
+ clk->dev, clk->id);
+
+ req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id;
+ req.clk_set_rate.rate = rate;
+
+ ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ return resp.clk_set_rate.rate;
+}
+
+static int tegra186_clk_en_dis(struct clk *clk,
+ enum mrq_reset_commands cmd)
+{
+ struct mrq_clk_request req;
+ struct mrq_clk_response resp;
+ int ret;
+
+ req.cmd_and_id = (cmd << 24) | clk->id;
+
+ ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tegra186_clk_enable(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE);
+}
+
+static int tegra186_clk_disable(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);
+}
+
+static struct clk_ops tegra186_clk_ops = {
+ .get_rate = tegra186_clk_get_rate,
+ .set_rate = tegra186_clk_set_rate,
+ .enable = tegra186_clk_enable,
+ .disable = tegra186_clk_disable,
+};
+
+static int tegra186_clk_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra186_clk) = {
+ .name = "tegra186_clk",
+ .id = UCLASS_CLK,
+ .probe = tegra186_clk_probe,
+ .ops = &tegra186_clk_ops,
+};
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index b3e84052eb..67ebec7c57 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -161,6 +161,16 @@ config SYS_I2C_MVTWSI
Support for Marvell I2C controllers as used on the orion5x and
kirkwood SoC families.
+config TEGRA186_BPMP_I2C
+ bool "Enable Tegra186 BPMP-based I2C driver"
+ depends on TEGRA186_BPMP
+ help
+ Support for Tegra I2C controllers managed by the BPMP (Boot and
+ Power Management Processor). On Tegra186, some I2C controllers are
+ directly controlled by the main CPU, whereas others are controlled
+ by the BPMP, and can only be accessed by the main CPU via IPC
+ requests to the BPMP. This driver covers the latter case.
+
source "drivers/i2c/muxes/Kconfig"
endmenu
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 167424db98..97b6bedde8 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -41,5 +41,6 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
+obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
obj-$(CONFIG_I2C_MUX) += muxes/
diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c
new file mode 100644
index 0000000000..88e8413d9e
--- /dev/null
+++ b/drivers/i2c/tegra186_bpmp_i2c.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <misc.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra186_bpmp_i2c {
+ uint32_t bpmp_bus_id;
+};
+
+static inline void serialize_u16(uint8_t **p, uint16_t val)
+{
+ (*p)[0] = val & 0xff;
+ (*p)[1] = val >> 8;
+ (*p) += 2;
+}
+
+/* These just happen to have the same values as I2C_M_* and SERIALI2C_* */
+#define SUPPORTED_FLAGS \
+ (I2C_M_TEN | \
+ I2C_M_RD | \
+ I2C_M_STOP | \
+ I2C_M_NOSTART | \
+ I2C_M_REV_DIR_ADDR | \
+ I2C_M_IGNORE_NAK | \
+ I2C_M_NO_RD_ACK | \
+ I2C_M_RECV_LEN)
+
+static int tegra186_bpmp_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct tegra186_bpmp_i2c *priv = dev_get_priv(dev);
+ struct mrq_i2c_request req;
+ struct mrq_i2c_response resp;
+ uint8_t *p;
+ int left, i, ret;
+
+ req.cmd = CMD_I2C_XFER;
+ req.xfer.bus_id = priv->bpmp_bus_id;
+ p = &req.xfer.data_buf[0];
+ left = ARRAY_SIZE(req.xfer.data_buf);
+ for (i = 0; i < nmsgs; i++) {
+ int len = 6;
+ if (!(msg[i].flags & I2C_M_RD))
+ len += msg[i].len;
+ if ((len >= BIT(16)) || (len > left))
+ return -ENOSPC;
+
+ if (msg[i].flags & ~SUPPORTED_FLAGS)
+ return -EINVAL;
+
+ serialize_u16(&p, msg[i].addr);
+ serialize_u16(&p, msg[i].flags);
+ serialize_u16(&p, msg[i].len);
+ if (!(msg[i].flags & I2C_M_RD)) {
+ memcpy(p, msg[i].buf, msg[i].len);
+ p += msg[i].len;
+ }
+ }
+ req.xfer.data_size = p - &req.xfer.data_buf[0];
+
+ ret = misc_call(dev->parent, MRQ_I2C, &req, sizeof(req), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ p = &resp.xfer.data_buf[0];
+ left = resp.xfer.data_size;
+ if (left > ARRAY_SIZE(resp.xfer.data_buf))
+ return -EINVAL;
+ for (i = 0; i < nmsgs; i++) {
+ if (msg[i].flags & I2C_M_RD) {
+ memcpy(msg[i].buf, p, msg[i].len);
+ p += msg[i].len;
+ }
+ }
+
+ return 0;
+}
+
+static int tegra186_bpmp_i2c_probe(struct udevice *dev)
+{
+ struct tegra186_bpmp_i2c *priv = dev_get_priv(dev);
+ int ret;
+ struct fdtdec_phandle_args args;
+
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ "nvidia,bpmp", NULL, 0, 0, &args);
+ if (ret < 0) {
+ debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "nvidia,bpmp-bus-id", U32_MAX);
+ if (priv->bpmp_bus_id == U32_MAX) {
+ debug("%s: could not parse nvidia,bpmp-bus-id\n", __func__);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static const struct dm_i2c_ops tegra186_bpmp_i2c_ops = {
+ .xfer = tegra186_bpmp_i2c_xfer,
+};
+
+static const struct udevice_id tegra186_bpmp_i2c_ids[] = {
+ { .compatible = "nvidia,tegra186-bpmp-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_gpio) = {
+ .name = "tegra186_bpmp_i2c",
+ .id = UCLASS_I2C,
+ .of_match = tegra186_bpmp_i2c_ids,
+ .probe = tegra186_bpmp_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct tegra186_bpmp_i2c),
+ .ops = &tegra186_bpmp_i2c_ops,
+};
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 2fa07f9c57..31ba263b72 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -12,13 +12,27 @@
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
+#ifdef CONFIG_TEGRA186
+#include <clk.h>
+#include <reset.h>
+#else
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/clk_rst.h>
+#endif
+#include <asm/arch/gpio.h>
#include <asm/arch-tegra/tegra_i2c.h>
+/*
+ * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
+ * should not be present. These are needed because newer Tegra SoCs support
+ * only the standard clock/reset APIs, whereas older Tegra SoCs support only
+ * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
+ * fixed to implement the standard APIs, and all drivers converted to solely
+ * use the new standard APIs, with no ifdefs.
+ */
+
DECLARE_GLOBAL_DATA_PTR;
enum i2c_type {
@@ -30,7 +44,12 @@ enum i2c_type {
/* Information about i2c controller */
struct i2c_bus {
int id;
+#ifdef CONFIG_TEGRA186
+ struct reset_ctl reset_ctl;
+ struct clk clk;
+#else
enum periph_id periph_id;
+#endif
int speed;
int pinmux_config;
struct i2c_control *control;
@@ -62,12 +81,41 @@ static void set_packet_mode(struct i2c_bus *i2c_bus)
static void i2c_reset_controller(struct i2c_bus *i2c_bus)
{
/* Reset I2C controller. */
+#ifdef CONFIG_TEGRA186
+ reset_assert(&i2c_bus->reset_ctl);
+ udelay(1);
+ reset_deassert(&i2c_bus->reset_ctl);
+ udelay(1);
+#else
reset_periph(i2c_bus->periph_id, 1);
+#endif
/* re-program config register to packet mode */
set_packet_mode(i2c_bus);
}
+#ifdef CONFIG_TEGRA186
+static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
+{
+ int ret;
+
+ ret = reset_assert(&i2c_bus->reset_ctl);
+ if (ret)
+ return ret;
+ ret = clk_enable(&i2c_bus->clk);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(&i2c_bus->clk, rate);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ ret = reset_deassert(&i2c_bus->reset_ctl);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
if (!i2c_bus->speed)
@@ -78,8 +126,12 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
* here, in section 23.3.1, but in fact we seem to need a factor of
* 16 to get the right frequency.
*/
+#ifdef CONFIG_TEGRA186
+ i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
+#else
clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
i2c_bus->speed * 2 * 8);
+#endif
if (i2c_bus->type == TYPE_114) {
/*
@@ -94,12 +146,17 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
* is running, we hang, and we need it for the new calc.
*/
int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
+ unsigned rate = CLK_MULT_STD_FAST_MODE *
+ (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
clk_div_stdfst_mode);
+#ifdef CONFIG_TEGRA186
+ i2c_init_clock(i2c_bus, rate);
+#else
clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
- CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
- i2c_bus->speed * 2);
+ rate);
+#endif
}
/* Reset I2C controller. */
@@ -112,7 +169,9 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
}
+#ifndef CONFIG_TEGRA186
funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
+#endif
}
static void send_packet_headers(
@@ -333,8 +392,12 @@ static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
static int tegra_i2c_probe(struct udevice *dev)
{
struct i2c_bus *i2c_bus = dev_get_priv(dev);
+#ifdef CONFIG_TEGRA186
+ int ret;
+#else
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
+#endif
bool is_dvc;
i2c_bus->id = dev->seq;
@@ -345,6 +408,18 @@ static int tegra_i2c_probe(struct udevice *dev)
* We don't have a binding for pinmux yet. Leave it out for now. So
* far no one needs anything other than the default.
*/
+#ifdef CONFIG_TEGRA186
+ ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
+ if (ret) {
+ error("reset_get_by_name() failed: %d\n", ret);
+ return ret;
+ }
+ ret = clk_get_by_name(dev, "i2c", &i2c_bus->clk);
+ if (ret) {
+ error("clk_get_by_name() failed: %d\n", ret);
+ return ret;
+ }
+#else
i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
i2c_bus->periph_id = clock_decode_periph_id(blob, node);
@@ -359,6 +434,7 @@ static int tegra_i2c_probe(struct udevice *dev)
*/
if (i2c_bus->periph_id == -1)
return -EINVAL;
+#endif
is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
if (is_dvc) {
@@ -370,7 +446,12 @@ static int tegra_i2c_probe(struct udevice *dev)
i2c_init_controller(i2c_bus);
debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
- i2c_bus->periph_id, i2c_bus->speed);
+#ifndef CONFIG_TEGRA186
+ i2c_bus->periph_id,
+#else
+ -1,
+#endif
+ i2c_bus->speed);
return 0;
}
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 80c15581b9..4af1cbf3d7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -121,6 +121,18 @@ config PCA9551_I2C_ADDR
help
The I2C address of the PCA9551 LED controller.
+config TEGRA186_BPMP
+ bool "Enable support for the Tegra186 BPMP driver"
+ depends on TEGRA186
+ help
+ The Tegra BPMP (Boot and Power Management Processor) is a separate
+ auxiliary CPU embedded into Tegra to perform power management work,
+ and controls related features such as clocks, resets, power domains,
+ PMIC I2C bus, etc. This driver provides the core low-level
+ communication path by which feature-specific drivers (such as clock)
+ can make requests to the BPMP. This driver is similar to an MFD
+ driver in the Linux kernel.
+
config WINBOND_W83627
bool "Enable Winbond Super I/O driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index af541c6784..dac9d1007a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
endif
endif
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
+obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
diff --git a/drivers/misc/tegra186_bpmp.c b/drivers/misc/tegra186_bpmp.c
new file mode 100644
index 0000000000..f4ddbea376
--- /dev/null
+++ b/drivers/misc/tegra186_bpmp.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <mailbox.h>
+#include <misc.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+#include <asm/arch-tegra/ivc.h>
+
+#define BPMP_IVC_FRAME_COUNT 1
+#define BPMP_IVC_FRAME_SIZE 128
+
+#define BPMP_FLAG_DO_ACK BIT(0)
+#define BPMP_FLAG_RING_DOORBELL BIT(1)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra186_bpmp {
+ struct mbox_chan mbox;
+ struct tegra_ivc ivc;
+};
+
+static int tegra186_bpmp_call(struct udevice *dev, int mrq, void *tx_msg,
+ int tx_size, void *rx_msg, int rx_size)
+{
+ struct tegra186_bpmp *priv = dev_get_priv(dev);
+ int ret, err;
+ void *ivc_frame;
+ struct mrq_request *req;
+ struct mrq_response *resp;
+ ulong start_time;
+
+ debug("%s(dev=%p, mrq=%u, tx_msg=%p, tx_size=%d, rx_msg=%p, rx_size=%d) (priv=%p)\n",
+ __func__, dev, mrq, tx_msg, tx_size, rx_msg, rx_size, priv);
+
+ if ((tx_size > BPMP_IVC_FRAME_SIZE) || (rx_size > BPMP_IVC_FRAME_SIZE))
+ return -EINVAL;
+
+ ret = tegra_ivc_write_get_next_frame(&priv->ivc, &ivc_frame);
+ if (ret) {
+ error("tegra_ivc_write_get_next_frame() failed: %d\n", ret);
+ return ret;
+ }
+
+ req = ivc_frame;
+ req->mrq = mrq;
+ req->flags = BPMP_FLAG_DO_ACK | BPMP_FLAG_RING_DOORBELL;
+ memcpy(req + 1, tx_msg, tx_size);
+
+ ret = tegra_ivc_write_advance(&priv->ivc);
+ if (ret) {
+ error("tegra_ivc_write_advance() failed: %d\n", ret);
+ return ret;
+ }
+
+ start_time = timer_get_us();
+ for (;;) {
+ ret = tegra_ivc_channel_notified(&priv->ivc);
+ if (ret) {
+ error("tegra_ivc_channel_notified() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = tegra_ivc_read_get_next_frame(&priv->ivc, &ivc_frame);
+ if (!ret)
+ break;
+
+ /* Timeout 20ms; roughly 10x current max observed duration */
+ if ((timer_get_us() - start_time) > 20 * 1000) {
+ error("tegra_ivc_read_get_next_frame() timed out (%d)\n",
+ ret);
+ return -ETIMEDOUT;
+ }
+ }
+
+ resp = ivc_frame;
+ err = resp->err;
+ if (!err && rx_msg && rx_size)
+ memcpy(rx_msg, resp + 1, rx_size);
+
+ ret = tegra_ivc_read_advance(&priv->ivc);
+ if (ret) {
+ error("tegra_ivc_write_advance() failed: %d\n", ret);
+ return ret;
+ }
+
+ if (err) {
+ error("BPMP responded with error %d\n", err);
+ /* err isn't a U-Boot error code, so don't that */
+ return -EIO;
+ }
+
+ return rx_size;
+}
+
+/**
+ * The BPMP exposes multiple different services. We create a sub-device for
+ * each separate type of service, since each device must be of the appropriate
+ * UCLASS.
+ */
+static int tegra186_bpmp_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *child;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk",
+ dev->of_offset, &child);
+ if (ret)
+ return ret;
+
+ ret = device_bind_driver_to_node(dev, "tegra186_reset",
+ "tegra186_reset", dev->of_offset,
+ &child);
+ if (ret)
+ return ret;
+
+ ret = device_bind_driver_to_node(dev, "tegra186_power_domain",
+ "tegra186_power_domain",
+ dev->of_offset, &child);
+ if (ret)
+ return ret;
+
+ ret = dm_scan_fdt_dev(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static ulong tegra186_bpmp_get_shmem(struct udevice *dev, int index)
+{
+ int ret;
+ struct fdtdec_phandle_args args;
+ fdt_addr_t reg;
+
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ "shmem", NULL, 0, index, &args);
+ if (ret < 0) {
+ error("fdtdec_parse_phandle_with_args() failed: %d\n", ret);
+ return ret;
+ }
+
+ reg = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, args.node,
+ "reg", 0, NULL, true);
+ if (reg == FDT_ADDR_T_NONE) {
+ error("fdtdec_get_addr_size_auto_noparent() failed\n");
+ return -ENODEV;
+ }
+
+ return reg;
+}
+
+static void tegra186_bpmp_ivc_notify(struct tegra_ivc *ivc)
+{
+ struct tegra186_bpmp *priv =
+ container_of(ivc, struct tegra186_bpmp, ivc);
+ int ret;
+
+ ret = mbox_send(&priv->mbox, NULL);
+ if (ret)
+ error("mbox_send() failed: %d\n", ret);
+}
+
+static int tegra186_bpmp_probe(struct udevice *dev)
+{
+ struct tegra186_bpmp *priv = dev_get_priv(dev);
+ int ret;
+ ulong tx_base, rx_base, start_time;
+
+ debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
+
+ ret = mbox_get_by_index(dev, 0, &priv->mbox);
+ if (ret) {
+ error("mbox_get_by_index() failed: %d\n", ret);
+ return ret;
+ }
+
+ tx_base = tegra186_bpmp_get_shmem(dev, 0);
+ if (IS_ERR_VALUE(tx_base)) {
+ error("tegra186_bpmp_get_shmem failed for tx_base\n");
+ return tx_base;
+ }
+ rx_base = tegra186_bpmp_get_shmem(dev, 1);
+ if (IS_ERR_VALUE(rx_base)) {
+ error("tegra186_bpmp_get_shmem failed for rx_base\n");
+ return rx_base;
+ }
+ debug("shmem: rx=%lx, tx=%lx\n", rx_base, tx_base);
+
+ ret = tegra_ivc_init(&priv->ivc, rx_base, tx_base, BPMP_IVC_FRAME_COUNT,
+ BPMP_IVC_FRAME_SIZE, tegra186_bpmp_ivc_notify);
+ if (ret) {
+ error("tegra_ivc_init() failed: %d\n", ret);
+ return ret;
+ }
+
+ tegra_ivc_channel_reset(&priv->ivc);
+ start_time = timer_get_us();
+ for (;;) {
+ ret = tegra_ivc_channel_notified(&priv->ivc);
+ if (!ret)
+ break;
+
+ /* Timeout 100ms */
+ if ((timer_get_us() - start_time) > 100 * 1000) {
+ error("Initial IVC reset timed out (%d)\n", ret);
+ ret = -ETIMEDOUT;
+ goto err_free_mbox;
+ }
+ }
+
+ return 0;
+
+err_free_mbox:
+ mbox_free(&priv->mbox);
+
+ return ret;
+}
+
+static int tegra186_bpmp_remove(struct udevice *dev)
+{
+ struct tegra186_bpmp *priv = dev_get_priv(dev);
+
+ debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
+
+ mbox_free(&priv->mbox);
+
+ return 0;
+}
+
+static struct misc_ops tegra186_bpmp_ops = {
+ .call = tegra186_bpmp_call,
+};
+
+static const struct udevice_id tegra186_bpmp_ids[] = {
+ { .compatible = "nvidia,tegra186-bpmp" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra186_bpmp) = {
+ .name = "tegra186_bpmp",
+ .id = UCLASS_MISC,
+ .of_match = tegra186_bpmp_ids,
+ .bind = tegra186_bpmp_bind,
+ .probe = tegra186_bpmp_probe,
+ .remove = tegra186_bpmp_remove,
+ .ops = &tegra186_bpmp_ops,
+ .priv_auto_alloc_size = sizeof(struct tegra186_bpmp),
+};
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 023ba3c643..f0a39a63c6 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -9,6 +9,7 @@
#include <bouncebuf.h>
#include <common.h>
+#include <dm/device.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -20,6 +21,15 @@
#include <asm/arch-tegra/tegra_mmc.h>
#include <mmc.h>
+/*
+ * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
+ * should not be present. These are needed because newer Tegra SoCs support
+ * only the standard clock/reset APIs, whereas older Tegra SoCs support only
+ * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
+ * fixed to implement the standard APIs, and all drivers converted to solely
+ * use the new standard APIs, with no ifdefs.
+ */
+
DECLARE_GLOBAL_DATA_PTR;
struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
@@ -360,11 +370,14 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
*/
if (clock == 0)
goto out;
-#ifndef CONFIG_TEGRA186
+#ifdef CONFIG_TEGRA186
+ {
+ ulong rate = clk_set_rate(&host->clk, clock);
+ div = (rate + clock - 1) / clock;
+ }
+#else
clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
&div);
-#else
- div = (20000000 + clock - 1) / clock;
#endif
debug("div = %d\n", div);
@@ -539,6 +552,9 @@ static int do_mmc_init(int dev_index, bool removable)
{
struct mmc_host *host;
struct mmc *mmc;
+#ifdef CONFIG_TEGRA186
+ int ret;
+#endif
/* DT should have been read & host config filled in */
host = &mmc_host[dev_index];
@@ -550,7 +566,21 @@ static int do_mmc_init(int dev_index, bool removable)
gpio_get_number(&host->cd_gpio));
host->clock = 0;
-#ifndef CONFIG_TEGRA186
+
+#ifdef CONFIG_TEGRA186
+ ret = reset_assert(&host->reset_ctl);
+ if (ret)
+ return ret;
+ ret = clk_enable(&host->clk);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(&host->clk, 20000000);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ ret = reset_deassert(&host->reset_ctl);
+ if (ret)
+ return ret;
+#else
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
#endif
@@ -577,11 +607,7 @@ static int do_mmc_init(int dev_index, bool removable)
* (actually 52MHz)
*/
host->cfg.f_min = 375000;
-#ifndef CONFIG_TEGRA186
host->cfg.f_max = 48000000;
-#else
- host->cfg.f_max = 375000;
-#endif
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
@@ -613,7 +639,27 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
return -FDT_ERR_NOTFOUND;
}
-#ifndef CONFIG_TEGRA186
+#ifdef CONFIG_TEGRA186
+ {
+ /*
+ * FIXME: This variable should go away when the MMC device
+ * actually is a udevice.
+ */
+ struct udevice dev;
+ int ret;
+ dev.of_offset = node;
+ ret = reset_get_by_name(&dev, "sdmmc", &host->reset_ctl);
+ if (ret) {
+ debug("reset_get_by_index() failed: %d\n", ret);
+ return ret;
+ }
+ ret = clk_get_by_name(&dev, "sdmmc", &host->clk);
+ if (ret) {
+ debug("clk_get_by_index() failed: %d\n", ret);
+ return ret;
+ }
+ }
+#else
host->mmc_id = clock_decode_periph_id(blob, node);
if (host->mmc_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id\n", __func__);
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 26aa2b0930..669e37bb5d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -31,6 +31,7 @@ config PCI_SANDBOX
config PCI_TEGRA
bool "Tegra PCI support"
depends on TEGRA
+ depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
help
Enable support for the PCIe controller found on some generations of
Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index 352cdef56a..ea8adb98db 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -13,22 +13,35 @@
#define pr_fmt(fmt) "tegra-pcie: " fmt
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <pci.h>
+#include <power-domain.h>
+#include <reset.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <linux/list.h>
+
+#ifndef CONFIG_TEGRA186
#include <asm/arch/clock.h>
#include <asm/arch/powergate.h>
#include <asm/arch-tegra/xusb-padctl.h>
-
-#include <linux/list.h>
-
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+#endif
+
+/*
+ * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
+ * should not be present. These are needed because newer Tegra SoCs support
+ * only the standard clock/reset APIs, whereas older Tegra SoCs support only
+ * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
+ * fixed to implement the standard APIs, and all drivers converted to solely
+ * use the new standard APIs, with no ifdefs.
+ */
DECLARE_GLOBAL_DATA_PTR;
@@ -103,6 +116,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
#define AFI_FUSE 0x104
#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
@@ -110,6 +126,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define AFI_PEX0_CTRL 0x110
#define AFI_PEX1_CTRL 0x118
#define AFI_PEX2_CTRL 0x128
+#define AFI_PEX2_CTRL_T186 0x19c
#define AFI_PEX_CTRL_RST (1 << 0)
#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
@@ -173,6 +190,7 @@ enum tegra_pci_id {
TEGRA30_PCIE,
TEGRA124_PCIE,
TEGRA210_PCIE,
+ TEGRA186_PCIE,
};
struct tegra_pcie_port {
@@ -189,6 +207,7 @@ struct tegra_pcie_soc {
unsigned int num_ports;
unsigned long pads_pll_ctl;
unsigned long tx_ref_sel;
+ unsigned long afi_pex2_ctrl;
u32 pads_refclk_cfg0;
u32 pads_refclk_cfg1;
bool has_pex_clkreq_en;
@@ -209,7 +228,17 @@ struct tegra_pcie {
unsigned long xbar;
const struct tegra_pcie_soc *soc;
+
+#ifdef CONFIG_TEGRA186
+ struct clk clk_afi;
+ struct clk clk_pex;
+ struct reset_ctl reset_afi;
+ struct reset_ctl reset_pex;
+ struct reset_ctl reset_pcie_x;
+ struct power_domain pwrdom;
+#else
struct tegra_xusb_phy *phy;
+#endif
};
static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
@@ -229,10 +258,12 @@ static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
writel(value, pcie->pads.start + offset);
}
+#ifndef CONFIG_TEGRA186
static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
{
return readl(pcie->pads.start + offset);
}
+#endif
static unsigned long rp_readl(struct tegra_pcie_port *port,
unsigned long offset)
@@ -400,6 +431,24 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
return 0;
}
break;
+ case TEGRA186_PCIE:
+ switch (lanes) {
+ case 0x0010004:
+ debug("x4 x1 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
+ return 0;
+
+ case 0x0010102:
+ debug("x2 x1 x1 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
+ return 0;
+
+ case 0x0010101:
+ debug("x1 x1 x1 configuration\n");
+ *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
+ return 0;
+ }
+ break;
default:
break;
}
@@ -471,6 +520,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
return err;
}
+#ifndef CONFIG_TEGRA186
pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
if (pcie->phy) {
err = tegra_xusb_phy_prepare(pcie->phy);
@@ -479,6 +529,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
return err;
}
}
+#endif
fdt_for_each_subnode(fdt, subnode, node) {
unsigned int index = 0, num_lanes = 0;
@@ -523,6 +574,44 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
return 0;
}
+#ifdef CONFIG_TEGRA186
+static int tegra_pcie_power_on(struct tegra_pcie *pcie)
+{
+ int ret;
+
+ ret = power_domain_on(&pcie->pwrdom);
+ if (ret) {
+ error("power_domain_on() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_enable(&pcie->clk_afi);
+ if (ret) {
+ error("clk_enable(afi) failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_enable(&pcie->clk_pex);
+ if (ret) {
+ error("clk_enable(pex) failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&pcie->reset_afi);
+ if (ret) {
+ error("reset_deassert(afi) failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&pcie->reset_pex);
+ if (ret) {
+ error("reset_deassert(pex) failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+#else
static int tegra_pcie_power_on(struct tegra_pcie *pcie)
{
const struct tegra_pcie_soc *soc = pcie->soc;
@@ -639,6 +728,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
return 0;
}
+#endif
static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
{
@@ -647,7 +737,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
u32 value;
int err;
+#ifdef CONFIG_TEGRA186
+ {
+#else
if (pcie->phy) {
+#endif
value = afi_readl(pcie, AFI_PLLE_CONTROL);
value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
@@ -675,6 +769,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
afi_writel(pcie, value, AFI_FUSE);
+#ifndef CONFIG_TEGRA186
if (pcie->phy)
err = tegra_xusb_phy_enable(pcie->phy);
else
@@ -684,9 +779,18 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
error("failed to power on PHY: %d\n", err);
return err;
}
+#endif
/* take the PCIEXCLK logic out of reset */
+#ifdef CONFIG_TEGRA186
+ err = reset_deassert(&pcie->reset_pcie_x);
+ if (err) {
+ error("reset_deassert(pcie_x) failed: %d\n", err);
+ return err;
+ }
+#else
reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
+#endif
/* finally enable PCIe */
value = afi_readl(pcie, AFI_CONFIGURATION);
@@ -787,7 +891,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
break;
case 2:
- ret = AFI_PEX2_CTRL;
+ ret = port->pcie->soc->afi_pex2_ctrl;
break;
}
@@ -945,6 +1049,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
.num_ports = 3,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+ .afi_pex2_ctrl = AFI_PEX2_CTRL,
.pads_refclk_cfg0 = 0xfa5cfa5c,
.pads_refclk_cfg1 = 0xfa5cfa5c,
.has_pex_clkreq_en = true,
@@ -972,7 +1077,16 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
.has_cml_clk = true,
.has_gen2 = true,
.force_pca_enable = true,
- }
+ },
+ [TEGRA186_PCIE] = {
+ .num_ports = 3,
+ .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
+ .pads_refclk_cfg0 = 0x80b880b8,
+ .pads_refclk_cfg1 = 0x000480b8,
+ .has_pex_clkreq_en = true,
+ .has_pex_bias_ctrl = true,
+ .has_gen2 = true,
+ },
};
static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
@@ -996,6 +1110,44 @@ static int pci_tegra_probe(struct udevice *dev)
struct tegra_pcie *pcie = dev_get_priv(dev);
int err;
+#ifdef CONFIG_TEGRA186
+ err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
+ if (err) {
+ debug("clk_get_by_name(afi) failed: %d\n", err);
+ return err;
+ }
+
+ err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
+ if (err) {
+ debug("clk_get_by_name(pex) failed: %d\n", err);
+ return err;
+ }
+
+ err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
+ if (err) {
+ debug("reset_get_by_name(afi) failed: %d\n", err);
+ return err;
+ }
+
+ err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
+ if (err) {
+ debug("reset_get_by_name(pex) failed: %d\n", err);
+ return err;
+ }
+
+ err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
+ if (err) {
+ debug("reset_get_by_name(pcie_x) failed: %d\n", err);
+ return err;
+ }
+
+ err = power_domain_get(dev, &pcie->pwrdom);
+ if (err) {
+ debug("power_domain_get() failed: %d\n", err);
+ return err;
+ }
+#endif
+
err = tegra_pcie_power_on(pcie);
if (err < 0) {
error("failed to power on");
@@ -1033,6 +1185,7 @@ static const struct udevice_id pci_tegra_ids[] = {
{ .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
{ .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
{ .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
+ { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
{ }
};
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index b904097433..132e33250e 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -17,4 +17,11 @@ config SANDBOX_POWER_DOMAIN
simply accepts requests to power on/off various HW modules without
actually doing anything beyond a little error checking.
+config TEGRA186_POWER_DOMAIN
+ bool "Enable Tegra186 BPMP-based power domain driver"
+ depends on TEGRA186_BPMP
+ help
+ Enable support for manipulating Tegra's on-SoC power domains via IPC
+ requests to the BPMP (Boot and Power Management Processor).
+
endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index c18292f0ec..2c3d92638f 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
+obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c
new file mode 100644
index 0000000000..41d84de83e
--- /dev/null
+++ b/drivers/power/domain/tegra186-power-domain.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <power-domain-uclass.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+#define UPDATE BIT(0)
+#define ON BIT(1)
+
+static int tegra186_power_domain_request(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__,
+ power_domain, power_domain->dev, power_domain->id);
+
+ return 0;
+}
+
+static int tegra186_power_domain_free(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__,
+ power_domain, power_domain->dev, power_domain->id);
+
+ return 0;
+}
+
+static int tegra186_power_domain_common(struct power_domain *power_domain,
+ bool on)
+{
+ struct mrq_pg_update_state_request req;
+ int on_state = on ? ON : 0;
+ int ret;
+
+ req.partition_id = power_domain->id;
+ req.logic_state = UPDATE | on_state;
+ req.sram_state = UPDATE | on_state;
+ /*
+ * Drivers manage their own clocks so they don't get out of sync, and
+ * since some power domains have many clocks, only a subset of which
+ * are actually needed depending on use-case.
+ */
+ req.clock_state = UPDATE;
+
+ ret = misc_call(power_domain->dev->parent, MRQ_PG_UPDATE_STATE, &req,
+ sizeof(req), NULL, 0);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tegra186_power_domain_on(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__,
+ power_domain, power_domain->dev, power_domain->id);
+
+ return tegra186_power_domain_common(power_domain, true);
+}
+
+static int tegra186_power_domain_off(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__,
+ power_domain, power_domain->dev, power_domain->id);
+
+ return tegra186_power_domain_common(power_domain, false);
+}
+
+struct power_domain_ops tegra186_power_domain_ops = {
+ .request = tegra186_power_domain_request,
+ .free = tegra186_power_domain_free,
+ .on = tegra186_power_domain_on,
+ .off = tegra186_power_domain_off,
+};
+
+static int tegra186_power_domain_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra186_power_domain) = {
+ .name = "tegra186_power_domain",
+ .id = UCLASS_POWER_DOMAIN,
+ .probe = tegra186_power_domain_probe,
+ .ops = &tegra186_power_domain_ops,
+};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0fe8cc3827..5b84f2178b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,4 +20,11 @@ config SANDBOX_RESET
simply accepts requests to reset various HW modules without actually
doing anything beyond a little error checking.
+config TEGRA186_RESET
+ bool "Enable Tegra186 BPMP-based reset driver"
+ depends on TEGRA186_BPMP
+ help
+ Enable support for manipulating Tegra's on-SoC reset signals via IPC
+ requests to the BPMP (Boot and Power Management Processor).
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 71f3b21961..ff0e090775 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_DM_RESET) += reset-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c
new file mode 100644
index 0000000000..228adda0aa
--- /dev/null
+++ b/drivers/reset/tegra186-reset.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <reset-uclass.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+static int tegra186_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int tegra186_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int tegra186_reset_common(struct reset_ctl *reset_ctl,
+ enum mrq_reset_commands cmd)
+{
+ struct mrq_reset_request req;
+ int ret;
+
+ req.cmd = cmd;
+ req.reset_id = reset_ctl->id;
+
+ ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req),
+ NULL, 0);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
+}
+
+static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
+}
+
+struct reset_ops tegra186_reset_ops = {
+ .request = tegra186_reset_request,
+ .free = tegra186_reset_free,
+ .rst_assert = tegra186_reset_assert,
+ .rst_deassert = tegra186_reset_deassert,
+};
+
+static int tegra186_reset_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra186_reset) = {
+ .name = "tegra186_reset",
+ .id = UCLASS_RESET,
+ .probe = tegra186_reset_probe,
+ .ops = &tegra186_reset_ops,
+};
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-23 07:18:03 +0000