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-rw-r--r--drivers/watchdog/Kconfig4
-rw-r--r--drivers/watchdog/designware_wdt.c21
2 files changed, 2 insertions, 23 deletions
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c3eb8a8aec..532ada89c1 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -64,8 +64,8 @@ config ULP_WATCHDOG
config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"
- select HW_WATCHDOG if !WDT
- default y if WDT && ROCKCHIP_RK3399
+ depends on WDT
+ default y if ROCKCHIP_RK3399
help
Enable this to support Designware Watchdog Timer IP, present e.g.
on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index cfec29bd15..cad756aeaf 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -60,26 +60,6 @@ static void designware_wdt_reset_common(void __iomem *base)
writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
}
-#if !CONFIG_IS_ENABLED(WDT)
-void hw_watchdog_reset(void)
-{
- designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
-}
-
-void hw_watchdog_init(void)
-{
- /* reset to disable the watchdog */
- hw_watchdog_reset();
- /* set timer in miliseconds */
- designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
- CONFIG_DW_WDT_CLOCK_KHZ,
- CONFIG_WATCHDOG_TIMEOUT_MSECS);
- /* enable the watchdog */
- designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
- /* reset the watchdog */
- hw_watchdog_reset();
-}
-#else
static int designware_wdt_reset(struct udevice *dev)
{
struct designware_wdt_priv *priv = dev_get_priv(dev);
@@ -195,4 +175,3 @@ U_BOOT_DRIVER(designware_wdt) = {
.ops = &designware_wdt_ops,
.flags = DM_FLAG_PRE_RELOC,
};
-#endif