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-rw-r--r--drivers/spi/Kconfig16
-rw-r--r--drivers/spi/Makefile2
-rw-r--r--drivers/spi/cadence_qspi.c19
-rw-r--r--drivers/spi/cadence_qspi.h6
-rw-r--r--drivers/spi/cadence_qspi_apb.c7
-rw-r--r--drivers/spi/fsl_dspi.c30
-rw-r--r--drivers/spi/spi-mem.c2
-rw-r--r--drivers/spi/spi-uclass.c4
-rw-r--r--drivers/spi/stm32_qspi.c625
-rw-r--r--drivers/spi/ti_qspi.c351
-rw-r--r--drivers/spi/zynqmp_gqspi.c4
11 files changed, 414 insertions, 652 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 098372e093..fb794adae7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -222,8 +222,7 @@ config SPI_SUNXI
config STM32_QSPI
bool "STM32F7 QSPI driver"
- depends on STM32F7
- imply SPI_FLASH_BAR
+ depends on STM32F7 || ARCH_STM32MP
help
Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash chips on platforms embedding
@@ -260,6 +259,13 @@ config TEGRA210_QSPI
be used to access SPI chips on platforms embedding this
NVIDIA Tegra210 IP core.
+config TI_QSPI
+ bool "TI QSPI driver"
+ imply TI_EDMA3
+ help
+ Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
+ This driver support spi flash single, quad and memory reads.
+
config XILINX_SPI
bool "Xilinx SPI driver"
help
@@ -347,12 +353,6 @@ config SH_QSPI
Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs.
-config TI_QSPI
- bool "TI QSPI driver"
- help
- Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
- This driver support spi flash single, quad and memory reads.
-
config KIRKWOOD_SPI
bool "Marvell Kirkwood SPI Driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 01907bef79..8be9a4baa2 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -9,6 +9,7 @@ obj-y += spi-uclass.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
+obj-$(CONFIG_TI_QSPI) += ti_qspi.o
else
obj-y += spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
@@ -56,7 +57,6 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
-obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 11fce9c4fe..41c87004d8 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <reset.h>
#include <spi.h>
#include <linux/errno.h>
#include "cadence_qspi.h"
@@ -154,10 +155,17 @@ static int cadence_spi_probe(struct udevice *bus)
{
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
+ int ret;
priv->regbase = plat->regbase;
priv->ahbbase = plat->ahbbase;
+ ret = reset_get_bulk(bus, &priv->resets);
+ if (ret)
+ dev_warn(bus, "Can't get reset: %d\n", ret);
+ else
+ reset_deassert_bulk(&priv->resets);
+
if (!priv->qspi_is_init) {
cadence_qspi_apb_controller_init(plat);
priv->qspi_is_init = 1;
@@ -166,6 +174,13 @@ static int cadence_spi_probe(struct udevice *bus)
return 0;
}
+static int cadence_spi_remove(struct udevice *dev)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(dev);
+
+ return reset_release_bulk(&priv->resets);
+}
+
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
@@ -256,7 +271,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
break;
case CQSPI_INDIRECT_WRITE:
err = cadence_qspi_apb_indirect_write_setup
- (plat, priv->cmd_len, cmd_buf);
+ (plat, priv->cmd_len, dm_plat->mode, cmd_buf);
if (!err) {
err = cadence_qspi_apb_indirect_write_execute
(plat, data_bytes, dout);
@@ -342,4 +357,6 @@ U_BOOT_DRIVER(cadence_spi) = {
.platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
.priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
.probe = cadence_spi_probe,
+ .remove = cadence_spi_remove,
+ .flags = DM_FLAG_OS_PREPARE,
};
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 055900def0..20cceca239 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -7,6 +7,8 @@
#ifndef __CADENCE_QSPI_H__
#define __CADENCE_QSPI_H__
+#include <reset.h>
+
#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
#define CQSPI_NO_DECODER_MAX_CS 4
@@ -42,6 +44,8 @@ struct cadence_spi_priv {
unsigned int qspi_calibrated_hz;
unsigned int qspi_calibrated_cs;
unsigned int previous_hz;
+
+ struct reset_ctl_bulk resets;
};
/* Functions call declaration */
@@ -60,7 +64,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
unsigned int rxlen, u8 *rxbuf);
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
- unsigned int cmdlen, const u8 *cmdbuf);
+ unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
unsigned int txlen, const u8 *txbuf);
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index a8af352030..55a7501913 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -77,6 +77,7 @@
#define CQSPI_REG_WR_INSTR 0x08
#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
+#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
#define CQSPI_REG_DELAY 0x0C
#define CQSPI_REG_DELAY_TSLCH_LSB 0
@@ -686,7 +687,7 @@ failrd:
/* Opcode + Address (3/4 bytes) */
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
- unsigned int cmdlen, const u8 *cmdbuf)
+ unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf)
{
unsigned int reg;
unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
@@ -702,6 +703,10 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
/* Configure the opcode */
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
+
+ if (tx_width & SPI_TX_QUAD)
+ reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
+
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
/* Setup write address. */
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 764c94215e..a68a51945e 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -273,7 +273,18 @@ static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
if (len > 1) {
int tmp_len = len - 1;
while (tmp_len--) {
- if (dout != NULL) {
+ if ((dout != NULL) && (din != NULL)) {
+ if (priv->charbit == 16) {
+ dspi_tx(priv, ctrl, *spi_wr16++);
+ *spi_rd16++ = dspi_rx(priv);
+ }
+ else {
+ dspi_tx(priv, ctrl, *spi_wr++);
+ *spi_rd++ = dspi_rx(priv);
+ }
+ }
+
+ else if (dout != NULL) {
if (priv->charbit == 16)
dspi_tx(priv, ctrl, *spi_wr16++);
else
@@ -281,7 +292,7 @@ static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
dspi_rx(priv);
}
- if (din != NULL) {
+ else if (din != NULL) {
dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
if (priv->charbit == 16)
*spi_rd16++ = dspi_rx(priv);
@@ -297,7 +308,18 @@ static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
ctrl &= ~DSPI_TFR_CONT;
if (len) {
- if (dout != NULL) {
+ if ((dout != NULL) && (din != NULL)) {
+ if (priv->charbit == 16) {
+ dspi_tx(priv, ctrl, *spi_wr16++);
+ *spi_rd16++ = dspi_rx(priv);
+ }
+ else {
+ dspi_tx(priv, ctrl, *spi_wr++);
+ *spi_rd++ = dspi_rx(priv);
+ }
+ }
+
+ else if (dout != NULL) {
if (priv->charbit == 16)
dspi_tx(priv, ctrl, *spi_wr16);
else
@@ -305,7 +327,7 @@ static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
dspi_rx(priv);
}
- if (din != NULL) {
+ else if (din != NULL) {
dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
if (priv->charbit == 16)
*spi_rd16 = dspi_rx(priv);
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 1bb0987edb..b86eee75bc 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -214,7 +214,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
if (ret < 0)
return ret;
- if (ops->mem_ops) {
+ if (ops->mem_ops && ops->mem_ops->exec_op) {
#ifndef __UBOOT__
/*
* Flush the message queue before executing our SPI memory
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 2bc289a74c..88cb2a1262 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -328,7 +328,9 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
}
plat = dev_get_parent_platdata(dev);
- if (!speed) {
+
+ /* get speed and mode from platdata when available */
+ if (plat->max_hz) {
speed = plat->max_hz;
mode = plat->mode;
}
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 8b60d7c3b2..bb1067ff4a 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -9,15 +9,11 @@
#include <common.h>
#include <clk.h>
-#include <dm.h>
-#include <errno.h>
-#include <malloc.h>
#include <reset.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
+#include <spi-mem.h>
+#include <linux/iopoll.h>
#include <linux/ioport.h>
+#include <linux/sizes.h>
struct stm32_qspi_regs {
u32 cr; /* 0x00 */
@@ -45,8 +41,7 @@ struct stm32_qspi_regs {
#define STM32_QSPI_CR_SSHIFT BIT(4)
#define STM32_QSPI_CR_DFM BIT(6)
#define STM32_QSPI_CR_FSEL BIT(7)
-#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
-#define STM32_QSPI_CR_FTHRES_SHIFT (8)
+#define STM32_QSPI_CR_FTHRES_SHIFT 8
#define STM32_QSPI_CR_TEIE BIT(16)
#define STM32_QSPI_CR_TCIE BIT(17)
#define STM32_QSPI_CR_FTIE BIT(18)
@@ -55,16 +50,16 @@ struct stm32_qspi_regs {
#define STM32_QSPI_CR_APMS BIT(22)
#define STM32_QSPI_CR_PMM BIT(23)
#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
-#define STM32_QSPI_CR_PRESCALER_SHIFT (24)
+#define STM32_QSPI_CR_PRESCALER_SHIFT 24
/*
* QUADSPI device configuration register
*/
#define STM32_QSPI_DCR_CKMODE BIT(0)
#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
-#define STM32_QSPI_DCR_CSHT_SHIFT (8)
+#define STM32_QSPI_DCR_CSHT_SHIFT 8
#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
-#define STM32_QSPI_DCR_FSIZE_SHIFT (16)
+#define STM32_QSPI_DCR_FSIZE_SHIFT 16
/*
* QUADSPI status register
@@ -75,8 +70,6 @@ struct stm32_qspi_regs {
#define STM32_QSPI_SR_SMF BIT(3)
#define STM32_QSPI_SR_TOF BIT(4)
#define STM32_QSPI_SR_BUSY BIT(5)
-#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
-#define STM32_QSPI_SR_FLEVEL_SHIFT (8)
/*
* QUADSPI flag clear register
@@ -92,388 +85,276 @@ struct stm32_qspi_regs {
#define STM32_QSPI_CCR_DDRM BIT(31)
#define STM32_QSPI_CCR_DHHC BIT(30)
#define STM32_QSPI_CCR_SIOO BIT(28)
-#define STM32_QSPI_CCR_FMODE_SHIFT (26)
-#define STM32_QSPI_CCR_DMODE_SHIFT (24)
-#define STM32_QSPI_CCR_DCYC_SHIFT (18)
-#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
-#define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
-#define STM32_QSPI_CCR_ABMODE_SHIFT (14)
-#define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
-#define STM32_QSPI_CCR_ADMODE_SHIFT (10)
-#define STM32_QSPI_CCR_IMODE_SHIFT (8)
-#define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
-
-enum STM32_QSPI_CCR_IMODE {
- STM32_QSPI_CCR_IMODE_NONE = 0,
- STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
- STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
- STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
-};
-
-enum STM32_QSPI_CCR_ADMODE {
- STM32_QSPI_CCR_ADMODE_NONE = 0,
- STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
- STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
- STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
-};
-
-enum STM32_QSPI_CCR_ADSIZE {
- STM32_QSPI_CCR_ADSIZE_8BIT = 0,
- STM32_QSPI_CCR_ADSIZE_16BIT = 1,
- STM32_QSPI_CCR_ADSIZE_24BIT = 2,
- STM32_QSPI_CCR_ADSIZE_32BIT = 3,
-};
-
-enum STM32_QSPI_CCR_ABMODE {
- STM32_QSPI_CCR_ABMODE_NONE = 0,
- STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
- STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
- STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
-};
-
-enum STM32_QSPI_CCR_ABSIZE {
- STM32_QSPI_CCR_ABSIZE_8BIT = 0,
- STM32_QSPI_CCR_ABSIZE_16BIT = 1,
- STM32_QSPI_CCR_ABSIZE_24BIT = 2,
- STM32_QSPI_CCR_ABSIZE_32BIT = 3,
-};
-
-enum STM32_QSPI_CCR_DMODE {
- STM32_QSPI_CCR_DMODE_NONE = 0,
- STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
- STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
- STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
-};
-
-enum STM32_QSPI_CCR_FMODE {
- STM32_QSPI_CCR_IND_WRITE = 0,
- STM32_QSPI_CCR_IND_READ = 1,
- STM32_QSPI_CCR_AUTO_POLL = 2,
- STM32_QSPI_CCR_MEM_MAP = 3,
-};
-
-/* default SCK frequency, unit: HZ */
-#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
-
-#define STM32_MAX_NORCHIP 2
-
-struct stm32_qspi_platdata {
- u32 base;
- u32 memory_map;
- u32 max_hz;
+#define STM32_QSPI_CCR_FMODE_SHIFT 26
+#define STM32_QSPI_CCR_DMODE_SHIFT 24
+#define STM32_QSPI_CCR_DCYC_SHIFT 18
+#define STM32_QSPI_CCR_ABSIZE_SHIFT 16
+#define STM32_QSPI_CCR_ABMODE_SHIFT 14
+#define STM32_QSPI_CCR_ADSIZE_SHIFT 12
+#define STM32_QSPI_CCR_ADMODE_SHIFT 10
+#define STM32_QSPI_CCR_IMODE_SHIFT 8
+
+#define STM32_QSPI_CCR_IND_WRITE 0
+#define STM32_QSPI_CCR_IND_READ 1
+#define STM32_QSPI_CCR_MEM_MAP 3
+
+#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
+#define STM32_QSPI_MAX_CHIP 2
+
+#define STM32_QSPI_FIFO_TIMEOUT_US 30000
+#define STM32_QSPI_CMD_TIMEOUT_US 1000000
+#define STM32_BUSY_TIMEOUT_US 100000
+#define STM32_ABT_TIMEOUT_US 100000
+
+struct stm32_qspi_flash {
+ u32 cr;
+ u32 dcr;
+ bool initialized;
};
struct stm32_qspi_priv {
struct stm32_qspi_regs *regs;
+ struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
+ void __iomem *mm_base;
+ resource_size_t mm_size;
ulong clock_rate;
- u32 max_hz;
- u32 mode;
-
- u32 command;
- u32 address;
- u32 dummycycles;
-#define CMD_HAS_ADR BIT(24)
-#define CMD_HAS_DUMMY BIT(25)
-#define CMD_HAS_DATA BIT(26)
+ int cs_used;
};
-static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
+static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
{
- clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
-}
+ u32 sr;
+ int ret;
-static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
-{
- setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
-}
+ ret = readl_poll_timeout(&priv->regs->sr, sr,
+ !(sr & STM32_QSPI_SR_BUSY),
+ STM32_BUSY_TIMEOUT_US);
+ if (ret)
+ pr_err("busy timeout (stat:%#x)\n", sr);
-static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
-{
- while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
- ;
+ return ret;
}
-static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
+static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
+ const struct spi_mem_op *op)
{
- while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
- ;
-}
+ u32 sr;
+ int ret;
-static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
-{
- while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
- ;
-}
+ if (!op->data.nbytes)
+ return _stm32_qspi_wait_for_not_busy(priv);
-static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
-{
- u32 fsize = fls(size) - 1;
+ ret = readl_poll_timeout(&priv->regs->sr, sr,
+ sr & STM32_QSPI_SR_TCF,
+ STM32_QSPI_CMD_TIMEOUT_US);
+ if (ret) {
+ pr_err("cmd timeout (stat:%#x)\n", sr);
+ } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
+ pr_err("transfer error (stat:%#x)\n", sr);
+ ret = -EIO;
+ }
- clrsetbits_le32(&priv->regs->dcr,
- STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
- fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
+ /* clear flags */
+ writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
+
+ return ret;
}
-static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
+static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
{
- clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
- cs ? STM32_QSPI_CR_FSEL : 0);
+ *val = readb(addr);
}
-static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode)
+static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
{
- unsigned int ccr_reg = 0;
- u8 imode, admode, dmode;
- u32 mode = priv->mode;
- u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
-
- imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
- admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
- dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
-
- if ((priv->command & CMD_HAS_ADR) && (priv->command & CMD_HAS_DATA)) {
- if (fmode == STM32_QSPI_CCR_IND_WRITE) {
- if (mode & SPI_TX_QUAD)
- dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
- else if (mode & SPI_TX_DUAL)
- dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
- } else if ((fmode == STM32_QSPI_CCR_MEM_MAP) ||
- (fmode == STM32_QSPI_CCR_IND_READ)) {
- if (mode & SPI_RX_QUAD)
- dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
- else if (mode & SPI_RX_DUAL)
- dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
- }
- }
-
- if (priv->command & CMD_HAS_DATA)
- ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
-
- if (priv->command & CMD_HAS_DUMMY)
- ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
- << STM32_QSPI_CCR_DCYC_SHIFT);
-
- if (priv->command & CMD_HAS_ADR) {
- ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
- << STM32_QSPI_CCR_ADSIZE_SHIFT);
- ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
- }
-
- ccr_reg |= (fmode << STM32_QSPI_CCR_FMODE_SHIFT);
- ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
- ccr_reg |= cmd;
-
- return ccr_reg;
+ writeb(*val, addr);
}
-static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
- struct spi_flash *flash)
+static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
+ const struct spi_mem_op *op)
{
- unsigned int ccr_reg;
+ void (*fifo)(u8 *val, void __iomem *addr);
+ u32 len = op->data.nbytes, sr;
+ u8 *buf;
+ int ret;
- priv->command = flash->read_opcode | CMD_HAS_ADR | CMD_HAS_DATA
- | CMD_HAS_DUMMY;
- priv->dummycycles = flash->read_dummy;
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ fifo = _stm32_qspi_read_fifo;
+ buf = op->data.buf.in;
- ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);
+ } else {
+ fifo = _stm32_qspi_write_fifo;
+ buf = (u8 *)op->data.buf.out;
+ }
- _stm32_qspi_wait_for_not_busy(priv);
+ while (len--) {
+ ret = readl_poll_timeout(&priv->regs->sr, sr,
+ sr & STM32_QSPI_SR_FTF,
+ STM32_QSPI_FIFO_TIMEOUT_US);
+ if (ret) {
+ pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
+ return ret;
+ }
- writel(ccr_reg, &priv->regs->ccr);
+ fifo(buf++, &priv->regs->dr);
+ }
- priv->dummycycles = 0;
+ return 0;
}
-static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
+static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
+ const struct spi_mem_op *op)
{
- setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
-}
+ memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
+ op->data.nbytes);
-static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
- u32 length)
-{
- writel(length - 1, &priv->regs->dlr);
+ return 0;
}
-static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
+static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
+ const struct spi_mem_op *op,
+ u8 mode)
{
- writel(cr_reg, &priv->regs->ccr);
+ if (!op->data.nbytes)
+ return 0;
+
+ if (mode == STM32_QSPI_CCR_MEM_MAP)
+ return stm32_qspi_mm(priv, op);
- if (priv->command & CMD_HAS_ADR)
- writel(priv->address, &priv->regs->ar);
+ return _stm32_qspi_poll(priv, op);
}
-static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
- struct spi_flash *flash, unsigned int bitlen,
- const u8 *dout, u8 *din, unsigned long flags)
+static int _stm32_qspi_get_mode(u8 buswidth)
{
- unsigned int words = bitlen / 8;
- u32 ccr_reg;
- int i;
+ if (buswidth == 4)
+ return 3;
- if (flags & SPI_XFER_MMAP) {
- _stm32_qspi_enable_mmap(priv, flash);
- return 0;
- } else if (flags & SPI_XFER_MMAP_END) {
- _stm32_qspi_disable_mmap(priv);
- return 0;
- }
-
- if (bitlen == 0)
- return -1;
+ return buswidth;
+}
- if (bitlen % 8) {
- debug("spi_xfer: Non byte aligned SPI transfer\n");
- return -1;
- }
+static int stm32_qspi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
+ u32 cr, ccr, addr_max;
+ u8 mode = STM32_QSPI_CCR_IND_WRITE;
+ int timeout, ret;
+
+ debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
+ __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+ op->dummy.buswidth, op->data.buswidth,
+ op->addr.val, op->data.nbytes);
+
+ ret = _stm32_qspi_wait_for_not_busy(priv);
+ if (ret)
+ return ret;
- if (dout && din) {
- debug("spi_xfer: QSPI cannot have data in and data out set\n");
- return -1;
- }
+ addr_max = op->addr.val + op->data.nbytes + 1;
- if (!dout && (flags & SPI_XFER_BEGIN)) {
- debug("spi_xfer: QSPI transfer must begin with command\n");
- return -1;
+ if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
+ if (addr_max < priv->mm_size && op->addr.buswidth)
+ mode = STM32_QSPI_CCR_MEM_MAP;
+ else
+ mode = STM32_QSPI_CCR_IND_READ;
}
- if (dout) {
- if (flags & SPI_XFER_BEGIN) {
- /* data is command */
- priv->command = dout[0] | CMD_HAS_DATA;
- if (words >= 4) {
- /* address is here too */
- priv->address = (dout[1] << 16) |
- (dout[2] << 8) | dout[3];
- priv->command |= CMD_HAS_ADR;
- }
-
- if (words > 4) {
- /* rest is dummy bytes */
- priv->dummycycles = (words - 4) * 8;
- priv->command |= CMD_HAS_DUMMY;
- }
-
- if (flags & SPI_XFER_END) {
- /* command without data */
- priv->command &= ~(CMD_HAS_DATA);
- }
- }
-
- if (flags & SPI_XFER_END) {
- ccr_reg = _stm32_qspi_gen_ccr(priv,
- STM32_QSPI_CCR_IND_WRITE);
-
- _stm32_qspi_wait_for_not_busy(priv);
-
- if (priv->command & CMD_HAS_DATA)
- _stm32_qspi_set_xfer_length(priv, words);
-
- _stm32_qspi_start_xfer(priv, ccr_reg);
-
- debug("%s: write: ccr:0x%08x adr:0x%08x\n",
- __func__, priv->regs->ccr, priv->regs->ar);
-
- if (priv->command & CMD_HAS_DATA) {
- _stm32_qspi_wait_for_ftf(priv);
-
- debug("%s: words:%d data:", __func__, words);
+ if (op->data.nbytes)
+ writel(op->data.nbytes - 1, &priv->regs->dlr);
- i = 0;
- while (words > i) {
- writeb(dout[i], &priv->regs->dr);
- debug("%02x ", dout[i]);
- i++;
- }
- debug("\n");
+ ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
+ ccr |= op->cmd.opcode;
+ ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
+ << STM32_QSPI_CCR_IMODE_SHIFT);
- _stm32_qspi_wait_for_complete(priv);
- } else {
- _stm32_qspi_wait_for_not_busy(priv);
- }
- }
- } else if (din) {
- ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ);
+ if (op->addr.nbytes) {
+ ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
+ ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
+ << STM32_QSPI_CCR_ADMODE_SHIFT);
+ }
- _stm32_qspi_wait_for_not_busy(priv);
+ if (op->dummy.buswidth && op->dummy.nbytes)
+ ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
+ << STM32_QSPI_CCR_DCYC_SHIFT);
- _stm32_qspi_set_xfer_length(priv, words);
+ if (op->data.nbytes)
+ ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
+ << STM32_QSPI_CCR_DMODE_SHIFT);
- _stm32_qspi_start_xfer(priv, ccr_reg);
+ writel(ccr, &priv->regs->ccr);
- debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
- priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
+ if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
+ writel(op->addr.val, &priv->regs->ar);
- debug("%s: data:", __func__);
+ ret = _stm32_qspi_tx(priv, op, mode);
+ /*
+ * Abort in:
+ * -error case
+ * -read memory map: prefetching must be stopped if we read the last
+ * byte of device (device size - fifo size). like device size is not
+ * knows, the prefetching is always stop.
+ */
+ if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
+ goto abort;
- i = 0;
- while (words > i) {
- din[i] = readb(&priv->regs->dr);
- debug("%02x ", din[i]);
- i++;
- }
- debug("\n");
- }
+ /* Wait end of tx in indirect mode */
+ ret = _stm32_qspi_wait_cmd(priv, op);
+ if (ret)
+ goto abort;
return 0;
-}
-
-static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
-{
- struct resource res_regs, res_mem;
- struct stm32_qspi_platdata *plat = bus->platdata;
- int ret;
- ret = dev_read_resource_byname(bus, "qspi", &res_regs);
- if (ret) {
- debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
- return -ENOMEM;
- }
- ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
- if (ret) {
- debug("Error: can't get mmap base address(ret = %d)!\n", ret);
- return -ENOMEM;
- }
+abort:
+ setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
- plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
- STM32_QSPI_DEFAULT_SCK_FREQ);
+ /* Wait clear of abort bit by hw */
+ timeout = readl_poll_timeout(&priv->regs->cr, cr,
+ !(cr & STM32_QSPI_CR_ABORT),
+ STM32_ABT_TIMEOUT_US);
- plat->base = res_regs.start;
- plat->memory_map = res_mem.start;
+ writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
- debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
- __func__,
- plat->base,
- plat->memory_map,
- plat->max_hz
- );
+ if (ret || timeout)
+ pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
- return 0;
+ return ret;
}
static int stm32_qspi_probe(struct udevice *bus)
{
- struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
struct stm32_qspi_priv *priv = dev_get_priv(bus);
- struct dm_spi_bus *dm_spi_bus;
+ struct resource res;
struct clk clk;
struct reset_ctl reset_ctl;
int ret;
- dm_spi_bus = bus->uclass_priv;
+ ret = dev_read_resource_byname(bus, "qspi", &res);
+ if (ret) {
+ dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
+ return ret;
+ }
- dm_spi_bus->max_hz = plat->max_hz;
+ priv->regs = (struct stm32_qspi_regs *)res.start;
- priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
+ ret = dev_read_resource_byname(bus, "qspi_mm", &res);
+ if (ret) {
+ dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
+ return ret;
+ }
- priv->max_hz = plat->max_hz;
+ priv->mm_base = (void __iomem *)res.start;
+
+ priv->mm_size = resource_size(&res);
+ if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
+ return -EINVAL;
+
+ debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
+ __func__, priv->regs, priv->mm_base, priv->mm_size);
ret = clk_get_by_index(bus, 0, &clk);
if (ret < 0)
return ret;
ret = clk_enable(&clk);
-
if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
@@ -499,78 +380,68 @@ static int stm32_qspi_probe(struct udevice *bus)
reset_deassert(&reset_ctl);
}
+ priv->cs_used = -1;
+
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
- return 0;
-}
+ /* Set dcr fsize to max address */
+ setbits_le32(&priv->regs->dcr,
+ STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
-static int stm32_qspi_remove(struct udevice *bus)
-{
return 0;
}
static int stm32_qspi_claim_bus(struct udevice *dev)
{
- struct stm32_qspi_priv *priv;
- struct udevice *bus;
- struct spi_flash *flash;
- struct dm_spi_slave_platdata *slave_plat;
+ struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
- bus = dev->parent;
- priv = dev_get_priv(bus);
- flash = dev_get_uclass_priv(dev);
- slave_plat = dev_get_parent_platdata(dev);
-
- if (slave_plat->cs >= STM32_MAX_NORCHIP)
+ if (slave_plat->cs >= STM32_QSPI_MAX_CHIP)
return -ENODEV;
- _stm32_qspi_set_cs(priv, slave_plat->cs);
-
- _stm32_qspi_set_flash_size(priv, flash->size);
+ if (priv->cs_used != slave_plat->cs) {
+ struct stm32_qspi_flash *flash = &priv->flash[slave_plat->cs];
- _stm32_qspi_enable(priv);
+ priv->cs_used = slave_plat->cs;
- return 0;
-}
+ if (flash->initialized) {
+ /* Set the configuration: speed + cs */
+ writel(flash->cr, &priv->regs->cr);
+ writel(flash->dcr, &priv->regs->dcr);
+ } else {
+ /* Set chip select */
+ clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
+ priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
-static int stm32_qspi_release_bus(struct udevice *dev)
-{
- struct stm32_qspi_priv *priv;
- struct udevice *bus;
+ /* Save the configuration: speed + cs */
+ flash->cr = readl(&priv->regs->cr);
+ flash->dcr = readl(&priv->regs->dcr);
- bus = dev->parent;
- priv = dev_get_priv(bus);
+ flash->initialized = true;
+ }
+ }
- _stm32_qspi_disable(priv);
+ setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
return 0;
}
-static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int stm32_qspi_release_bus(struct udevice *dev)
{
- struct stm32_qspi_priv *priv;
- struct udevice *bus;
- struct spi_flash *flash;
+ struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
- bus = dev->parent;
- priv = dev_get_priv(bus);
- flash = dev_get_uclass_priv(dev);
+ clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
- return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
- (u8 *)din, flags);
+ return 0;
}
static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct stm32_qspi_platdata *plat = bus->platdata;
struct stm32_qspi_priv *priv = dev_get_priv(bus);
u32 qspi_clk = priv->clock_rate;
u32 prescaler = 255;
u32 csht;
-
- if (speed > plat->max_hz)
- speed = plat->max_hz;
+ int ret;
if (speed > 0) {
prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
@@ -583,7 +454,9 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
- _stm32_qspi_wait_for_not_busy(priv);
+ ret = _stm32_qspi_wait_for_not_busy(priv);
+ if (ret)
+ return ret;
clrsetbits_le32(&priv->regs->cr,
STM32_QSPI_CR_PRESCALER_MASK <<
@@ -603,8 +476,11 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
{
struct stm32_qspi_priv *priv = dev_get_priv(bus);
+ int ret;
- _stm32_qspi_wait_for_not_busy(priv);
+ ret = _stm32_qspi_wait_for_not_busy(priv);
+ if (ret)
+ return ret;
if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
@@ -616,20 +492,6 @@ static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
if (mode & SPI_CS_HIGH)
return -ENODEV;
- if (mode & SPI_RX_QUAD)
- priv->mode |= SPI_RX_QUAD;
- else if (mode & SPI_RX_DUAL)
- priv->mode |= SPI_RX_DUAL;
- else
- priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
-
- if (mode & SPI_TX_QUAD)
- priv->mode |= SPI_TX_QUAD;
- else if (mode & SPI_TX_DUAL)
- priv->mode |= SPI_TX_DUAL;
- else
- priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
-
debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
if (mode & SPI_RX_QUAD)
@@ -649,12 +511,16 @@ static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
return 0;
}
+static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
+ .exec_op = stm32_qspi_exec_op,
+};
+
static const struct dm_spi_ops stm32_qspi_ops = {
.claim_bus = stm32_qspi_claim_bus,
.release_bus = stm32_qspi_release_bus,
- .xfer = stm32_qspi_xfer,
.set_speed = stm32_qspi_set_speed,
.set_mode = stm32_qspi_set_mode,
+ .mem_ops = &stm32_qspi_mem_ops,
};
static const struct udevice_id stm32_qspi_ids[] = {
@@ -664,13 +530,10 @@ static const struct udevice_id stm32_qspi_ids[] = {
};
U_BOOT_DRIVER(stm32_qspi) = {
- .name = "stm32_qspi",
- .id = UCLASS_SPI,
+ .name = "stm32_qspi",
+ .id = UCLASS_SPI,
.of_match = stm32_qspi_ids,
- .ops = &stm32_qspi_ops,
- .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
+ .ops = &stm32_qspi_ops,
.priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
- .probe = stm32_qspi_probe,
- .remove = stm32_qspi_remove,
+ .probe = stm32_qspi_probe,
};
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 2dcce66de0..77fa17ee8a 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -10,6 +10,7 @@
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <spi-mem.h>
#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
@@ -40,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_INVAL (4 << 16)
#define QSPI_RD_QUAD (7 << 16)
/* device control */
-#define QSPI_DD(m, n) (m << (3 + n*8))
#define QSPI_CKPHA(n) (1 << (2 + n*8))
#define QSPI_CSPOL(n) (1 << (1 + n*8))
#define QSPI_CKPOL(n) (1 << (n*8))
@@ -52,22 +52,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define MM_SWITCH 0x01
#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xfffff8ff
-#define MMAP_START_ADDR_DRA 0x5c000000
-#define MMAP_START_ADDR_AM43x 0x30000000
-#define CORE_CTRL_IO 0x4a002558
-
-#define QSPI_CMD_READ (0x3 << 0)
-#define QSPI_CMD_READ_DUAL (0x6b << 0)
-#define QSPI_CMD_READ_QUAD (0x6c << 0)
-#define QSPI_CMD_READ_FAST (0x0b << 0)
-#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
-#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
-#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
+
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
-#define QSPI_CMD_WRITE (0x12 << 16)
-#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
+#define QSPI_SETUP0_ADDR_SHIFT (8)
+#define QSPI_SETUP0_DBITS_SHIFT (10)
/* ti qspi register set */
struct ti_qspi_regs {
@@ -98,13 +88,10 @@ struct ti_qspi_regs {
/* ti qspi priv */
struct ti_qspi_priv {
-#ifndef CONFIG_DM_SPI
- struct spi_slave slave;
-#else
void *memory_map;
+ size_t mmap_size;
uint max_hz;
u32 num_cs;
-#endif
struct ti_qspi_regs *base;
void *ctrl_mod_mmap;
ulong fclk;
@@ -113,8 +100,9 @@ struct ti_qspi_priv {
u32 dc;
};
-static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
+static int ti_qspi_set_speed(struct udevice *bus, uint hz)
{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
uint clk_div;
if (!hz)
@@ -133,6 +121,8 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
&priv->base->clk_ctrl);
/* enable SCLK and program the clk divider */
writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
+
+ return 0;
}
static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
@@ -142,38 +132,6 @@ static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
readl(&priv->base->cmd);
}
-static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
-{
- priv->dc = 0;
- if (mode & SPI_CPHA)
- priv->dc |= QSPI_CKPHA(0);
- if (mode & SPI_CPOL)
- priv->dc |= QSPI_CKPOL(0);
- if (mode & SPI_CS_HIGH)
- priv->dc |= QSPI_CSPOL(0);
-
- return 0;
-}
-
-static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
-{
- writel(priv->dc, &priv->base->dc);
- writel(0, &priv->base->cmd);
- writel(0, &priv->base->data);
-
- priv->dc <<= cs * 8;
- writel(priv->dc, &priv->base->dc);
-
- return 0;
-}
-
-static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
-{
- writel(0, &priv->base->dc);
- writel(0, &priv->base->cmd);
- writel(0, &priv->base->data);
-}
-
static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
u32 val;
@@ -186,27 +144,25 @@ static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
writel(val, ctrl_mod_mmap);
}
-static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags,
- u32 cs)
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
uint words = bitlen >> 3; /* fixed 8-bit word length */
const uchar *txp = dout;
uchar *rxp = din;
uint status;
int timeout;
+ unsigned int cs = slave->cs;
- /* Setup mmap flags */
- if (flags & SPI_XFER_MMAP) {
- writel(MM_SWITCH, &priv->base->memswitch);
- if (priv->ctrl_mod_mmap)
- ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
- return 0;
- } else if (flags & SPI_XFER_MMAP_END) {
- writel(~MM_SWITCH, &priv->base->memswitch);
- if (priv->ctrl_mod_mmap)
- ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
- return 0;
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
}
if (bitlen == 0)
@@ -294,9 +250,9 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
}
/* TODO: control from sf layer to here through dm-spi */
-#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
-void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
{
+#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
unsigned int addr = (unsigned int) (data);
unsigned int edma_slot_num = 1;
@@ -311,187 +267,85 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
/* disable edma3 clocks */
disable_edma3_clocks();
-
- *((unsigned int *)offset) += len;
-}
-#endif
-
-#ifndef CONFIG_DM_SPI
-
-static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
-{
- return container_of(slave, struct ti_qspi_priv, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* CS handled in xfer */
- return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
- ti_qspi_cs_deactivate(priv);
-}
-
-void spi_init(void)
-{
- /* nothing to do */
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
-{
- u32 memval = 0;
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
- struct spi_slave *slave = &priv->slave;
- memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_8_BITS |
- QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS);
- slave->mode |= SPI_RX_QUAD;
#else
- memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
- QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS;
+ memcpy_fromio(data, offset, len);
#endif
- writel(memval, &priv->base->setup0);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct ti_qspi_priv *priv;
-
-#ifdef CONFIG_AM43XX
- gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
- gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
- priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
- if (!priv) {
- printf("SPI_error: Fail to allocate ti_qspi_priv\n");
- return NULL;
- }
-
- priv->base = (struct ti_qspi_regs *)QSPI_BASE;
- priv->mode = mode;
-#if defined(CONFIG_DRA7XX)
- priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
- priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
- priv->fclk = QSPI_DRA7XX_FCLK;
-#else
- priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
- priv->fclk = QSPI_FCLK;
-#endif
-
- ti_spi_set_speed(priv, max_hz);
-
-#ifdef CONFIG_TI_SPI_MMAP
- ti_spi_setup_spi_register(priv);
-#endif
-
- return &priv->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
- free(priv);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
- __ti_qspi_set_mode(priv, priv->mode);
- return __ti_qspi_claim_bus(priv, priv->slave.cs);
-}
-void spi_release_bus(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
- __ti_qspi_release_bus(priv);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
- debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
- priv->slave.bus, priv->slave.cs, bitlen, flags);
- return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
+ *((unsigned int *)offset) += len;
}
-#else /* CONFIG_DM_SPI */
-
-static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
- struct spi_slave *slave,
- bool enable)
+static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
+ u8 data_nbits, u8 addr_width,
+ u8 dummy_bytes)
{
- u32 memval;
- u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
-
- if (!enable) {
- writel(0, &priv->base->setup0);
- return;
- }
-
- memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
+ u32 memval = opcode;
- switch (mode) {
- case SPI_RX_QUAD:
- memval |= QSPI_CMD_READ_QUAD;
- memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ switch (data_nbits) {
+ case 4:
memval |= QSPI_SETUP0_READ_QUAD;
- slave->mode |= SPI_RX_QUAD;
break;
- case SPI_RX_DUAL:
- memval |= QSPI_CMD_READ_DUAL;
- memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ case 2:
memval |= QSPI_SETUP0_READ_DUAL;
break;
default:
- memval |= QSPI_CMD_READ;
- memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
memval |= QSPI_SETUP0_READ_NORMAL;
break;
}
+ memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
+ dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
+
writel(memval, &priv->base->setup0);
}
-
-static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
+static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
- ti_spi_set_speed(priv, max_hz);
+ priv->dc = 0;
+ if (mode & SPI_CPHA)
+ priv->dc |= QSPI_CKPHA(0);
+ if (mode & SPI_CPOL)
+ priv->dc |= QSPI_CKPOL(0);
+ if (mode & SPI_CS_HIGH)
+ priv->dc |= QSPI_CSPOL(0);
return 0;
}
-static int ti_qspi_set_mode(struct udevice *bus, uint mode)
+static int ti_qspi_exec_mem_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
- struct ti_qspi_priv *priv = dev_get_priv(bus);
- return __ti_qspi_set_mode(priv, mode);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = slave->dev->parent;
+ priv = dev_get_priv(bus);
+ u32 from = 0;
+ int ret = 0;
+
+ /* Only optimize read path. */
+ if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
+ !op->addr.nbytes || op->addr.nbytes > 4)
+ return -ENOTSUPP;
+
+ /* Address exceeds MMIO window size, fall back to regular mode. */
+ from = op->addr.val;
+ if (from + op->data.nbytes > priv->mmap_size)
+ return -ENOTSUPP;
+
+ ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
+ op->addr.nbytes, op->dummy.nbytes);
+
+ ti_qspi_copy_mmap((void *)op->data.buf.in,
+ (void *)priv->memory_map + from, op->data.nbytes);
+
+ return ret;
}
static int ti_qspi_claim_bus(struct udevice *dev)
{
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
- struct spi_slave *slave = dev_get_parent_priv(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
@@ -503,42 +357,41 @@ static int ti_qspi_claim_bus(struct udevice *dev)
return -EINVAL;
}
- __ti_qspi_setup_memorymap(priv, slave, true);
-
- return __ti_qspi_claim_bus(priv, slave_plat->cs);
-}
-
-static int ti_qspi_release_bus(struct udevice *dev)
-{
- struct spi_slave *slave = dev_get_parent_priv(dev);
- struct ti_qspi_priv *priv;
- struct udevice *bus;
+ writel(MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
+ slave_plat->cs, true);
- bus = dev->parent;
- priv = dev_get_priv(bus);
+ writel(priv->dc, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
- __ti_qspi_setup_memorymap(priv, slave, false);
- __ti_qspi_release_bus(priv);
+ priv->dc <<= slave_plat->cs * 8;
+ writel(priv->dc, &priv->base->dc);
return 0;
}
-static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int ti_qspi_release_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
bus = dev->parent;
priv = dev_get_priv(bus);
- if (slave->cs > priv->num_cs) {
- debug("invalid qspi chip select\n");
- return -EINVAL;
- }
+ writel(~MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
+ slave_plat->cs, false);
- return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+ writel(0, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
+ writel(0, &priv->base->setup0);
+
+ return 0;
}
static int ti_qspi_probe(struct udevice *bus)
@@ -594,12 +447,15 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
+ fdt_addr_t mmap_addr;
+ fdt_addr_t mmap_size;
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
priv->base = map_physmem(devfdt_get_addr(bus),
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
- priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
- MAP_NOCACHE);
+ mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
+ priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
+ priv->mmap_size = mmap_size;
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
@@ -614,15 +470,9 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
return 0;
}
-static int ti_qspi_child_pre_probe(struct udevice *dev)
-{
- struct spi_slave *slave = dev_get_parent_priv(dev);
- struct udevice *bus = dev_get_parent(dev);
- struct ti_qspi_priv *priv = dev_get_priv(bus);
-
- slave->memory_map = priv->memory_map;
- return 0;
-}
+static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
+ .exec_op = ti_qspi_exec_mem_op,
+};
static const struct dm_spi_ops ti_qspi_ops = {
.claim_bus = ti_qspi_claim_bus,
@@ -630,6 +480,7 @@ static const struct dm_spi_ops ti_qspi_ops = {
.xfer = ti_qspi_xfer,
.set_speed = ti_qspi_set_speed,
.set_mode = ti_qspi_set_mode,
+ .mem_ops = &ti_qspi_mem_ops,
};
static const struct udevice_id ti_qspi_ids[] = {
@@ -646,6 +497,4 @@ U_BOOT_DRIVER(ti_qspi) = {
.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
.probe = ti_qspi_probe,
- .child_pre_probe = ti_qspi_child_pre_probe,
};
-#endif /* CONFIG_DM_SPI */
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index da9413c066..04ea42cbcc 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -267,7 +267,7 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
- } else if (reqhz < GQSPI_FREQ_100MHZ) {
+ } else if (reqhz <= GQSPI_FREQ_100MHZ) {
zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
@@ -277,7 +277,7 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
| (GQSPI_DATA_DLY_ADJ_VALUE <<
GQSPI_DATA_DLY_ADJ_SHIFT));
- } else if (reqhz < GQSPI_FREQ_150MHZ) {
+ } else if (reqhz <= GQSPI_FREQ_150MHZ) {
lpbkdlyadj = readl(&regs->lpbkdly);
lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
GQSPI_LPBK_DLY_ADJ_DLY_0);
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-28 11:17:03 +0000