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-rw-r--r--drivers/ram/aspeed/Kconfig61
-rw-r--r--drivers/ram/aspeed/Makefile3
-rw-r--r--drivers/ram/aspeed/sdram_ast2600.c1061
-rw-r--r--drivers/ram/k3-j721e/lpddr4.c14
-rw-r--r--drivers/ram/k3-j721e/lpddr4_private.h20
-rw-r--r--drivers/ram/stm32_sdram.c10
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_ddr.c36
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_interactive.c4
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_ram.c38
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_tests.c19
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_tuning.c124
11 files changed, 1265 insertions, 125 deletions
diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig
index 020c913188..049b9dc249 100644
--- a/drivers/ram/aspeed/Kconfig
+++ b/drivers/ram/aspeed/Kconfig
@@ -1,4 +1,5 @@
if RAM || SPL_RAM
+
config ASPEED_DDR4_DUALX8
bool "Enable Dual X8 DDR4 die"
depends on DM && OF_CONTROL && ARCH_ASPEED
@@ -7,4 +8,62 @@ config ASPEED_DDR4_DUALX8
Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram
controller needs to know if the memory chip mounted on the board is dual
x8 die or not. Or it may get the wrong size of the memory space.
-endif
+
+if ASPEED_AST2600
+
+choice
+ prompt "DDR4 target date rate"
+ default ASPEED_DDR4_1600
+
+config ASPEED_DDR4_400
+ bool "DDR4 targets at 400Mbps"
+ depends on DM && OF_CONTROL && ARCH_ASPEED
+ help
+ select DDR4 target data rate at 400M
+
+config ASPEED_DDR4_800
+ bool "DDR4 targets at 800Mbps"
+ depends on DM && OF_CONTROL && ARCH_ASPEED
+ help
+ select DDR4 target data rate at 800M
+
+config ASPEED_DDR4_1333
+ bool "DDR4 targets at 1333Mbps"
+ depends on DM && OF_CONTROL && ARCH_ASPEED
+ help
+ select DDR4 target data rate at 1333M
+
+config ASPEED_DDR4_1600
+ bool "DDR4 targets at 1600Mbps"
+ depends on DM && OF_CONTROL && ARCH_ASPEED
+ help
+ select DDR4 target data rate at 1600M
+endchoice
+
+config ASPEED_BYPASS_SELFTEST
+ bool "bypass self test during DRAM initialization"
+ default n
+ help
+ Say Y here to bypass DRAM self test to speed up the boot time
+
+config ASPEED_ECC
+ bool "aspeed SDRAM error correcting code"
+ depends on DM && OF_CONTROL && ARCH_ASPEED
+ default n
+ help
+ enable SDRAM ECC function
+
+if ASPEED_ECC
+config ASPEED_ECC_SIZE
+ int "ECC size: 0=driver auto-caluated"
+ depends on ASPEED_ECC
+ default 0
+ help
+ SDRAM size with the error correcting code enabled. The unit is
+ in Megabytes. Noted that only the 8/9 of the configured size
+ can be used by the system. The remaining 1/9 will be used by
+ the ECC engine. If the size is set to 0, the sdram driver will
+ calculate the SDRAM size and set the whole range be ECC enabled.
+endif # end of ASPEED_ECC
+endif # end of ASPEED_AST2600
+endif # end of RAM || SPL_RAM
diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile
index af604f8a4b..7ac10af1c2 100644
--- a/drivers/ram/aspeed/Makefile
+++ b/drivers/ram/aspeed/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o \ No newline at end of file
+obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
+obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
new file mode 100644
index 0000000000..fd4235225a
--- /dev/null
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -0,0 +1,1061 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <ram.h>
+#include <regmap.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2600.h>
+#include <asm/arch/sdram_ast2600.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <dt-bindings/clock/ast2600-clock.h>
+
+#define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea
+#define DDR_PHY_TBL_END 0xaeededed
+
+#if defined(CONFIG_ASPEED_DDR4_800)
+u32 ast2600_sdramphy_config[165] = {
+ 0x1e6e0100, // start address
+ 0x00000000, // phyr000
+ 0x0c002062, // phyr004
+ 0x1a7a0063, // phyr008
+ 0x5a7a0063, // phyr00c
+ 0x1a7a0063, // phyr010
+ 0x1a7a0063, // phyr014
+ 0x20000000, // phyr018
+ 0x20000000, // phyr01c
+ 0x20000000, // phyr020
+ 0x20000000, // phyr024
+ 0x00000008, // phyr028
+ 0x00000000, // phyr02c
+ 0x00077600, // phyr030
+ 0x00000000, // phyr034
+ 0x00000000, // phyr038
+ 0x20000000, // phyr03c
+ 0x50506000, // phyr040
+ 0x50505050, // phyr044
+ 0x00002f07, // phyr048
+ 0x00003080, // phyr04c
+ 0x04000000, // phyr050
+ 0x00000200, // phyr054
+ 0x03140201, // phyr058
+ 0x04800000, // phyr05c
+ 0x0800044e, // phyr060
+ 0x00000000, // phyr064
+ 0x00180008, // phyr068
+ 0x00e00400, // phyr06c
+ 0x00140206, // phyr070
+ 0x1d4c0000, // phyr074
+ 0x493e0107, // phyr078
+ 0x08060404, // phyr07c
+ 0x90000a00, // phyr080
+ 0x06420618, // phyr084
+ 0x00001002, // phyr088
+ 0x05701016, // phyr08c
+ 0x10000000, // phyr090
+ 0xaeeddeea, // change address
+ 0x1e6e019c, // new address
+ 0x20202020, // phyr09c
+ 0x20202020, // phyr0a0
+ 0x00002020, // phyr0a4
+ 0x00002020, // phyr0a8
+ 0x00000001, // phyr0ac
+ 0xaeeddeea, // change address
+ 0x1e6e01cc, // new address
+ 0x01010101, // phyr0cc
+ 0x01010101, // phyr0d0
+ 0x80808080, // phyr0d4
+ 0x80808080, // phyr0d8
+ 0xaeeddeea, // change address
+ 0x1e6e0288, // new address
+ 0x80808080, // phyr188
+ 0x80808080, // phyr18c
+ 0x80808080, // phyr190
+ 0x80808080, // phyr194
+ 0xaeeddeea, // change address
+ 0x1e6e02f8, // new address
+ 0x90909090, // phyr1f8
+ 0x88888888, // phyr1fc
+ 0xaeeddeea, // change address
+ 0x1e6e0300, // new address
+ 0x00000000, // phyr200
+ 0xaeeddeea, // change address
+ 0x1e6e0194, // new address
+ 0x80118260, // phyr094
+ 0xaeeddeea, // change address
+ 0x1e6e019c, // new address
+ 0x20202020, // phyr09c
+ 0x20202020, // phyr0a0
+ 0x00002020, // phyr0a4
+ 0x80000000, // phyr0a8
+ 0x00000001, // phyr0ac
+ 0xaeeddeea, // change address
+ 0x1e6e0318, // new address
+ 0x09222719, // phyr218
+ 0x00aa4403, // phyr21c
+ 0xaeeddeea, // change address
+ 0x1e6e0198, // new address
+ 0x08060000, // phyr098
+ 0xaeeddeea, // change address
+ 0x1e6e01b0, // new address
+ 0x00000000, // phyr0b0
+ 0x00000000, // phyr0b4
+ 0x00000000, // phyr0b8
+ 0x00000000, // phyr0bc
+ 0x00000000, // phyr0c0
+ 0x00000000, // phyr0c4
+ 0x000aff2c, // phyr0c8
+ 0xaeeddeea, // change address
+ 0x1e6e01dc, // new address
+ 0x00080000, // phyr0dc
+ 0x00000000, // phyr0e0
+ 0xaa55aa55, // phyr0e4
+ 0x55aa55aa, // phyr0e8
+ 0xaaaa5555, // phyr0ec
+ 0x5555aaaa, // phyr0f0
+ 0xaa55aa55, // phyr0f4
+ 0x55aa55aa, // phyr0f8
+ 0xaaaa5555, // phyr0fc
+ 0x5555aaaa, // phyr100
+ 0xaa55aa55, // phyr104
+ 0x55aa55aa, // phyr108
+ 0xaaaa5555, // phyr10c
+ 0x5555aaaa, // phyr110
+ 0xaa55aa55, // phyr114
+ 0x55aa55aa, // phyr118
+ 0xaaaa5555, // phyr11c
+ 0x5555aaaa, // phyr120
+ 0x20202020, // phyr124
+ 0x20202020, // phyr128
+ 0x20202020, // phyr12c
+ 0x20202020, // phyr130
+ 0x20202020, // phyr134
+ 0x20202020, // phyr138
+ 0x20202020, // phyr13c
+ 0x20202020, // phyr140
+ 0x20202020, // phyr144
+ 0x20202020, // phyr148
+ 0x20202020, // phyr14c
+ 0x20202020, // phyr150
+ 0x20202020, // phyr154
+ 0x20202020, // phyr158
+ 0x20202020, // phyr15c
+ 0x20202020, // phyr160
+ 0x20202020, // phyr164
+ 0x20202020, // phyr168
+ 0x20202020, // phyr16c
+ 0x20202020, // phyr170
+ 0xaeeddeea, // change address
+ 0x1e6e0298, // new address
+ 0x20200800, // phyr198
+ 0x20202020, // phyr19c
+ 0x20202020, // phyr1a0
+ 0x20202020, // phyr1a4
+ 0x20202020, // phyr1a8
+ 0x20202020, // phyr1ac
+ 0x20202020, // phyr1b0
+ 0x20202020, // phyr1b4
+ 0x20202020, // phyr1b8
+ 0x20202020, // phyr1bc
+ 0x20202020, // phyr1c0
+ 0x20202020, // phyr1c4
+ 0x20202020, // phyr1c8
+ 0x20202020, // phyr1cc
+ 0x20202020, // phyr1d0
+ 0x20202020, // phyr1d4
+ 0x20202020, // phyr1d8
+ 0x20202020, // phyr1dc
+ 0x20202020, // phyr1e0
+ 0x20202020, // phyr1e4
+ 0x00002020, // phyr1e8
+ 0xaeeddeea, // change address
+ 0x1e6e0304, // new address
+ 0x00000800, // phyr204
+ 0xaeeddeea, // change address
+ 0x1e6e027c, // new address
+ 0x4e400000, // phyr17c
+ 0x59595959, // phyr180
+ 0x40404040, // phyr184
+ 0xaeeddeea, // change address
+ 0x1e6e02f4, // new address
+ 0x00000059, // phyr1f4
+ 0xaeededed, // end
+};
+#else
+u32 ast2600_sdramphy_config[165] = {
+ 0x1e6e0100, // start address
+ 0x00000000, // phyr000
+ 0x0c002062, // phyr004
+ 0x1a7a0063, // phyr008
+ 0x5a7a0063, // phyr00c
+ 0x1a7a0063, // phyr010
+ 0x1a7a0063, // phyr014
+ 0x20000000, // phyr018
+ 0x20000000, // phyr01c
+ 0x20000000, // phyr020
+ 0x20000000, // phyr024
+ 0x00000008, // phyr028
+ 0x00000000, // phyr02c
+ 0x00077600, // phyr030
+ 0x00000000, // phyr034
+ 0x00000000, // phyr038
+ 0x20000000, // phyr03c
+ 0x50506000, // phyr040
+ 0x50505050, // phyr044
+ 0x00002f07, // phyr048
+ 0x00003080, // phyr04c
+ 0x04000000, // phyr050
+ 0x00000200, // phyr054
+ 0x03140501, // phyr058-rtt:40
+ 0x04800000, // phyr05c
+ 0x0800044e, // phyr060
+ 0x00000000, // phyr064
+ 0x00180008, // phyr068
+ 0x00e00400, // phyr06c
+ 0x00140206, // phyr070
+ 0x1d4c0000, // phyr074
+ 0x493e0107, // phyr078
+ 0x08060404, // phyr07c
+ 0x90000a00, // phyr080
+ 0x06420c30, // phyr084
+ 0x00001002, // phyr088
+ 0x05701016, // phyr08c
+ 0x10000000, // phyr090
+ 0xaeeddeea, // change address
+ 0x1e6e019c, // new address
+ 0x20202020, // phyr09c
+ 0x20202020, // phyr0a0
+ 0x00002020, // phyr0a4
+ 0x00002020, // phyr0a8
+ 0x00000001, // phyr0ac
+ 0xaeeddeea, // change address
+ 0x1e6e01cc, // new address
+ 0x01010101, // phyr0cc
+ 0x01010101, // phyr0d0
+ 0x80808080, // phyr0d4
+ 0x80808080, // phyr0d8
+ 0xaeeddeea, // change address
+ 0x1e6e0288, // new address
+ 0x80808080, // phyr188
+ 0x80808080, // phyr18c
+ 0x80808080, // phyr190
+ 0x80808080, // phyr194
+ 0xaeeddeea, // change address
+ 0x1e6e02f8, // new address
+ 0x90909090, // phyr1f8
+ 0x88888888, // phyr1fc
+ 0xaeeddeea, // change address
+ 0x1e6e0300, // new address
+ 0x00000000, // phyr200
+ 0xaeeddeea, // change address
+ 0x1e6e0194, // new address
+ 0x801112e0, // phyr094 - bit12=1,15=0,- write window is ok
+ 0xaeeddeea, // change address
+ 0x1e6e019c, // new address
+ 0x20202020, // phyr09c
+ 0x20202020, // phyr0a0
+ 0x00002020, // phyr0a4
+ 0x80000000, // phyr0a8
+ 0x00000001, // phyr0ac
+ 0xaeeddeea, // change address
+ 0x1e6e0318, // new address
+ 0x09222719, // phyr218
+ 0x00aa4403, // phyr21c
+ 0xaeeddeea, // change address
+ 0x1e6e0198, // new address
+ 0x08060000, // phyr098
+ 0xaeeddeea, // change address
+ 0x1e6e01b0, // new address
+ 0x00000000, // phyr0b0
+ 0x00000000, // phyr0b4
+ 0x00000000, // phyr0b8
+ 0x00000000, // phyr0bc
+ 0x00000000, // phyr0c0 - ori
+ 0x00000000, // phyr0c4
+ 0x000aff2c, // phyr0c8
+ 0xaeeddeea, // change address
+ 0x1e6e01dc, // new address
+ 0x00080000, // phyr0dc
+ 0x00000000, // phyr0e0
+ 0xaa55aa55, // phyr0e4
+ 0x55aa55aa, // phyr0e8
+ 0xaaaa5555, // phyr0ec
+ 0x5555aaaa, // phyr0f0
+ 0xaa55aa55, // phyr0f4
+ 0x55aa55aa, // phyr0f8
+ 0xaaaa5555, // phyr0fc
+ 0x5555aaaa, // phyr100
+ 0xaa55aa55, // phyr104
+ 0x55aa55aa, // phyr108
+ 0xaaaa5555, // phyr10c
+ 0x5555aaaa, // phyr110
+ 0xaa55aa55, // phyr114
+ 0x55aa55aa, // phyr118
+ 0xaaaa5555, // phyr11c
+ 0x5555aaaa, // phyr120
+ 0x20202020, // phyr124
+ 0x20202020, // phyr128
+ 0x20202020, // phyr12c
+ 0x20202020, // phyr130
+ 0x20202020, // phyr134
+ 0x20202020, // phyr138
+ 0x20202020, // phyr13c
+ 0x20202020, // phyr140
+ 0x20202020, // phyr144
+ 0x20202020, // phyr148
+ 0x20202020, // phyr14c
+ 0x20202020, // phyr150
+ 0x20202020, // phyr154
+ 0x20202020, // phyr158
+ 0x20202020, // phyr15c
+ 0x20202020, // phyr160
+ 0x20202020, // phyr164
+ 0x20202020, // phyr168
+ 0x20202020, // phyr16c
+ 0x20202020, // phyr170
+ 0xaeeddeea, // change address
+ 0x1e6e0298, // new address
+ 0x20200800, // phyr198
+ 0x20202020, // phyr19c
+ 0x20202020, // phyr1a0
+ 0x20202020, // phyr1a4
+ 0x20202020, // phyr1a8
+ 0x20202020, // phyr1ac
+ 0x20202020, // phyr1b0
+ 0x20202020, // phyr1b4
+ 0x20202020, // phyr1b8
+ 0x20202020, // phyr1bc
+ 0x20202020, // phyr1c0
+ 0x20202020, // phyr1c4
+ 0x20202020, // phyr1c8
+ 0x20202020, // phyr1cc
+ 0x20202020, // phyr1d0
+ 0x20202020, // phyr1d4
+ 0x20202020, // phyr1d8
+ 0x20202020, // phyr1dc
+ 0x20202020, // phyr1e0
+ 0x20202020, // phyr1e4
+ 0x00002020, // phyr1e8
+ 0xaeeddeea, // change address
+ 0x1e6e0304, // new address
+ 0x00000800, // phyr204
+ 0xaeeddeea, // change address
+ 0x1e6e027c, // new address
+ 0x4e400000, // phyr17c
+ 0x59595959, // phyr180
+ 0x40404040, // phyr184
+ 0xaeeddeea, // change address
+ 0x1e6e02f4, // new address
+ 0x00000059, // phyr1f4
+ 0xaeededed, // end
+};
+#endif
+
+/* MPLL configuration */
+#define SCU_MPLL_FREQ_400M 0x0008405F
+#define SCU_MPLL_EXT_400M 0x0000002F
+#define SCU_MPLL_FREQ_333M 0x00488299
+#define SCU_MPLL_EXT_333M 0x0000014C
+#define SCU_MPLL_FREQ_200M 0x0078007F
+#define SCU_MPLL_EXT_200M 0x0000003F
+#define SCU_MPLL_FREQ_100M 0x0078003F
+#define SCU_MPLL_EXT_100M 0x0000001F
+
+#if defined(CONFIG_ASPEED_DDR4_1600)
+#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M
+#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M
+#elif defined(CONFIG_ASPEED_DDR4_1333)
+#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M
+#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M
+#elif defined(CONFIG_ASPEED_DDR4_800)
+#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M
+#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M
+#elif defined(CONFIG_ASPEED_DDR4_400)
+#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M
+#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M
+#else
+#error "undefined DDR4 target rate\n"
+#endif
+
+/*
+ * AC timing and SDRAM mode register setting
+ * for real chip are derived from the model GDDR4-1600
+ */
+#define DDR4_MR01_MODE 0x03010510
+#define DDR4_MR23_MODE 0x00000000
+#define DDR4_MR45_MODE 0x04000000
+#define DDR4_MR6_MODE 0x00000400
+#define DDR4_TRFC_1600 0x467299f1
+#define DDR4_TRFC_1333 0x3a5f80c9
+#define DDR4_TRFC_800 0x23394c78
+#define DDR4_TRFC_400 0x111c263c
+
+#if defined(CONFIG_ASPEED_DDR4_1600)
+#define DDR4_TRFC DDR4_TRFC_1600
+#define DDR4_PHY_TRAIN_TRFC 0xc30
+#elif defined(CONFIG_ASPEED_DDR4_1333)
+#define DDR4_TRFC DDR4_TRFC_1333
+#define DDR4_PHY_TRAIN_TRFC 0xa25
+#elif defined(CONFIG_ASPEED_DDR4_800)
+#define DDR4_TRFC DDR4_TRFC_800
+#define DDR4_PHY_TRAIN_TRFC 0x618
+#elif defined(CONFIG_ASPEED_DDR4_400)
+#define DDR4_TRFC DDR4_TRFC_400
+#define DDR4_PHY_TRAIN_TRFC 0x30c
+#else
+#error "undefined tRFC setting"
+#endif
+
+/* supported SDRAM size */
+#define SDRAM_SIZE_1KB (1024U)
+#define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
+#define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB)
+#define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 ddr4_ac_timing[4] = {
+ 0x040e0307, 0x0f4711f1, 0x0e060304, 0x00001240 };
+static const u32 ddr_max_grant_params[4] = {
+ 0x44444444, 0x44444444, 0x44444444, 0x44444444 };
+
+struct dram_info {
+ struct ram_info info;
+ struct clk ddr_clk;
+ struct ast2600_sdrammc_regs *regs;
+ struct ast2600_scu *scu;
+ struct ast2600_ddr_phy *phy;
+ void __iomem *phy_setting;
+ void __iomem *phy_status;
+ ulong clock_rate;
+};
+
+static void ast2600_sdramphy_kick_training(struct dram_info *info)
+{
+ u32 data;
+ struct ast2600_sdrammc_regs *regs = info->regs;
+
+ writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]);
+ udelay(5);
+ writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
+ udelay(1000);
+
+ while (1) {
+ data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
+ if (~data)
+ break;
+ }
+}
+
+/**
+ * @brief load DDR-PHY configurations table to the PHY registers
+ * @param[in] p_tbl - pointer to the configuration table
+ * @param[in] info - pointer to the DRAM info struct
+ *
+ * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
+ * system: one is in the SDRAM MC (memory controller) which is used in run
+ * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
+ * training.
+ */
+static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
+{
+ u32 reg_base = (u32)info->phy_setting;
+ u32 addr = p_tbl[0];
+ u32 data;
+ int i = 1;
+
+ writel(0, &info->regs->phy_ctrl[0]);
+ udelay(10);
+
+ while (1) {
+ if (addr < reg_base) {
+ debug("invalid DDR-PHY addr: 0x%08x\n", addr);
+ break;
+ }
+ data = p_tbl[i++];
+
+ if (data == DDR_PHY_TBL_END) {
+ break;
+ } else if (data == DDR_PHY_TBL_CHG_ADDR) {
+ addr = p_tbl[i++];
+ } else {
+ writel(data, addr);
+ addr += 4;
+ }
+ }
+
+ data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
+ data |= DDR4_PHY_TRAIN_TRFC;
+ writel(data, info->phy_setting + 0x84);
+}
+
+static int ast2600_sdramphy_check_status(struct dram_info *info)
+{
+ u32 value, tmp;
+ u32 reg_base = (u32)info->phy_status;
+ int need_retrain = 0;
+
+ debug("\nSDRAM PHY training report:\n");
+
+ /* training status */
+ value = readl(reg_base + 0x00);
+ debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
+
+ if (value & BIT(3))
+ debug("\tinitial PVT calibration fail\n");
+
+ if (value & BIT(5))
+ debug("\truntime calibration fail\n");
+
+ /* PU & PD */
+ value = readl(reg_base + 0x30);
+ debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
+ debug(" PU = 0x%02x\n", value & 0xff);
+ debug(" PD = 0x%02x\n", (value >> 16) & 0xff);
+
+ /* read eye window */
+ value = readl(reg_base + 0x68);
+ if (0 == (value & GENMASK(7, 0)))
+ need_retrain = 1;
+
+ debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
+ debug(" rising edge of read data eye training pass window\n");
+ tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
+ debug(" B0:%d%%\n", tmp);
+ tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
+ debug(" B1:%d%%\n", tmp);
+
+ value = readl(reg_base + 0xC8);
+ debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
+ debug(" falling edge of read data eye training pass window\n");
+ tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
+ debug(" B0:%d%%\n", tmp);
+ tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
+ debug(" B1:%d%%\n", tmp);
+
+ /* write eye window */
+ value = readl(reg_base + 0x7c);
+ if (0 == (value & GENMASK(7, 0)))
+ need_retrain = 1;
+
+ debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
+ debug(" rising edge of write data eye training pass window\n");
+ tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
+ debug(" B0:%d%%\n", tmp);
+ tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
+ debug(" B1:%d%%\n", tmp);
+
+ /* read Vref training result */
+ value = readl(reg_base + 0x88);
+ debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
+ debug(" read Vref training result\n");
+ tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127;
+ debug(" B0:%d%%\n", tmp);
+ tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127;
+ debug(" B1:%d%%\n", tmp);
+
+ /* write Vref training result */
+ value = readl(reg_base + 0x90);
+ debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
+
+ /* gate train */
+ value = readl(reg_base + 0x50);
+ if ((0 == (value & GENMASK(15, 0))) ||
+ (0 == (value & GENMASK(31, 16)))) {
+ need_retrain = 1;
+ }
+
+ debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
+
+ return need_retrain;
+}
+
+#ifndef CONFIG_ASPEED_BYPASS_SELFTEST
+#define MC_TEST_PATTERN_N 8
+static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
+ 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
+ 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 };
+
+#define TIMEOUT_DRAM 5000000
+int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode)
+{
+ unsigned int data;
+ unsigned int timeout = 0;
+ struct ast2600_sdrammc_regs *regs = info->regs;
+
+ writel(0, &regs->ecc_test_ctrl);
+
+ if (mode == 0)
+ writel(0x00000085 | (datagen << 3), &regs->ecc_test_ctrl);
+ else
+ writel(0x000000C1 | (datagen << 3), &regs->ecc_test_ctrl);
+
+ do {
+ data = readl(&regs->ecc_test_ctrl) & GENMASK(13, 12);
+
+ if (data & BIT(13))
+ return 0;
+
+ if (++timeout > TIMEOUT_DRAM) {
+ debug("Timeout!!\n");
+ writel(0, &regs->ecc_test_ctrl);
+ return -1;
+ }
+ } while (!data);
+
+ writel(0, &regs->ecc_test_ctrl);
+
+ return 0;
+}
+
+int ast2600_sdrammc_cbr_test(struct dram_info *info)
+{
+ u32 i;
+ struct ast2600_sdrammc_regs *regs = info->regs;
+
+ clrsetbits_le32(&regs->test_addr, GENMASK(30, 4), 0x7ffff0);
+
+ /* single */
+ for (i = 0; i < 8; i++)
+ if (ast2600_sdrammc_dg_test(info, i, 0))
+ return -1;
+
+ /* burst */
+ for (i = 0; i < 8; i++)
+ if (ast2600_sdrammc_dg_test(info, i, i))
+ return -1;
+
+ return 0;
+}
+
+static int ast2600_sdrammc_test(struct dram_info *info)
+{
+ struct ast2600_sdrammc_regs *regs = info->regs;
+
+ u32 pass_cnt = 0;
+ u32 fail_cnt = 0;
+ u32 target_cnt = 2;
+ u32 test_cnt = 0;
+ u32 pattern;
+ u32 i = 0;
+ bool finish = false;
+
+ debug("sdram mc test:\n");
+ while (!finish) {
+ pattern = as2600_sdrammc_test_pattern[i++];
+ i = i % MC_TEST_PATTERN_N;
+ debug(" pattern = %08X : ", pattern);
+ writel(pattern, &regs->test_init_val);
+
+ if (ast2600_sdrammc_cbr_test(info)) {
+ debug("fail\n");
+ fail_cnt++;
+ } else {
+ debug("pass\n");
+ pass_cnt++;
+ }
+
+ if (++test_cnt == target_cnt)
+ finish = true;
+ }
+ debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt,
+ target_cnt);
+
+ return fail_cnt;
+}
+#endif
+
+/*
+ * scu500[14:13]
+ * 2b'00: VGA memory size = 16MB
+ * 2b'01: VGA memory size = 16MB
+ * 2b'10: VGA memory size = 32MB
+ * 2b'11: VGA memory size = 64MB
+ *
+ * mcr04[3:2]
+ * 2b'00: VGA memory size = 8MB
+ * 2b'01: VGA memory size = 16MB
+ * 2b'10: VGA memory size = 32MB
+ * 2b'11: VGA memory size = 64MB
+ */
+static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
+{
+ u32 vga_hwconf;
+ size_t vga_mem_size_base = 8 * 1024 * 1024;
+
+ vga_hwconf =
+ (readl(&info->scu->hwstrap1) & SCU_HWSTRAP1_VGA_MEM_MASK) >>
+ SCU_HWSTRAP1_VGA_MEM_SHIFT;
+
+ if (vga_hwconf == 0) {
+ vga_hwconf = 1;
+ writel(vga_hwconf << SCU_HWSTRAP1_VGA_MEM_SHIFT,
+ &info->scu->hwstrap1);
+ }
+
+ clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK,
+ ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) &
+ SDRAM_CONF_VGA_SIZE_MASK));
+
+ /* no need to reserve VGA memory if efuse[VGA disable] is set */
+ if (readl(&info->scu->efuse) & SCU_EFUSE_DIS_VGA)
+ return 0;
+
+ return vga_mem_size_base << vga_hwconf;
+}
+
+/*
+ * Find out RAM size and save it in dram_info
+ *
+ * The procedure is taken from Aspeed SDK
+ */
+static void ast2600_sdrammc_calc_size(struct dram_info *info)
+{
+ /* The controller supports 256/512/1024/2048 MB ram */
+ size_t ram_size = SDRAM_MIN_SIZE;
+ const int write_test_offset = 0x100000;
+ u32 test_pattern = 0xdeadbeef;
+ u32 cap_param = SDRAM_CONF_CAP_2048M;
+ u32 refresh_timing_param = DDR4_TRFC;
+ const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+
+ for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
+ ram_size >>= 1) {
+ writel(test_pattern, write_addr_base + (ram_size >> 1));
+ test_pattern = (test_pattern >> 4) | (test_pattern << 28);
+ }
+
+ /* One last write to overwrite all wrapped values */
+ writel(test_pattern, write_addr_base);
+
+ /* Reset the pattern and see which value was really written */
+ test_pattern = 0xdeadbeef;
+ for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
+ ram_size >>= 1) {
+ if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
+ break;
+
+ --cap_param;
+ refresh_timing_param >>= 8;
+ test_pattern = (test_pattern >> 4) | (test_pattern << 28);
+ }
+
+ clrsetbits_le32(&info->regs->ac_timing[1],
+ (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
+ ((refresh_timing_param & SDRAM_AC_TRFC_MASK)
+ << SDRAM_AC_TRFC_SHIFT));
+
+ info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
+
+ clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK,
+ ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK));
+}
+
+static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
+{
+ const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
+ MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
+ MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
+ (0x1 << MCR34_ODT_EXT_SHIFT);
+
+ /* init SDRAM-PHY only on real chip */
+ ast2600_sdramphy_init(ast2600_sdramphy_config, info);
+ writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
+ &info->regs->power_ctrl);
+ udelay(5);
+ ast2600_sdramphy_kick_training(info);
+ udelay(500);
+ writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
+
+ writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
+ writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
+ writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
+ writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
+ writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
+ writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
+ writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
+ &info->regs->mode_setting_control);
+
+ writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
+ (0x5f << SDRAM_REFRESH_PERIOD_SHIFT),
+ &info->regs->refresh_timing);
+
+ /* wait self-refresh idle */
+ while (readl(&info->regs->power_ctrl) &
+ MCR34_SELF_REFRESH_STATUS_MASK)
+ ;
+
+ writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
+ SDRAM_REFRESH_ZQCS_EN |
+ (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) |
+ (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
+ &info->regs->refresh_timing);
+
+ writel(power_ctrl, &info->regs->power_ctrl);
+ udelay(500);
+
+ return 0;
+}
+
+static void ast2600_sdrammc_unlock(struct dram_info *info)
+{
+ writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
+ while (!readl(&info->regs->protection_key))
+ ;
+}
+
+static void ast2600_sdrammc_lock(struct dram_info *info)
+{
+ writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
+ while (readl(&info->regs->protection_key))
+ ;
+}
+
+static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
+{
+ int i;
+
+ writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
+ writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
+ writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT,
+ &regs->arbitration_ctrl);
+ writel(0xFFBBFFF4, &regs->req_limit_mask);
+
+ for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
+ writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
+
+ writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl);
+
+ writel(0x07FFFFFF, &regs->ecc_range_ctrl);
+
+ writel(0, &regs->ecc_test_ctrl);
+ writel(0x80000001, &regs->test_addr);
+ writel(0, &regs->test_fail_dq_bit);
+ writel(0, &regs->test_init_val);
+
+ writel(0xFFFFFFFF, &regs->req_input_ctrl);
+ writel(0, &regs->req_high_pri_ctrl);
+
+ udelay(600);
+
+#ifdef CONFIG_ASPEED_DDR4_DUALX8
+ writel(0x37, &regs->config);
+#else
+ writel(0x17, &regs->config);
+#endif
+
+ /* load controller setting */
+ for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
+ writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
+
+ writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
+ writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
+ writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
+ writel(DDR4_MR6_MODE, &regs->mr6_mode_setting);
+}
+
+/*
+ * Update size info according to the ECC HW setting
+ *
+ * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we
+ * don't need to calculate the ECC size again but read from MCR04 and derive the
+ * size from its value.
+ */
+static void ast2600_sdrammc_update_size(struct dram_info *info)
+{
+ struct ast2600_sdrammc_regs *regs = info->regs;
+ u32 conf = readl(&regs->config);
+ u32 cap_param;
+ size_t ram_size = SDRAM_MAX_SIZE;
+ size_t hw_size;
+
+ cap_param = (conf & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT;
+ switch (cap_param) {
+ case SDRAM_CONF_CAP_2048M:
+ ram_size = 2048 * SDRAM_SIZE_1MB;
+ break;
+ case SDRAM_CONF_CAP_1024M:
+ ram_size = 1024 * SDRAM_SIZE_1MB;
+ break;
+ case SDRAM_CONF_CAP_512M:
+ ram_size = 512 * SDRAM_SIZE_1MB;
+ break;
+ case SDRAM_CONF_CAP_256M:
+ ram_size = 256 * SDRAM_SIZE_1MB;
+ break;
+ }
+
+ info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
+
+ if (0 == (conf & SDRAM_CONF_ECC_SETUP))
+ return;
+
+ hw_size = readl(&regs->ecc_range_ctrl) & SDRAM_ECC_RANGE_ADDR_MASK;
+ hw_size += (1 << SDRAM_ECC_RANGE_ADDR_SHIFT);
+
+ info->info.size = hw_size;
+}
+
+#ifdef CONFIG_ASPEED_ECC
+static void ast2600_sdrammc_ecc_enable(struct dram_info *info)
+{
+ struct ast2600_sdrammc_regs *regs = info->regs;
+ size_t conf_size;
+ u32 reg;
+
+ conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB;
+ if (conf_size > info->info.size) {
+ printf("warning: ECC configured %dMB but actual size is %dMB\n",
+ CONFIG_ASPEED_ECC_SIZE,
+ info->info.size / SDRAM_SIZE_1MB);
+ conf_size = info->info.size;
+ } else if (conf_size == 0) {
+ conf_size = info->info.size;
+ }
+
+ info->info.size = (((conf_size / 9) * 8) >> 20) << 20;
+ writel(((info->info.size >> 20) - 1) << 20, &regs->ecc_range_ctrl);
+ reg = readl(&regs->config) | SDRAM_CONF_ECC_SETUP;
+ writel(reg, &regs->config);
+
+ writel(0, &regs->test_init_val);
+ writel(0x80000001, &regs->test_addr);
+ writel(0x221, &regs->ecc_test_ctrl);
+ while (0 == (readl(&regs->ecc_test_ctrl) & BIT(12)))
+ ;
+ writel(0, &regs->ecc_test_ctrl);
+ writel(BIT(31), &regs->intr_ctrl);
+ writel(0, &regs->intr_ctrl);
+}
+#endif
+
+static int ast2600_sdrammc_probe(struct udevice *dev)
+{
+ int ret;
+ u32 reg;
+ struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
+ struct ast2600_sdrammc_regs *regs = priv->regs;
+ struct udevice *clk_dev;
+
+ /* find SCU base address from clock device */
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(aspeed_ast2600_scu), &clk_dev);
+ if (ret) {
+ debug("clock device not defined\n");
+ return ret;
+ }
+
+ priv->scu = devfdt_get_addr_ptr(clk_dev);
+ if (IS_ERR(priv->scu)) {
+ debug("%s(): can't get SCU\n", __func__);
+ return PTR_ERR(priv->scu);
+ }
+
+ if (readl(&priv->scu->dram_hdshk) & SCU_DRAM_HDSHK_RDY) {
+ printf("already initialized, ");
+ ast2600_sdrammc_update_size(priv);
+ return 0;
+ }
+
+ reg = readl(&priv->scu->mpll);
+ reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK |
+ SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK);
+ reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG);
+ writel(reg, &priv->scu->mpll);
+ writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext);
+ udelay(100);
+ reg &= ~(SCU_PLL_RST | SCU_PLL_OFF);
+ writel(reg, &priv->scu->mpll);
+
+ while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0)
+ ;
+
+ ast2600_sdrammc_unlock(priv);
+ ast2600_sdrammc_common_init(regs);
+L_ast2600_sdramphy_train:
+ ast2600_sdrammc_init_ddr4(priv);
+
+ /* make sure DDR-PHY is ready before access */
+ do {
+ reg = readl(priv->phy_status) & BIT(1);
+ } while (reg == 0);
+
+ if (ast2600_sdramphy_check_status(priv) != 0) {
+ printf("DDR4 PHY training fail, retrain\n");
+ goto L_ast2600_sdramphy_train;
+ }
+
+ ast2600_sdrammc_calc_size(priv);
+
+#ifndef CONFIG_ASPEED_BYPASS_SELFTEST
+ if (ast2600_sdrammc_test(priv) != 0) {
+ printf("%s: DDR4 init fail\n", __func__);
+ return -EINVAL;
+ }
+#endif
+
+#ifdef CONFIG_ASPEED_ECC
+ ast2600_sdrammc_ecc_enable(priv);
+#endif
+
+ writel(readl(&priv->scu->dram_hdshk) | SCU_DRAM_HDSHK_RDY,
+ &priv->scu->dram_hdshk);
+
+ clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
+ ast2600_sdrammc_lock(priv);
+ return 0;
+}
+
+static int ast2600_sdrammc_of_to_plat(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
+ priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
+ priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
+
+ priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "clock-frequency", 0);
+ if (!priv->clock_rate) {
+ debug("DDR Clock Rate not defined\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops ast2600_sdrammc_ops = {
+ .get_info = ast2600_sdrammc_get_info,
+};
+
+static const struct udevice_id ast2600_sdrammc_ids[] = {
+ { .compatible = "aspeed,ast2600-sdrammc" },
+ { }
+};
+
+U_BOOT_DRIVER(sdrammc_ast2600) = {
+ .name = "aspeed_ast2600_sdrammc",
+ .id = UCLASS_RAM,
+ .of_match = ast2600_sdrammc_ids,
+ .ops = &ast2600_sdrammc_ops,
+ .of_to_plat = ast2600_sdrammc_of_to_plat,
+ .probe = ast2600_sdrammc_probe,
+ .priv_auto = sizeof(struct dram_info),
+};
diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c
index fc80fb1e2c..68043d7cb6 100644
--- a/drivers/ram/k3-j721e/lpddr4.c
+++ b/drivers/ram/k3-j721e/lpddr4.c
@@ -719,7 +719,7 @@ uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,
/* MISRA compliance (Shifting operation) check */
if (fieldshift < WORD_SHIFT) {
- if (((ctlirqstatus >> fieldshift) & BIT_MASK) > 0U) {
+ if ((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) {
*irqstatus = true;
} else {
*irqstatus = false;
@@ -746,11 +746,11 @@ uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,
if (localinterrupt > WORD_SHIFT) {
localinterrupt =
(localinterrupt - (uint32_t) WORD_SHIFT);
- regval = ((uint32_t) BIT_MASK << localinterrupt);
+ regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG),
regval);
} else {
- regval = ((uint32_t) BIT_MASK << localinterrupt);
+ regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG),
regval);
}
@@ -823,7 +823,7 @@ uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,
phyindepirqstatus =
CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
*irqstatus =
- (((phyindepirqstatus >> (uint32_t) intr) & BIT_MASK) > 0U);
+ !!((phyindepirqstatus >> (uint32_t)intr) & LPDDR4_BIT_MASK);
}
return result;
}
@@ -841,7 +841,7 @@ uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
/* Write 1 to the requested bit to ACk the interrupt */
- regval = ((uint32_t) BIT_MASK << ui32shiftinterrupt);
+ regval = (uint32_t)LPDDR4_BIT_MASK << ui32shiftinterrupt;
CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
}
@@ -894,7 +894,7 @@ static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,
(volatile uint32_t
*)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
/* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */
- errbitmask = (BIT_MASK << 1) | (BIT_MASK);
+ errbitmask = (LPDDR4_BIT_MASK << 1) | LPDDR4_BIT_MASK;
for (snum = 0U; snum < DSLICE_NUM; snum++) {
regval = CPS_REG_READ(regaddress);
if ((regval & errbitmask) != 0U) {
@@ -1054,7 +1054,7 @@ static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,
lpddr4_debuginfo * debuginfo, bool * errfoundptr)
{
- uint32_t errbitmask = (BIT_MASK << 0x1U) | (BIT_MASK);
+ uint32_t errbitmask = (LPDDR4_BIT_MASK << 0x1U) | LPDDR4_BIT_MASK;
/* Check PLL observation registers for PLL lock errors */
debuginfo->pllerror =
diff --git a/drivers/ram/k3-j721e/lpddr4_private.h b/drivers/ram/k3-j721e/lpddr4_private.h
index 42c923464a..3d5017ea47 100644
--- a/drivers/ram/k3-j721e/lpddr4_private.h
+++ b/drivers/ram/k3-j721e/lpddr4_private.h
@@ -14,9 +14,9 @@
#define VERSION_0 (0x54d5da40U)
#define VERSION_1 (0xc1865a1U)
-#define BIT_MASK (0x1U)
-#define BYTE_MASK (0xffU)
-#define NIBBLE_MASK (0xfU)
+#define LPDDR4_BIT_MASK (0x1U)
+#define BYTE_MASK (0xffU)
+#define NIBBLE_MASK (0xfU)
#define WORD_SHIFT (32U)
#define WORD_MASK (0xffffffffU)
@@ -46,11 +46,15 @@
#define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
#define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
-#define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U)
-#define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U))
+#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U)
+#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \
+ ((uint32_t)LPDDR4_BIT_MASK << 4U))
#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
-#define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U))
-#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U))
-#define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U))
+#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \
+ ((uint32_t)LPDDR4_BIT_MASK << 6U))
+#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \
+ (((uint32_t)BYTE_MASK) << 16U))
+#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \
+ (((uint32_t)BYTE_MASK) << 18U))
#endif /* LPDDR4_PRIV_H */
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 4003db0e50..540ad85138 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -4,6 +4,8 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -272,7 +274,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (ret) {
- dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
+ dev_dbg(dev, "can't find syscon device (%d)\n", ret);
} else {
syscfg_base = (u32 *)ofnode_get_addr(args.node);
@@ -281,7 +283,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
/* set memory mapping selection */
clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
} else {
- dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
+ dev_dbg(dev, "cannot find st,mem_remap property\n");
}
swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
@@ -289,7 +291,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
/* set fmc swapping selection */
clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
} else {
- dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
+ dev_dbg(dev, "cannot find st,swp_fmc property\n");
}
dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
@@ -348,7 +350,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
}
params->no_sdram_banks = bank;
- debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+ dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks);
return 0;
}
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index bf3a4c97a4..0457166b12 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <clk.h>
#include <log.h>
@@ -311,17 +313,17 @@ static void set_reg(const struct ddr_info *priv,
u32 base_addr = get_base_addr(priv, base);
const struct reg_desc *desc = ddr_registers[type].desc;
- debug("init %s\n", ddr_registers[type].name);
+ log_debug("init %s\n", ddr_registers[type].name);
for (i = 0; i < ddr_registers[type].size; i++) {
ptr = (unsigned int *)(base_addr + desc[i].offset);
if (desc[i].par_offset == INVALID_OFFSET) {
- pr_err("invalid parameter offset for %s", desc[i].name);
+ log_err("invalid parameter offset for %s", desc[i].name);
} else {
value = *((u32 *)((u32)param +
desc[i].par_offset));
writel(value, ptr);
- debug("[0x%x] %s= 0x%08x\n",
- (u32)ptr, desc[i].name, value);
+ log_debug("[0x%x] %s= 0x%08x\n",
+ (u32)ptr, desc[i].name, value);
}
}
}
@@ -564,16 +566,16 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
DDRPHYC_PGSR_RVERR |
DDRPHYC_PGSR_RVEIRR),
1000000);
- debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
- (u32)&phy->pgsr, pgsr, ret);
+ log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
+ (u32)&phy->pgsr, pgsr, ret);
}
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
{
pir |= DDRPHYC_PIR_INIT;
writel(pir, &phy->pir);
- debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
- (u32)&phy->pir, pir, readl(&phy->pir));
+ log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
+ (u32)&phy->pir, pir, readl(&phy->pir));
/* need to wait 10 configuration clock before start polling */
udelay(10);
@@ -603,7 +605,7 @@ static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
panic("Timeout initialising DRAM : DDR->swstat = %x\n",
swstat);
- debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
+ log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
}
/* wait quasi dynamic register update */
@@ -634,7 +636,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode)
if (ret)
panic("Timeout DRAM : DDR->stat = %x\n", stat);
- debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
+ log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
}
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
@@ -706,9 +708,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
panic("ddr power init failed\n");
start:
- debug("name = %s\n", config->info.name);
- debug("speed = %d kHz\n", config->info.speed);
- debug("size = 0x%x\n", config->info.size);
+ log_debug("name = %s\n", config->info.name);
+ log_debug("speed = %d kHz\n", config->info.speed);
+ log_debug("size = 0x%x\n", config->info.size);
/*
* 1. Program the DWC_ddr_umctl2 registers
* 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
@@ -745,8 +747,8 @@ start:
/* 1.5. initialize registers ddr_umctl2 */
/* Stop uMCTL2 before PHY is ready */
clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
- debug("[0x%08x] dfimisc = 0x%08x\n",
- (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
+ log_debug("[0x%08x] dfimisc = 0x%08x\n",
+ (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
set_reg(priv, REG_REG, &config->c_reg);
set_reg(priv, REG_TIMING, &config->c_timing);
@@ -809,9 +811,9 @@ start:
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
if (config->p_cal_present) {
- debug("DDR DQS training skipped.\n");
+ log_debug("DDR DQS training skipped.\n");
} else {
- debug("DDR DQS training : ");
+ log_debug("DDR DQS training : ");
/* 8. Disable Auto refresh and power down by setting
* - RFSHCTL3.dis_au_refresh = 1
* - PWRCTL.powerdown_en = 0
diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c
index 5a5d067046..e45a2489c5 100644
--- a/drivers/ram/stm32mp1/stm32mp1_interactive.c
+++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c
@@ -3,6 +3,8 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <command.h>
#include <console.h>
@@ -404,7 +406,7 @@ bool stm32mp1_ddr_interactive(void *priv,
#endif
}
- debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
+ log_debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
if (next_step < 0)
return false;
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index 0b6d20f566..26f0b4f1ea 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -12,6 +14,7 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include "stm32mp1_ddr.h"
static const char *const clkname[] = {
@@ -37,7 +40,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
ret = clk_enable(&clk);
if (ret) {
- printf("error for %s : %d\n", clkname[idx], ret);
+ log_err("error for %s : %d\n", clkname[idx], ret);
return ret;
}
}
@@ -45,13 +48,13 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
priv->clk = clk;
ddrphy_clk = clk_get_rate(&priv->clk);
- debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
- mem_speed, (u32)(ddrphy_clk / 1000));
+ log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000));
/* max 10% frequency delta */
ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
if (ddr_clk > (mem_speed * 100)) {
- pr_err("DDR expected freq %d kHz, current is %d kHz\n",
- mem_speed, (u32)(ddrphy_clk / 1000));
+ log_err("DDR expected freq %d kHz, current is %d kHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000));
return -EINVAL;
}
@@ -118,7 +121,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
config.info.name = ofnode_read_string(node, "st,mem-name");
if (!config.info.name) {
- debug("%s: no st,mem-name\n", __func__);
+ dev_dbg(dev, "no st,mem-name\n");
return -EINVAL;
}
printf("RAM: %s\n", config.info.name);
@@ -128,12 +131,12 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
(void *)((u32)&config +
param[idx].offset),
param[idx].size);
- debug("%s: %s[0x%x] = %d\n", __func__,
- param[idx].name, param[idx].size, ret);
+ dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
+ param[idx].name, param[idx].size, ret);
if (ret &&
(ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
- pr_err("%s: Cannot read %s, error=%d\n",
- __func__, param[idx].name, ret);
+ dev_err(dev, "Cannot read %s, error=%d\n",
+ param[idx].name, ret);
return -EINVAL;
}
if (param[idx].present) {
@@ -153,7 +156,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
ret = clk_get_by_name(dev, "axidcg", &axidcg);
if (ret) {
- debug("%s: Cannot found axidcg\n", __func__);
+ dev_dbg(dev, "%s: Cannot found axidcg\n", __func__);
return -EINVAL;
}
clk_disable(&axidcg); /* disable clock gating during init */
@@ -163,13 +166,13 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
clk_enable(&axidcg); /* enable clock gating */
/* check size */
- debug("%s : get_ram_size(%x, %x)\n", __func__,
- (u32)priv->info.base, (u32)STM32_DDR_SIZE);
+ dev_dbg(dev, "get_ram_size(%x, %x)\n",
+ (u32)priv->info.base, (u32)STM32_DDR_SIZE);
priv->info.size = get_ram_size((long *)priv->info.base,
STM32_DDR_SIZE);
- debug("%s : %x\n", __func__, (u32)priv->info.size);
+ dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size);
/* check memory access for all memory */
if (config.info.size != priv->info.size) {
@@ -186,12 +189,11 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
struct regmap *map;
int ret;
- debug("STM32MP1 DDR probe\n");
priv->dev = dev;
ret = regmap_init_mem(dev_ofnode(dev), &map);
if (ret)
- return ret;
+ return log_ret(ret);
priv->ctl = regmap_get_range(map, 0);
priv->phy = regmap_get_range(map, 1);
@@ -203,7 +205,9 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
#if !defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
priv->info.size = 0;
- return stm32mp1_ddr_setup(dev);
+ ret = stm32mp1_ddr_setup(dev);
+
+ return log_ret(ret);
#else
ofnode node = stm32mp1_ddr_get_ofnode(dev);
priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c
index 952006aa14..1fcc7cfd69 100644
--- a/drivers/ram/stm32mp1/stm32mp1_tests.c
+++ b/drivers/ram/stm32mp1/stm32mp1_tests.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <console.h>
#include <init.h>
@@ -197,8 +200,8 @@ static u32 databus(u32 *address)
/* Read it back (immediately is okay for this test). */
read_value = readl(address);
- debug("%x: %x <=> %x\n",
- (u32)address, read_value, pattern);
+ log_debug("%x: %x <=> %x\n",
+ (u32)address, read_value, pattern);
if (read_value != pattern)
return pattern;
@@ -252,8 +255,8 @@ static u32 *addressbus(u32 *address, u32 nb_bytes)
for (offset = 1; (offset & mask) != 0; offset <<= 1) {
read_value = readl(&address[offset]);
- debug("%x: %x <=> %x\n",
- (u32)&address[offset], read_value, pattern);
+ log_debug("%x: %x <=> %x\n",
+ (u32)&address[offset], read_value, pattern);
if (read_value != pattern)
return &address[offset];
}
@@ -363,8 +366,8 @@ static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl,
data = readl(addr + 4 * i);
if (~(1 << i) != data) {
error |= 1 << i;
- debug("%x: error %x expected %x => error:%x\n",
- addr + 4 * i, data, ~(1 << i), error);
+ log_debug("%x: error %x expected %x => error:%x\n",
+ addr + 4 * i, data, ~(1 << i), error);
}
}
if (test_loop_end(&loop, nb_loop, 1000))
@@ -403,8 +406,8 @@ static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl,
data = readl(addr + 4 * i);
if ((1 << i) != data) {
error |= 1 << i;
- debug("%x: error %x expected %x => error:%x\n",
- addr + 4 * i, data, (1 << i), error);
+ log_debug("%x: error %x expected %x => error:%x\n",
+ addr + 4 * i, data, (1 << i), error);
}
}
if (test_loop_end(&loop, nb_loop, 1000))
diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c
index a8d6892bb0..c8cd7c3cea 100644
--- a/drivers/ram/stm32mp1/stm32mp1_tuning.c
+++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <console.h>
#include <clk.h>
@@ -227,8 +230,7 @@ static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
& DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
- pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
- __func__, addr, readl(addr), index);
+ log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index);
return index;
}
@@ -470,13 +472,13 @@ static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
for (bit_i = 0; bit_i < 8; bit_i++) {
set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
index = DQ_unit_index(phy, byte, bit_i);
- pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
- byte, bit_i, deskew_delay[byte][bit_i],
- index, index - 3);
+ log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
+ byte, bit_i, deskew_delay[byte][bit_i],
+ index, index - 3);
printf("Byte %d, bit %d, DQ delay = %d",
byte, bit_i, deskew_delay[byte][bit_i]);
if (deskew_non_converge[byte][bit_i] == 1)
- pr_debug(" - not converged : still more skew");
+ log_debug(" - not converged : still more skew");
printf("\n");
}
}
@@ -536,7 +538,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
/* Config the BIST block */
config_BIST(ctl, phy);
- pr_debug("BIST Config done.\n");
+ log_debug("BIST Config done.\n");
/* Train each byte */
for (datx8 = 0; datx8 < nb_bytes; datx8++) {
@@ -545,9 +547,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
datx8 + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("\n======================\n");
- pr_debug("Start deskew byte %d .\n", datx8);
- pr_debug("======================\n");
+ log_debug("\n======================\n");
+ log_debug("Start deskew byte %d .\n", datx8);
+ log_debug("======================\n");
/* Enable Byte (DXNGCR, bit DXEN) */
setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
@@ -584,7 +586,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* Else, look for Pass init condition
*/
if (!success) {
- pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
+ log_debug("Fail at init condtion. Let's look for a good init condition.\n");
success = 0; /* init */
/* Make sure we start with a PASS condition before
* looking for a fail condition.
@@ -592,7 +594,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
/* escape if we find a PASS */
- pr_debug("increase Phase idx\n");
+ log_debug("increase Phase idx\n");
while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
DQS_phase_delay(phy, datx8, phase_idx);
BIST_test(phy, datx8, &result);
@@ -618,7 +620,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* we have hold violation, lets try reduce DQS_unit
* Delay
*/
- pr_debug("Still fail. Try decrease DQS Unit delay\n");
+ log_debug("Still fail. Try decrease DQS Unit delay\n");
phase_idx = 0;
dqs_unit_delay_index = 0;
@@ -665,9 +667,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
return TEST_FAILED;
}
- pr_debug("there is a pass region for phase idx %d\n",
- phase_idx);
- pr_debug("Step1: Find the first failing condition\n");
+ log_debug("there is a pass region for phase idx %d\n",
+ phase_idx);
+ log_debug("Step1: Find the first failing condition\n");
/* Look for the first failing condition by PHASE stepping.
* This part of the algo can finish without converging.
*/
@@ -692,9 +694,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* stepping (minimal delay)
*/
if (!success) {
- pr_debug("Fail region (PHASE) found phase idx %d\n",
- phase_idx);
- pr_debug("Let's look for first success by DQS Unit steps\n");
+ log_debug("Fail region (PHASE) found phase idx %d\n",
+ phase_idx);
+ log_debug("Let's look for first success by DQS Unit steps\n");
/* This part, the algo always converge */
phase_idx--;
@@ -721,7 +723,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
/*+1 to get back to current condition */
last_right_ok.unit = dqs_unit_delay_index + 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Found %d\n", dqs_unit_delay_index);
+ log_debug("Found %d\n", dqs_unit_delay_index);
} else {
/* the last OK condition is then with the
* previous phase_idx.
@@ -735,8 +737,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
last_right_ok.unit = 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Not Found : try previous phase %d\n",
- phase_idx - 1);
+ log_debug("Not Found : try previous phase %d\n",
+ phase_idx - 1);
DQS_phase_delay(phy, datx8, phase_idx - 1);
dqs_unit_delay_index = 0;
@@ -749,8 +751,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
BIST_test(phy, datx8, &result);
success = result.test_result;
dqs_unit_delay_index++;
- pr_debug("dqs_unit_delay_index = %d, result = %d\n",
- dqs_unit_delay_index, success);
+ log_debug("dqs_unit_delay_index = %d, result = %d\n",
+ dqs_unit_delay_index, success);
}
if (!success) {
@@ -758,7 +760,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
dqs_unit_delay_index - 1;
} else {
last_right_ok.unit = 0;
- pr_debug("ERROR: failed region not FOUND");
+ log_debug("ERROR: failed region not FOUND");
}
}
} else {
@@ -775,7 +777,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
last_right_ok.phase = MAX_DQS_PHASE_IDX;
last_right_ok.unit = MAX_DQS_UNIT_IDX;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Can't find the a fail condition\n");
+ log_debug("Can't find the a fail condition\n");
}
/* step 2:
@@ -787,9 +789,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
printf("Byte %d, DQS unit = %d, phase = %d\n",
datx8, last_right_ok.unit, last_right_ok.phase);
- pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
- last_right_ok.unit, last_right_ok.phase,
- last_right_ok.bits_delay);
+ log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
+ last_right_ok.unit, last_right_ok.phase,
+ last_right_ok.bits_delay);
/* Restore the last_right_ok condtion. */
DQS_unit_delay(phy, datx8, last_right_ok.unit);
@@ -812,7 +814,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
datx8 + 1, nb_bytes, error);
return error;
}
- pr_debug("deskewing bit %d:\n", bit_i);
+ log_debug("deskewing bit %d:\n", bit_i);
success = 1; /* init */
/* Set all DQDLYn to maximum value.
* Only bit_i will be down-delayed
@@ -855,10 +857,10 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* at one bit.
*/
fail_found = 1;
- pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
- bit_i, bit_i_delay_index + 1,
- datx8, bit_i,
- deskew_delay[datx8][bit_i]);
+ log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
+ bit_i, bit_i_delay_index + 1,
+ datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
} else {
/* if we can find a success condition by
* back-delaying this bit, just set the delay
@@ -870,20 +872,20 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* in the report.
*/
deskew_non_converge[datx8][bit_i] = 1;
- pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
- bit_i, datx8, bit_i,
- deskew_delay[datx8][bit_i]);
+ log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
+ bit_i, datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
}
}
- pr_debug("**********byte %d tuning complete************\n",
- datx8);
+ log_debug("**********byte %d tuning complete************\n",
+ datx8);
/* If we can't find any failure by back delaying DQ lines,
* hold the default values
*/
if (!fail_found) {
for (bit_i = 0; bit_i < 8; bit_i++)
deskew_delay[datx8][bit_i] = 0;
- pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
+ log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
}
apply_deskew_results(phy, datx8, deskew_delay,
@@ -986,7 +988,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
dqs_unit_delay_index_pass = dqs_unit_delay_index;
success = 0;
- pr_debug("STEP0: Find Init delay\n");
+ log_debug("STEP0: Find Init delay\n");
/* STEP0: Find Init delay: a delay that put the system
* in a "Pass" condition then (TODO) update
* dqs_unit_delay_index_pass & phase_idx_pass
@@ -1035,7 +1037,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
+ log_debug("STEP1: Find LEFT PHASE DQS Bound\n");
/* STEP1: Find LEFT PHASE DQS Bound */
while ((phase_idx >= 0) &&
(phase_idx <= MAX_DQS_PHASE_IDX) &&
@@ -1069,7 +1071,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP2: Find UNIT left bound\n");
+ log_debug("STEP2: Find UNIT left bound\n");
/* STEP2: Find UNIT left bound */
while ((dqs_unit_delay_index >= 0) &&
!left_unit_bound_found) {
@@ -1097,7 +1099,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP3: Find PHase right bound\n");
+ log_debug("STEP3: Find PHase right bound\n");
/* STEP3: Find PHase right bound, start with "pass"
* condition
*/
@@ -1135,7 +1137,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP4: Find UNIT right bound\n");
+ log_debug("STEP4: Find UNIT right bound\n");
/* STEP4: Find UNIT right bound */
while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
!right_unit_bound_found) {
@@ -1174,12 +1176,12 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
eye_training_val[byte][1]++;
- pr_debug("** found phase : %d - %d & unit %d - %d\n",
- right_bound.phase, left_bound.phase,
- right_bound.unit, left_bound.unit);
- pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
- eye_training_val[byte][0],
- eye_training_val[byte][1]);
+ log_debug("** found phase : %d - %d & unit %d - %d\n",
+ right_bound.phase, left_bound.phase,
+ right_bound.unit, left_bound.unit);
+ log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
+ eye_training_val[byte][0],
+ eye_training_val[byte][1]);
} else {
/* PPPPPPPPPP, we're already good.
* Set nominal values.
@@ -1280,11 +1282,11 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
* or pppppff or ffppppp
*/
if (left_bound_found || right_bound_found) {
- pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
- left_bound_found,
- right_bound_idx[0], left_bound_idx[0],
- right_bound_found,
- right_bound_idx[1], left_bound_idx[1]);
+ log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
+ left_bound_found,
+ right_bound_idx[0], left_bound_idx[0],
+ right_bound_found,
+ right_bound_idx[1], left_bound_idx[1]);
dqs_gate_values[byte][0] =
(right_bound_idx[0] + left_bound_idx[0]) / 2;
dqs_gate_values[byte][1] =
@@ -1319,14 +1321,14 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
left_bound_idx[0];
}
}
- pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
- dqs_gate_values[byte][0],
- dqs_gate_values[byte][1]);
- pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
+ log_debug("*******calculating mid region: system latency: %d phase: %d********\n",
+ dqs_gate_values[byte][0],
+ dqs_gate_values[byte][1]);
+ log_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
}
} else {
/* if intermitant, restore defaut values */
- pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
+ log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
dqs_gate_values[byte][0] = 0;
dqs_gate_values[byte][1] = 2;
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-14 01:14:11 +0000