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path: root/drivers/ram/k3-j721e/lpddr4.c
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Diffstat (limited to 'drivers/ram/k3-j721e/lpddr4.c')
-rw-r--r--drivers/ram/k3-j721e/lpddr4.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c
index fc80fb1e2c..68043d7cb6 100644
--- a/drivers/ram/k3-j721e/lpddr4.c
+++ b/drivers/ram/k3-j721e/lpddr4.c
@@ -719,7 +719,7 @@ uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,
/* MISRA compliance (Shifting operation) check */
if (fieldshift < WORD_SHIFT) {
- if (((ctlirqstatus >> fieldshift) & BIT_MASK) > 0U) {
+ if ((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) {
*irqstatus = true;
} else {
*irqstatus = false;
@@ -746,11 +746,11 @@ uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,
if (localinterrupt > WORD_SHIFT) {
localinterrupt =
(localinterrupt - (uint32_t) WORD_SHIFT);
- regval = ((uint32_t) BIT_MASK << localinterrupt);
+ regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG),
regval);
} else {
- regval = ((uint32_t) BIT_MASK << localinterrupt);
+ regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG),
regval);
}
@@ -823,7 +823,7 @@ uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,
phyindepirqstatus =
CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
*irqstatus =
- (((phyindepirqstatus >> (uint32_t) intr) & BIT_MASK) > 0U);
+ !!((phyindepirqstatus >> (uint32_t)intr) & LPDDR4_BIT_MASK);
}
return result;
}
@@ -841,7 +841,7 @@ uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
/* Write 1 to the requested bit to ACk the interrupt */
- regval = ((uint32_t) BIT_MASK << ui32shiftinterrupt);
+ regval = (uint32_t)LPDDR4_BIT_MASK << ui32shiftinterrupt;
CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
}
@@ -894,7 +894,7 @@ static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,
(volatile uint32_t
*)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
/* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */
- errbitmask = (BIT_MASK << 1) | (BIT_MASK);
+ errbitmask = (LPDDR4_BIT_MASK << 1) | LPDDR4_BIT_MASK;
for (snum = 0U; snum < DSLICE_NUM; snum++) {
regval = CPS_REG_READ(regaddress);
if ((regval & errbitmask) != 0U) {
@@ -1054,7 +1054,7 @@ static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,
lpddr4_debuginfo * debuginfo, bool * errfoundptr)
{
- uint32_t errbitmask = (BIT_MASK << 0x1U) | (BIT_MASK);
+ uint32_t errbitmask = (LPDDR4_BIT_MASK << 0x1U) | LPDDR4_BIT_MASK;
/* Check PLL observation registers for PLL lock errors */
debuginfo->pllerror =