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-rw-r--r--drivers/pci/pci-aardvark.c15
-rw-r--r--drivers/pci/pci_mvebu.c1
-rw-r--r--drivers/pci/pcie_ecam_generic.c17
-rw-r--r--drivers/pci/pcie_ecam_synquacer.c6
-rw-r--r--drivers/pci/pcie_layerscape_fixup.c8
-rw-r--r--drivers/pci/pcie_layerscape_gen4_fixup.c8
-rw-r--r--drivers/pci/pcie_phytium.c8
-rw-r--r--drivers/pci/pcie_rockchip.c13
-rw-r--r--drivers/pci/pcie_xilinx.c5
9 files changed, 31 insertions, 50 deletions
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index a92f00d0af..22b6d8b628 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -21,6 +21,7 @@
*
* Author: Victor Gu <xigu@marvell.com>
* Hezi Shahmoon <hezi.shahmoon@marvell.com>
+ * Pali Rohár <pali@kernel.org>
*
*/
@@ -165,16 +166,6 @@
#define PCIE_CONFIG_WR_TYPE0 0xa
#define PCIE_CONFIG_WR_TYPE1 0xb
-/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(b, d, f) (PCI_BDF(b, d, f) << 4)
-#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
-#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
-#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
-#define PCIE_CONF_REG(reg) ((reg) & 0xffc)
-#define PCIE_CONF_ADDR(bus, devfn, where) \
- (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
- PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
-
/* PCIe Retries & Timeout definitions */
#define PIO_MAX_RETRIES 1500
#define PIO_WAIT_TIMEOUT 1000
@@ -467,7 +458,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
+ reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
@@ -626,7 +617,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
+ reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 62a4df37a0..cc8ebff0c6 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -7,6 +7,7 @@
* Ported to U-Boot by:
* Anton Schubert <anton.schubert@gmx.de>
* Stefan Roese <sr@denx.de>
+ * Pali Rohár <pali@kernel.org>
*/
#include <common.h>
diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
index e83e5aff20..1a9f9aec2e 100644
--- a/drivers/pci/pcie_ecam_generic.c
+++ b/drivers/pci/pcie_ecam_generic.c
@@ -14,6 +14,8 @@
#include <asm/io.h>
+#define TYPE_PCI 0x1
+
/**
* struct generic_ecam_pcie - generic_ecam PCIe controller state
* @cfg_base: The base address of memory mapped configuration space
@@ -46,10 +48,14 @@ static int pci_generic_ecam_conf_address(const struct udevice *bus,
void *addr;
addr = pcie->cfg_base;
- addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
- addr += PCI_DEV(bdf) << 15;
- addr += PCI_FUNC(bdf) << 12;
- addr += offset;
+
+ if (dev_get_driver_data(bus) == TYPE_PCI) {
+ addr += ((PCI_BUS(bdf) - pcie->first_busno) << 16) |
+ (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | offset;
+ } else {
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - pcie->first_busno,
+ PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+ }
*paddress = addr;
return 0;
@@ -158,7 +164,8 @@ static const struct dm_pci_ops pci_generic_ecam_ops = {
};
static const struct udevice_id pci_generic_ecam_ids[] = {
- { .compatible = "pci-host-ecam-generic" },
+ { .compatible = "pci-host-ecam-generic" /* PCI-E */ },
+ { .compatible = "pci-host-cam-generic", .data = TYPE_PCI },
{ }
};
diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c
index c6e7c59f8a..e3e2289108 100644
--- a/drivers/pci/pcie_ecam_synquacer.c
+++ b/drivers/pci/pcie_ecam_synquacer.c
@@ -235,10 +235,8 @@ static int pci_synquacer_ecam_conf_address(const struct udevice *bus,
void *addr;
addr = pcie->cfg_base;
- addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
- addr += PCI_DEV(bdf) << 15;
- addr += PCI_FUNC(bdf) << 12;
- addr += offset;
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - pcie->first_busno,
+ PCI_DEV(bdf), PCI_FUNC(bdf), offset);
*paddress = addr;
return 0;
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 8a2a0e1f4a..a47c9ef7c2 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -584,9 +584,9 @@ static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
return;
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
@@ -600,9 +600,9 @@ static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
return;
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
index 7d11234106..b2a45bf105 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -193,9 +193,9 @@ static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
}
if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
@@ -214,9 +214,9 @@ static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
}
if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
diff --git a/drivers/pci/pcie_phytium.c b/drivers/pci/pcie_phytium.c
index 752e170321..a807276254 100644
--- a/drivers/pci/pcie_phytium.c
+++ b/drivers/pci/pcie_phytium.c
@@ -36,9 +36,7 @@ static int phytium_pci_skip_dev(pci_dev_t parent)
unsigned short capreg;
unsigned char port_type;
- addr += PCI_BUS(parent) << 20;
- addr += PCI_DEV(parent) << 15;
- addr += PCI_FUNC(parent) << 12;
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(parent), PCI_DEV(parent), PCI_FUNC(parent), 0);
pos = 0x34;
while (1) {
@@ -89,9 +87,7 @@ static int pci_phytium_conf_address(const struct udevice *bus, pci_dev_t bdf,
bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
addr = pcie->cfg_base;
- addr += PCI_BUS(bdf) << 20;
- addr += PCI_DEV(bdf) << 15;
- addr += PCI_FUNC(bdf) << 12;
+ addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), 0);
if (bus_no > 0 && dev_no > 0) {
if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index b0c91c0f43..67039d2a29 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -101,15 +101,6 @@ struct rockchip_pcie {
struct phy pcie_phy;
};
-static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
-{
- unsigned int bus = PCI_BUS(bdf);
- unsigned int dev = PCI_DEV(bdf);
- unsigned int func = PCI_FUNC(bdf);
-
- return (bus << 20) | (dev << 15) | (func << 12) | (offset & ~0x3);
-}
-
static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
@@ -117,7 +108,7 @@ static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
struct rockchip_pcie *priv = dev_get_priv(udev);
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
- int where = rockchip_pcie_off_conf(bdf, offset);
+ int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset & ~0x3);
ulong value;
if (bus == priv->first_busno && dev == 0) {
@@ -144,7 +135,7 @@ static int rockchip_pcie_wr_conf(struct udevice *udev, pci_dev_t bdf,
struct rockchip_pcie *priv = dev_get_priv(udev);
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
- int where = rockchip_pcie_off_conf(bdf, offset);
+ int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset & ~0x3);
ulong old;
if (bus == priv->first_busno && dev == 0) {
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index ae9a65b0a9..eb9ec97b74 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -76,10 +76,7 @@ static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
return -ENODEV;
addr = pcie->cfg_base;
- addr += bus << 20;
- addr += dev << 15;
- addr += func << 12;
- addr += offset;
+ addr += PCIE_ECAM_OFFSET(bus, dev, func, offset);
*paddress = addr;
return 0;
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-28 19:39:56 +0000