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-rw-r--r--drivers/net/designware.c15
-rw-r--r--drivers/net/mscc_eswitch/jr2_switch.c43
-rw-r--r--drivers/net/sun8i_emac.c8
3 files changed, 55 insertions, 11 deletions
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index b8ba00b7c0..5d92257e74 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -91,9 +91,8 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
}
#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
-static int dw_mdio_reset(struct mii_dev *bus)
+static int __dw_mdio_reset(struct udevice *dev)
{
- struct udevice *dev = bus->priv;
struct dw_eth_dev *priv = dev_get_priv(dev);
struct dw_eth_pdata *pdata = dev_get_plat(dev);
int ret;
@@ -122,6 +121,13 @@ static int dw_mdio_reset(struct mii_dev *bus)
return 0;
}
+
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+
+ return __dw_mdio_reset(dev);
+}
#endif
#if IS_ENABLED(CONFIG_DM_MDIO)
@@ -142,9 +148,10 @@ int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int
#if CONFIG_IS_ENABLED(DM_GPIO)
int designware_eth_mdio_reset(struct udevice *mdio_dev)
{
- struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+ struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
+ struct udevice *dev = mdio_pdata->mii_bus->priv;
- return dw_mdio_reset(pdata->mii_bus);
+ return __dw_mdio_reset(dev->parent);
}
#endif
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c
index 128d7f21ce..570d5a5109 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -235,7 +235,7 @@ static const char * const regs_names[] = {
"port36", "port37", "port38", "port39", "port40", "port41", "port42",
"port43", "port44", "port45", "port46", "port47",
"ana_ac", "ana_cl", "ana_l2", "asm", "hsio", "lrn",
- "qfwd", "qs", "qsys", "rew",
+ "qfwd", "qs", "qsys", "rew", "gcb", "icpu",
};
#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
@@ -252,6 +252,8 @@ enum jr2_ctrl_regs {
QS,
QSYS,
REW,
+ GCB,
+ ICPU,
};
#define JR2_MIIM_BUS_COUNT 3
@@ -367,7 +369,6 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr,
{
u32 ib_if_mode = 0;
u32 ib_qrate = 0;
- u32 ib_cal_ena = 0;
u32 ib1_tsdet = 0;
u32 ob_lev = 0;
u32 ob_ena_cas = 0;
@@ -379,7 +380,6 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr,
case PHY_INTERFACE_MODE_SGMII:
ib_if_mode = 1;
ib_qrate = 1;
- ib_cal_ena = 1;
ib1_tsdet = 3;
ob_lev = 48;
ob_ena_cas = 2;
@@ -402,6 +402,12 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr,
if (interface == PHY_INTERFACE_MODE_QSGMII)
writel(0xfff, base + HSIO_HW_CFGSTAT_HW_CFG);
+ writel(HSIO_ANA_SERDES6G_OB_CFG_RESISTOR_CTRL(1) |
+ HSIO_ANA_SERDES6G_OB_CFG_SR(7) |
+ HSIO_ANA_SERDES6G_OB_CFG_SR_H |
+ HSIO_ANA_SERDES6G_OB_CFG_ENA1V_MODE(ob_ena1v_mode) |
+ HSIO_ANA_SERDES6G_OB_CFG_POL, base + HSIO_ANA_SERDES6G_OB_CFG);
+
writel(HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(3),
base + HSIO_ANA_SERDES6G_COMMON_CFG);
writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(120) |
@@ -431,6 +437,21 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr,
HSIO_ANA_SERDES6G_IB_CFG1_TSDET(3) |
HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
base + HSIO_ANA_SERDES6G_IB_CFG1);
+
+ writel(HSIO_ANA_SERDES6G_IB_CFG2_UREG(4) |
+ HSIO_ANA_SERDES6G_IB_CFG2_UMAX(2) |
+ HSIO_ANA_SERDES6G_IB_CFG2_TCALV(12) |
+ HSIO_ANA_SERDES6G_IB_CFG2_OCALS(32) |
+ HSIO_ANA_SERDES6G_IB_CFG2_OINFS(7) |
+ HSIO_ANA_SERDES6G_IB_CFG2_OINFI(0x1f) |
+ HSIO_ANA_SERDES6G_IB_CFG2_TINFV(3),
+ base + HSIO_ANA_SERDES6G_IB_CFG2);
+
+ writel(HSIO_ANA_SERDES6G_IB_CFG3_INI_OFFSET(0x1f) |
+ HSIO_ANA_SERDES6G_IB_CFG3_INI_LP(1) |
+ HSIO_ANA_SERDES6G_IB_CFG3_INI_MID(0x1f),
+ base + HSIO_ANA_SERDES6G_IB_CFG3);
+
writel(HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST,
base + HSIO_DIG_SERDES6G_MISC_CFG);
@@ -505,7 +526,7 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr,
writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
- HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(ib_cal_ena) |
+ HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(1) |
HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
@@ -530,7 +551,7 @@ static void serdes6g_setup(void __iomem *base, uint32_t addr,
writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
- HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(ib_cal_ena) |
+ HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(1) |
HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
@@ -850,6 +871,7 @@ static int jr2_probe(struct udevice *dev)
struct mii_dev *bus;
struct ofnode_phandle_args phandle;
struct phy_device *phy;
+ u32 val;
if (!priv)
return -EINVAL;
@@ -865,6 +887,17 @@ static int jr2_probe(struct udevice *dev)
}
}
+ val = readl(priv->regs[ICPU] + ICPU_RESET);
+ val |= ICPU_RESET_CORE_RST_PROTECT;
+ writel(val, priv->regs[ICPU] + ICPU_RESET);
+
+ val = readl(priv->regs[GCB] + PERF_SOFT_RST);
+ val |= PERF_SOFT_RST_SOFT_SWC_RST;
+ writel(val, priv->regs[GCB] + PERF_SOFT_RST);
+
+ while (readl(priv->regs[GCB] + PERF_SOFT_RST) & PERF_SOFT_RST_SOFT_SWC_RST)
+ ;
+
/* Initialize miim buses */
memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT);
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index a6cdda81a7..5a1b38bf80 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -554,7 +554,7 @@ static int parse_phy_pins(struct udevice *dev)
* The GPIO pinmux value is an integration choice, so depends on the
* SoC, not the EMAC variant.
*/
- if (IS_ENABLED(CONFIG_MACH_SUN8I_H3))
+ if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
iomux = SUN8I_IOMUX_H3;
else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
iomux = SUN8I_IOMUX_R40;
@@ -562,8 +562,12 @@ static int parse_phy_pins(struct udevice *dev)
iomux = SUN8I_IOMUX_H6;
else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
iomux = SUN8I_IOMUX_H616;
- else
+ else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
+ iomux = SUN8I_IOMUX;
+ else if (IS_ENABLED(CONFIG_MACH_SUN50I))
iomux = SUN8I_IOMUX;
+ else
+ BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
for (i = 0; ; i++) {
int pin;
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-30 21:57:45 +0000