diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/net/fsl-mc/mc.c | 75 | ||||
| -rw-r--r-- | drivers/net/macb.c | 13 | ||||
| -rw-r--r-- | drivers/net/zynq_gem.c | 2 |
4 files changed, 20 insertions, 72 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 078d5a84f1..70e36611ea 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -168,7 +168,7 @@ config SUN8I_EMAC help This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. It can be found in H3/A64/A83T based SoCs and compatible with both - External and Internal PHY's. + External and Internal PHYs. config XILINX_AXIEMAC depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 079082a26f..9f69d75a89 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -154,48 +154,6 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr, } #endif -/* - * Calculates the values to be used to specify the address range - * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers. - * It returns the highest 512MB-aligned address within the given - * address range, in '*aligned_base_addr', and the number of 256 MiB - * blocks in it, in 'num_256mb_blocks'. - */ -static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, - size_t mc_ram_size, - u64 *aligned_base_addr, - u8 *num_256mb_blocks) -{ - u64 addr; - u16 num_blocks; - - if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; - if (num_blocks < 1 || num_blocks > 0xff) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - addr = (mc_private_ram_start_addr + mc_ram_size - 1) & - MC_RAM_BASE_ADDR_ALIGNMENT_MASK; - - if (addr < mc_private_ram_start_addr) { - printf("fsl-mc: ERROR: bad start address %#llx\n", - mc_private_ram_start_addr); - return -EFAULT; - } - - *aligned_base_addr = addr; - *num_256mb_blocks = num_blocks; - return 0; -} - static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id, struct eth_device *eth_dev) { @@ -550,17 +508,16 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) size_t raw_image_size = 0; #endif struct mc_version mc_ver_info; - u64 mc_ram_aligned_base_addr; u8 mc_ram_num_256mb_blocks; size_t mc_ram_size = mc_get_dram_block_size(); - - error = calculate_mc_private_ram_params(mc_ram_addr, - mc_ram_size, - &mc_ram_aligned_base_addr, - &mc_ram_num_256mb_blocks); - if (error != 0) + mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; + if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) { + error = -EINVAL; + printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", + mc_ram_size); goto out; + } /* * Management Complex cores should be held at reset out of POR. @@ -602,11 +559,11 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Tell MC what is the address range of the DRAM block assigned to it: */ - reg_mcfbalr = (u32)mc_ram_aligned_base_addr | + reg_mcfbalr = (u32)mc_ram_addr | (mc_ram_num_256mb_blocks - 1); out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); out_le32(&mc_ccsr_regs->reg_mcfbahr, - (u32)(mc_ram_aligned_base_addr >> 32)); + (u32)(mc_ram_addr >> 32)); out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ); /* @@ -714,21 +671,7 @@ int get_dpl_apply_status(void) */ u64 mc_get_dram_addr(void) { - u64 mc_ram_addr; - - /* - * The MC private DRAM block was already carved at the end of DRAM - * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: - */ - if (gd->bd->bi_dram[1].start) { - mc_ram_addr = - gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; - } else { - mc_ram_addr = - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; - } - - return mc_ram_addr; + return gd->arch.resv_ram; } /** diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 1c4bef97b6..402e866817 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -113,7 +113,9 @@ struct macb_device { struct mii_dev *bus; #ifdef CONFIG_DM_ETH +#ifdef CONFIG_CLK unsigned long pclk_rate; +#endif phy_interface_t phy_interface; #endif }; @@ -756,7 +758,7 @@ static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) static u32 macb_mdc_clk_div(int id, struct macb_device *macb) { u32 config; -#ifdef CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) unsigned long macb_hz = macb->pclk_rate; #else unsigned long macb_hz = get_macb_pclk_rate(id); @@ -778,7 +780,7 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb) { u32 config; -#ifdef CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) unsigned long macb_hz = macb->pclk_rate; #else unsigned long macb_hz = get_macb_pclk_rate(id); @@ -1002,6 +1004,7 @@ static const struct eth_ops macb_eth_ops = { .write_hwaddr = macb_write_hwaddr, }; +#ifdef CONFIG_CLK static int macb_enable_clk(struct udevice *dev) { struct macb_device *macb = dev_get_priv(dev); @@ -1025,13 +1028,13 @@ static int macb_enable_clk(struct udevice *dev) return 0; } +#endif static int macb_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct macb_device *macb = dev_get_priv(dev); const char *phy_mode; - int ret; phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); @@ -1044,9 +1047,11 @@ static int macb_eth_probe(struct udevice *dev) macb->regs = (void *)pdata->iobase; - ret = macb_enable_clk(dev); +#ifdef CONFIG_CLK + int ret = macb_enable_clk(dev); if (ret) return ret; +#endif _macb_eth_initialize(macb); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 4842a42896..357f8c2917 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -337,7 +337,7 @@ static int zynq_phy_init(struct udevice *dev) if (!priv->phydev) return -ENODEV; - priv->phydev->supported = supported | ADVERTISED_Pause | + priv->phydev->supported &= supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; priv->phydev->advertising = priv->phydev->supported; |