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-rw-r--r--drivers/net/sun8i_emac.c112
-rw-r--r--drivers/net/sunxi_emac.c28
-rw-r--r--drivers/net/zynq_gem.c53
3 files changed, 94 insertions, 99 deletions
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index c9798445c7..98bd7a5823 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -14,12 +14,14 @@
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <fdt_support.h>
#include <linux/err.h>
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
+#include <reset.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#ifdef CONFIG_DM_GPIO
#include <asm-generic/gpio.h>
@@ -135,6 +137,8 @@ struct emac_eth_dev {
phys_addr_t sysctl_reg;
struct phy_device *phydev;
struct mii_dev *bus;
+ struct clk tx_clk;
+ struct reset_ctl tx_rst;
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
@@ -285,10 +289,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
int ret;
u32 reg;
- reg = readl(priv->sysctl_reg + 0x30);
+ if (priv->variant == R40_GMAC) {
+ /* Select RGMII for R40 */
+ reg = readl(priv->sysctl_reg + 0x164);
+ reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII |
+ CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
- if (priv->variant == R40_GMAC)
+ writel(reg, priv->sysctl_reg + 0x164);
return 0;
+ }
+
+ reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == H3_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, &reg);
@@ -639,9 +651,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
return _sun8i_write_hwaddr(priv, pdata->enetaddr);
}
-static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int ret;
+
+ ret = clk_enable(&priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable TX clock\n");
+ return ret;
+ }
+
+ if (reset_valid(&priv->tx_rst)) {
+ ret = reset_deassert(&priv->tx_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert TX reset\n");
+ goto err_tx_clk;
+ }
+ }
if (priv->variant == H3_EMAC) {
/* Only H3/H5 have clock controls for internal EPHY */
@@ -656,26 +683,11 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
}
}
- if (priv->variant == R40_GMAC) {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
-
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
+ return 0;
- /* Select RGMII for R40 */
- setbits_le32(&ccm->gmac_clk_cfg,
- CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
- CCM_GMAC_CTRL_GPIT_RGMII);
- setbits_le32(&ccm->gmac_clk_cfg,
- CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
- } else {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
-
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
- }
+err_tx_clk:
+ clk_disable(&priv->tx_clk);
+ return ret;
}
#if defined(CONFIG_DM_GPIO)
@@ -802,10 +814,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->mac_reg = (void *)pdata->iobase;
- sun8i_emac_board_setup(priv);
+ ret = sun8i_emac_board_setup(priv);
+ if (ret)
+ return ret;
+
sun8i_emac_set_syscon(sun8i_pdata, priv);
sun8i_mdio_init(dev->name, dev);
@@ -834,8 +850,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
int offset = 0;
#ifdef CONFIG_DM_GPIO
int reset_flags = GPIOD_IS_OUT;
- int ret = 0;
#endif
+ int ret;
pdata->iobase = devfdt_get_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {
@@ -850,25 +866,35 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
}
- if (priv->variant != R40_GMAC) {
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
- if (offset < 0) {
- debug("%s: cannot find syscon node\n", __func__);
- return -EINVAL;
- }
- reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
- if (!reg) {
- debug("%s: cannot find reg property in syscon node\n",
- __func__);
- return -EINVAL;
- }
- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
- offset, reg);
- if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
- debug("%s: Cannot find syscon base address\n",
- __func__);
- return -EINVAL;
- }
+ ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to get TX clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "failed to get TX reset\n");
+ return ret;
+ }
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+ if (offset < 0) {
+ debug("%s: cannot find syscon node\n", __func__);
+ return -EINVAL;
+ }
+
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+ if (!reg) {
+ debug("%s: cannot find reg property in syscon node\n",
+ __func__);
+ return -EINVAL;
+ }
+ priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+ offset, reg);
+ if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find syscon base address\n", __func__);
+ return -EINVAL;
}
pdata->phy_interface = -1;
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 8dbd3c50c1..9a5f7fd3c7 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <linux/err.h>
#include <malloc.h>
@@ -157,6 +158,7 @@ struct sunxi_sramc_regs {
struct emac_eth_dev {
struct emac_regs *regs;
+ struct clk clk;
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
@@ -500,14 +502,12 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
return 0;
}
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
struct emac_regs *regs = priv->regs;
- int pin;
+ int pin, ret;
/* Map SRAM to EMAC */
setbits_le32(&sram->ctrl1, 0x5 << 2);
@@ -517,10 +517,16 @@ static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
/* Set up clock gating */
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+ ret = clk_enable(&priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable emac clock\n");
+ return ret;
+ }
/* Set MII clock */
clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
+
+ return 0;
}
static int sunxi_emac_eth_start(struct udevice *dev)
@@ -557,9 +563,19 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->regs = (struct emac_regs *)pdata->iobase;
- sunxi_emac_board_setup(priv);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to get emac clock\n");
+ return ret;
+ }
+
+ ret = sunxi_emac_board_setup(priv);
+ if (ret)
+ return ret;
return sunxi_emac_init_phy(priv, dev);
}
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3bd0093b7a..033efb8195 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -261,45 +261,6 @@ static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
}
-static int phy_detection(struct udevice *dev)
-{
- int i;
- u16 phyreg = 0;
- struct zynq_gem_priv *priv = dev->priv;
-
- if (priv->phyaddr != -1) {
- phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
- if ((phyreg != 0xFFFF) &&
- ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
- /* Found a valid PHY address */
- debug("Default phy address %d is valid\n",
- priv->phyaddr);
- return 0;
- } else {
- debug("PHY address is not setup correctly %d\n",
- priv->phyaddr);
- priv->phyaddr = -1;
- }
- }
-
- debug("detecting phy address\n");
- if (priv->phyaddr == -1) {
- /* detect the PHY address */
- for (i = 31; i >= 0; i--) {
- phyread(priv, i, PHY_DETECT_REG, &phyreg);
- if ((phyreg != 0xFFFF) &&
- ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
- /* Found a valid PHY address */
- priv->phyaddr = i;
- debug("Found valid phy address, %d\n", i);
- return 0;
- }
- }
- }
- printf("PHY is not detected\n");
- return -1;
-}
-
static int zynq_gem_setup_mac(struct udevice *dev)
{
u32 i, macaddrlow, macaddrhigh;
@@ -345,28 +306,20 @@ static int zynq_phy_init(struct udevice *dev)
/* Enable only MDIO bus */
writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
- if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
- (priv->interface != PHY_INTERFACE_MODE_GMII)) {
- ret = phy_detection(dev);
- if (ret) {
- printf("GEM PHY init failed\n");
- return ret;
- }
- }
-
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
if (!priv->phydev)
return -ENODEV;
- priv->phydev->supported &= supported | ADVERTISED_Pause |
- ADVERTISED_Asym_Pause;
if (priv->max_speed) {
ret = phy_set_supported(priv->phydev, priv->max_speed);
if (ret)
return ret;
}
+ priv->phydev->supported &= supported | ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause;
+
priv->phydev->advertising = priv->phydev->supported;
priv->phydev->node = priv->phy_of_node;
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 17:39:05 +0000