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-rw-r--r--drivers/net/Kconfig15
-rw-r--r--drivers/net/Makefile2
-rw-r--r--drivers/net/dwc_eth_qos.c35
-rw-r--r--drivers/net/dwc_eth_qos.h4
-rw-r--r--drivers/net/dwc_eth_qos_qcom.c612
-rw-r--r--drivers/net/fec_mxc.c92
-rw-r--r--drivers/net/fsl-mc/mc.c41
-rw-r--r--drivers/net/fsl_ls_mdio.c3
-rw-r--r--drivers/net/ftmac100.c119
-rw-r--r--drivers/net/ftmac100.h9
-rw-r--r--drivers/net/ksz9477.c23
-rw-r--r--drivers/net/mv88e6xxx.c755
-rw-r--r--drivers/net/ravb.c6
13 files changed, 1642 insertions, 74 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7873538cc2..ceadee98a1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -242,6 +242,13 @@ config DWC_ETH_QOS_TEGRA186
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in NVIDIA's Tegra186 chip.
+config DWC_ETH_QOS_QCOM
+ bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in Qcom QCS404 SoC.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
@@ -406,6 +413,7 @@ config FSL_FM_10GEC_REGULAR_NOTATION
config FTMAC100
bool "Ftmac100 Ethernet Support"
+ select MII
help
This MAC is present in Andestech SoCs.
@@ -473,6 +481,13 @@ config LITEETH
help
Driver for the LiteEth Ethernet MAC from LiteX.
+config MV88E6XXX
+ bool "Marvell MV88E6xxx Ethernet switch DSA driver"
+ depends on DM_DSA && DM_MDIO
+ help
+ This driver implements a DSA switch driver for the MV88E6xxx family
+ of Ethernet switches using the MDIO interface
+
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on ARCH_KIRKWOOD || ARCH_ORION5X
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5b4e60eea3..75daa5e694 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
+obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
@@ -60,6 +61,7 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o
obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
+obj-$(CONFIG_MV88E6XXX) += mv88e6xxx.o
obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVMDIO) += mvmdio.o
obj-$(CONFIG_MVNETA) += mvneta.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index afc47b56ff..112deb546d 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -774,10 +774,13 @@ static int eqos_start(struct udevice *dev)
pr_err("eqos_calibrate_pads() failed: %d", ret);
goto err_stop_resets;
}
- rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
- val = (rate / 1000000) - 1;
- writel(val, &eqos->mac_regs->us_tic_counter);
+ if (eqos->config->ops->eqos_get_tick_clk_rate) {
+ rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
+
+ val = (rate / 1000000) - 1;
+ writel(val, &eqos->mac_regs->us_tic_counter);
+ }
/*
* if PHY was already connected and configured,
@@ -849,12 +852,19 @@ static int eqos_start(struct udevice *dev)
rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
- /*
- * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
- * r/tqs is encoded as (n / 256) - 1.
- */
- tqs = (128 << tx_fifo_sz) / 256 - 1;
- rqs = (128 << rx_fifo_sz) / 256 - 1;
+ /* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */
+ tx_fifo_sz = 128 << tx_fifo_sz;
+ rx_fifo_sz = 128 << rx_fifo_sz;
+
+ /* Allow platform to override TX/RX fifo size */
+ if (eqos->tx_fifo_sz)
+ tx_fifo_sz = eqos->tx_fifo_sz;
+ if (eqos->rx_fifo_sz)
+ rx_fifo_sz = eqos->rx_fifo_sz;
+
+ /* r/tqs is encoded as (n / 256) - 1 */
+ tqs = tx_fifo_sz / 256 - 1;
+ rqs = rx_fifo_sz / 256 - 1;
clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
@@ -1702,6 +1712,13 @@ static const struct udevice_id eqos_ids[] = {
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
+ {
+ .compatible = "qcom,qcs404-ethqos",
+ .data = (ulong)&eqos_qcom_config
+ },
+#endif
+
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 8fccd6f057..fddbe9336c 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -253,6 +253,7 @@ struct eqos_priv {
struct eqos_mtl_regs *mtl_regs;
struct eqos_dma_regs *dma_regs;
struct eqos_tegra186_regs *tegra186_regs;
+ void *eqos_qcom_rgmii_regs;
struct reset_ctl reset_ctl;
struct gpio_desc phy_reset_gpio;
struct clk clk_master_bus;
@@ -276,6 +277,8 @@ struct eqos_priv {
bool started;
bool reg_access_ok;
bool clk_ck_enabled;
+ unsigned int tx_fifo_sz, rx_fifo_sz;
+ u32 reset_delays[3];
};
void eqos_inval_desc_generic(void *desc);
@@ -285,3 +288,4 @@ void eqos_flush_buffer_generic(void *buf, size_t size);
int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
+extern struct eqos_config eqos_qcom_config;
diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c
new file mode 100644
index 0000000000..df83f1c5f9
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_qcom.c
@@ -0,0 +1,612 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022-2023 Sumit Garg <sumit.garg@linaro.org>
+ *
+ * Qcom DWMAC specific glue layer
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include "dwc_eth_qos.h"
+
+/* RGMII_IO_MACRO_CONFIG fields */
+#define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
+#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
+#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
+#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
+#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
+#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
+#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
+#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
+#define RGMII_CONFIG_LOOPBACK_EN BIT(2)
+#define RGMII_CONFIG_PROG_SWAP BIT(1)
+#define RGMII_CONFIG_DDR_MODE BIT(0)
+
+/* SDCC_HC_REG_DLL_CONFIG fields */
+#define SDCC_DLL_CONFIG_DLL_RST BIT(30)
+#define SDCC_DLL_CONFIG_PDN BIT(29)
+#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
+#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
+#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
+#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
+#define SDCC_DLL_CONFIG_CDR_EN BIT(17)
+#define SDCC_DLL_CONFIG_DLL_EN BIT(16)
+#define SDCC_DLL_MCLK_GATING_EN BIT(5)
+#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2)
+
+/* SDCC_HC_REG_DDR_CONFIG fields */
+#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31)
+#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)
+#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)
+#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
+#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
+
+/* SDCC_HC_REG_DLL_CONFIG2 fields */
+#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21)
+#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10)
+#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2)
+#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1)
+#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0)
+
+/* SDC4_STATUS bits */
+#define SDC4_STATUS_DLL_LOCK BIT(7)
+
+/* RGMII_IO_MACRO_CONFIG2 fields */
+#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17)
+#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16)
+#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13)
+#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12)
+#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7)
+#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
+#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
+
+struct dwmac_rgmii_regs {
+ u32 io_macro_config; /* 0x00 */
+ u32 sdcc_hc_dll_config; /* 0x04 */
+ u32 reserved_1; /* 0x08 */
+ u32 sdcc_hc_ddr_config; /* 0x0c */
+ u32 sdcc_hc_dll_config2; /* 0x10 */
+ u32 sdc4_status; /* 0x14 */
+ u32 sdcc_usr_ctl; /* 0x18 */
+ u32 io_macro_config2; /* 0x1c */
+ u32 io_macro_debug1; /* 0x20 */
+ u32 reserved_2; /* 0x24 */
+ u32 emac_sys_low_power_dbg; /* 0x28 */
+ u32 reserved_3[53]; /* upto 0x100 */
+};
+
+static struct dwmac_rgmii_regs emac_v2_3_0_por = {
+ .io_macro_config = 0x00C01343,
+ .sdcc_hc_dll_config = 0x2004642C,
+ .sdcc_hc_ddr_config = 0x00000000,
+ .sdcc_hc_dll_config2 = 0x00200000,
+ .sdcc_usr_ctl = 0x00010800,
+ .io_macro_config2 = 0x00002060
+};
+
+static void ethqos_set_func_clk_en(struct dwmac_rgmii_regs *regs)
+{
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_FUNC_CLK_EN);
+}
+
+static int ethqos_dll_configure(struct udevice *dev,
+ struct dwmac_rgmii_regs *regs)
+{
+ unsigned int val;
+ int retry = 1000;
+
+ /* Set CDR_EN */
+ setbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EN);
+
+ /* Set CDR_EXT_EN */
+ setbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EXT_EN);
+
+ /* Clear CK_OUT_EN */
+ clrbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN);
+
+ /* Set DLL_EN */
+ setbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN);
+
+ clrbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_MCLK_GATING_EN);
+
+ clrbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CDR_FINE_PHASE);
+
+ /* Wait for CK_OUT_EN clear */
+ do {
+ val = readl(&regs->sdcc_hc_dll_config);
+ val &= SDCC_DLL_CONFIG_CK_OUT_EN;
+ if (!val)
+ break;
+ mdelay(1);
+ retry--;
+ } while (retry > 0);
+ if (!retry)
+ dev_err(dev, "Clear CK_OUT_EN timedout\n");
+
+ /* Set CK_OUT_EN */
+ setbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN);
+
+ /* Wait for CK_OUT_EN set */
+ retry = 1000;
+ do {
+ val = readl(&regs->sdcc_hc_dll_config);
+ val &= SDCC_DLL_CONFIG_CK_OUT_EN;
+ if (val)
+ break;
+ mdelay(1);
+ retry--;
+ } while (retry > 0);
+ if (!retry)
+ dev_err(dev, "Set CK_OUT_EN timedout\n");
+
+ /* Set DDR_CAL_EN */
+ setbits_le32(&regs->sdcc_hc_dll_config2, SDCC_DLL_CONFIG2_DDR_CAL_EN);
+
+ clrbits_le32(&regs->sdcc_hc_dll_config2,
+ SDCC_DLL_CONFIG2_DLL_CLOCK_DIS);
+
+ clrsetbits_le32(&regs->sdcc_hc_dll_config2,
+ SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 0x1A << 10);
+
+ clrsetbits_le32(&regs->sdcc_hc_dll_config2,
+ SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, BIT(2));
+
+ setbits_le32(&regs->sdcc_hc_dll_config2,
+ SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW);
+
+ return 0;
+}
+
+static int ethqos_rgmii_macro_init(struct udevice *dev,
+ struct dwmac_rgmii_regs *regs,
+ unsigned long speed)
+{
+ /* Disable loopback mode */
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN);
+
+ /* Select RGMII, write 0 to interface select */
+ clrbits_le32(&regs->io_macro_config, RGMII_CONFIG_INTF_SEL);
+
+ switch (speed) {
+ case SPEED_1000:
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_DDR_MODE);
+ clrbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_BYPASS_TX_ID_EN);
+ setbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_POS_NEG_DATA_SEL);
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_PROG_SWAP);
+
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL);
+ setbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN);
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_RSVD_CONFIG15);
+ setbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_RX_PROG_SWAP);
+
+ /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
+ clrsetbits_le32(&regs->sdcc_hc_ddr_config,
+ SDCC_DDR_CONFIG_PRG_RCLK_DLY, 57);
+ setbits_le32(&regs->sdcc_hc_ddr_config, SDCC_DDR_CONFIG_PRG_DLY_EN);
+
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
+ break;
+
+ case SPEED_100:
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_DDR_MODE);
+ setbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_BYPASS_TX_ID_EN);
+ clrbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_POS_NEG_DATA_SEL);
+ clrbits_le32(&regs->io_macro_config, RGMII_CONFIG_PROG_SWAP);
+ clrsetbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_MAX_SPD_PRG_2, BIT(6));
+
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL);
+ setbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN);
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_RSVD_CONFIG15);
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_RX_PROG_SWAP);
+
+ /* Write 0x5 to PRG_RCLK_DLY_CODE */
+ clrsetbits_le32(&regs->sdcc_hc_ddr_config,
+ SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+ (BIT(29) | BIT(27)));
+ setbits_le32(&regs->sdcc_hc_ddr_config,
+ SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY);
+ setbits_le32(&regs->sdcc_hc_ddr_config,
+ SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
+
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
+ break;
+
+ case SPEED_10:
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_DDR_MODE);
+ setbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_BYPASS_TX_ID_EN);
+ clrbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_POS_NEG_DATA_SEL);
+ clrbits_le32(&regs->io_macro_config, RGMII_CONFIG_PROG_SWAP);
+ clrsetbits_le32(&regs->io_macro_config,
+ RGMII_CONFIG_MAX_SPD_PRG_9,
+ BIT(12) | GENMASK(9, 8));
+
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL);
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN);
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_RSVD_CONFIG15);
+ clrbits_le32(&regs->io_macro_config2,
+ RGMII_CONFIG2_RX_PROG_SWAP);
+
+ /* Write 0x5 to PRG_RCLK_DLY_CODE */
+ clrsetbits_le32(&regs->sdcc_hc_ddr_config,
+ SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+ (BIT(29) | BIT(27)));
+ setbits_le32(&regs->sdcc_hc_ddr_config,
+ SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY);
+ setbits_le32(&regs->sdcc_hc_ddr_config,
+ SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
+
+ setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
+ break;
+
+ default:
+ dev_err(dev, "Invalid speed %ld\n", speed);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ethqos_configure(struct udevice *dev,
+ struct dwmac_rgmii_regs *regs,
+ unsigned long speed)
+{
+ unsigned int retry = 1000;
+
+ /* Reset to POR values and enable clk */
+ writel(emac_v2_3_0_por.io_macro_config, &regs->io_macro_config);
+ writel(emac_v2_3_0_por.sdcc_hc_dll_config, &regs->sdcc_hc_dll_config);
+ writel(emac_v2_3_0_por.sdcc_hc_ddr_config, &regs->sdcc_hc_ddr_config);
+ writel(emac_v2_3_0_por.sdcc_hc_dll_config2, &regs->sdcc_hc_dll_config2);
+ writel(emac_v2_3_0_por.sdcc_usr_ctl, &regs->sdcc_usr_ctl);
+ writel(emac_v2_3_0_por.io_macro_config2, &regs->io_macro_config2);
+
+ ethqos_set_func_clk_en(regs);
+
+ /* Initialize the DLL first */
+
+ /* Set DLL_RST */
+ setbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST);
+
+ /* Set PDN */
+ setbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN);
+
+ /* Clear DLL_RST */
+ clrbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST);
+
+ /* Clear PDN */
+ clrbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN);
+
+ if (speed == SPEED_1000) {
+ /* Set DLL_EN */
+ setbits_le32(&regs->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN);
+
+ /* Set CK_OUT_EN */
+ setbits_le32(&regs->sdcc_hc_dll_config,
+ SDCC_DLL_CONFIG_CK_OUT_EN);
+
+ /* Set USR_CTL bit 26 with mask of 3 bits */
+ clrsetbits_le32(&regs->sdcc_usr_ctl, GENMASK(26, 24), BIT(26));
+
+ /* wait for DLL LOCK */
+ do {
+ mdelay(1);
+ if (readl(&regs->sdc4_status) & SDC4_STATUS_DLL_LOCK)
+ break;
+ retry--;
+ } while (retry > 0);
+ if (!retry)
+ dev_err(dev, "Timeout while waiting for DLL lock\n");
+
+ ethqos_dll_configure(dev, regs);
+ }
+
+ ethqos_rgmii_macro_init(dev, regs, speed);
+
+ return 0;
+}
+
+static void ethqos_rgmii_dump(struct udevice *dev,
+ struct dwmac_rgmii_regs *regs)
+{
+ dev_dbg(dev, "Rgmii register dump\n");
+ dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %08x\n",
+ readl(&regs->io_macro_config));
+ dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %08x\n",
+ readl(&regs->sdcc_hc_dll_config));
+ dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %08x\n",
+ readl(&regs->sdcc_hc_ddr_config));
+ dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %08x\n",
+ readl(&regs->sdcc_hc_dll_config2));
+ dev_dbg(dev, "SDC4_STATUS: %08x\n",
+ readl(&regs->sdc4_status));
+ dev_dbg(dev, "SDCC_USR_CTL: %08x\n",
+ readl(&regs->sdcc_usr_ctl));
+ dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %08x\n",
+ readl(&regs->io_macro_config2));
+ dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %08x\n",
+ readl(&regs->io_macro_debug1));
+ dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %08x\n",
+ readl(&regs->emac_sys_low_power_dbg));
+}
+
+static int qcom_eqos_rgmii_set_speed(struct udevice *dev,
+ void *rgmii_regs,
+ unsigned long speed)
+{
+ int ret;
+
+ ethqos_rgmii_dump(dev, rgmii_regs);
+
+ ret = ethqos_configure(dev, rgmii_regs, speed);
+ if (ret)
+ return ret;
+
+ ethqos_rgmii_dump(dev, rgmii_regs);
+
+ return 0;
+}
+
+static int qcom_eqos_rgmii_reset(struct udevice *dev, void *rgmii_regs)
+{
+ ethqos_set_func_clk_en(rgmii_regs);
+
+ return 0;
+}
+
+static int eqos_start_clks_qcom(struct udevice *dev)
+{
+ if (IS_ENABLED(CONFIG_CLK)) {
+ struct clk_bulk clocks;
+ int ret;
+
+ ret = clk_get_bulk(dev, &clocks);
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(&clocks);
+ if (ret)
+ return ret;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_stop_clks_qcom(struct udevice *dev)
+{
+ if (IS_ENABLED(CONFIG_CLK)) {
+ struct clk_bulk clocks;
+ int ret;
+
+ ret = clk_get_bulk(dev, &clocks);
+ if (ret)
+ return ret;
+
+ ret = clk_disable_bulk(&clocks);
+ if (ret)
+ return ret;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_start_resets_qcom(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (!eqos->phy) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[0]);
+
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[1]);
+
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[2]);
+ }
+
+ ret = reset_deassert(&eqos->reset_ctl);
+ if (ret < 0) {
+ pr_err("reset_deassert() failed: %d", ret);
+ return ret;
+ }
+
+ ret = qcom_eqos_rgmii_reset(dev, eqos->eqos_qcom_rgmii_regs);
+ if (ret < 0) {
+ pr_err("qcom rgmii_reset failed: %d", ret);
+ return ret;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+/* Clock rates */
+#define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL)
+#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL)
+#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
+
+static int eqos_set_tx_clk_speed_qcom(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ ulong rate;
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ switch (eqos->phy->speed) {
+ case SPEED_1000:
+ rate = RGMII_1000_NOM_CLK_FREQ;
+ break;
+ case SPEED_100:
+ rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
+ break;
+ case SPEED_10:
+ rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
+ break;
+ default:
+ pr_err("invalid speed %d", eqos->phy->speed);
+ return -EINVAL;
+ }
+
+ ret = clk_set_rate(&eqos->clk_tx, rate);
+ if (ret < 0) {
+ pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
+ return ret;
+ }
+
+ ret = qcom_eqos_rgmii_set_speed(dev, eqos->eqos_qcom_rgmii_regs,
+ eqos->phy->speed);
+ if (ret < 0) {
+ pr_err("qcom set_speed: %d, failed: %d", eqos->phy->speed, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int eqos_probe_resources_qcom(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ phy_interface_t interface;
+ int reset_flags = GPIOD_IS_OUT;
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ interface = eqos->config->interface(dev);
+
+ if (interface == PHY_INTERFACE_MODE_NA) {
+ pr_err("Invalid PHY interface\n");
+ return -EINVAL;
+ }
+
+ eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+
+ eqos->tx_fifo_sz = dev_read_u32_default(dev, "tx-fifo-depth", 0);
+ eqos->rx_fifo_sz = dev_read_u32_default(dev, "rx-fifo-depth", 0);
+
+ ret = reset_get_by_name(dev, "emac", &eqos->reset_ctl);
+ if (ret) {
+ pr_err("reset_get_by_name(rst) failed: %d", ret);
+ return ret;
+ }
+
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+ if (ret == 0) {
+ ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+ eqos->reset_delays, 3);
+ } else if (ret == -ENOENT) {
+ ret = 0;
+ }
+
+ eqos->eqos_qcom_rgmii_regs = (void *)dev_read_addr_name(dev, "rgmii");
+ if ((fdt_addr_t)eqos->eqos_qcom_rgmii_regs == FDT_ADDR_T_NONE) {
+ pr_err("Invalid RGMII address\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_by_name(dev, "rgmii", &eqos->clk_tx);
+ if (ret) {
+ pr_err("clk_get_by_name(tx) failed: %d", ret);
+ return -EINVAL;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_remove_resources_qcom(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clk_free(&eqos->clk_tx);
+ dm_gpio_free(dev, &eqos->phy_reset_gpio);
+ reset_free(&eqos->reset_ctl);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static struct eqos_ops eqos_qcom_ops = {
+ .eqos_inval_desc = eqos_inval_desc_generic,
+ .eqos_flush_desc = eqos_flush_desc_generic,
+ .eqos_inval_buffer = eqos_inval_buffer_generic,
+ .eqos_flush_buffer = eqos_flush_buffer_generic,
+ .eqos_probe_resources = eqos_probe_resources_qcom,
+ .eqos_remove_resources = eqos_remove_resources_qcom,
+ .eqos_stop_resets = eqos_null_ops,
+ .eqos_start_resets = eqos_start_resets_qcom,
+ .eqos_stop_clks = eqos_stop_clks_qcom,
+ .eqos_start_clks = eqos_start_clks_qcom,
+ .eqos_calibrate_pads = eqos_null_ops,
+ .eqos_disable_calibration = eqos_null_ops,
+ .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_qcom,
+ .eqos_get_enetaddr = eqos_null_ops,
+};
+
+struct eqos_config __maybe_unused eqos_qcom_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 10,
+ .swr_wait = 50,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+ .axi_bus_width = EQOS_AXI_WIDTH_64,
+ .interface = dev_read_phy_mode,
+ .ops = &eqos_qcom_ops
+};
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 006d27051e..1a6c18a441 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -30,6 +30,8 @@
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm-generic/gpio.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
#include "fec_mxc.h"
#include <eth_phy.h>
@@ -1019,6 +1021,81 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
return bus;
}
+#ifdef CONFIG_DM_MDIO
+struct dm_fec_mdio_priv {
+ struct ethernet_regs *regs;
+};
+
+static int dm_fec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ return fec_mdio_read(priv->regs, addr, reg);
+}
+
+static int dm_fec_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 data)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ return fec_mdio_write(priv->regs, addr, reg, data);
+}
+
+static const struct mdio_ops dm_fec_mdio_ops = {
+ .read = dm_fec_mdio_read,
+ .write = dm_fec_mdio_write,
+};
+
+static int dm_fec_mdio_probe(struct udevice *dev)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct ethernet_regs *)ofnode_get_addr(dev_ofnode(dev->parent));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(fec_mdio) = {
+ .name = "fec_mdio",
+ .id = UCLASS_MDIO,
+ .probe = dm_fec_mdio_probe,
+ .ops = &dm_fec_mdio_ops,
+ .priv_auto = sizeof(struct dm_fec_mdio_priv),
+};
+
+static int dm_fec_bind_mdio(struct udevice *dev)
+{
+ struct udevice *mdiodev;
+ const char *name;
+ ofnode mdio;
+ int ret = -ENODEV;
+
+ /* for a UCLASS_MDIO driver we need to bind and probe manually
+ * for an internal MDIO bus that has no dt compatible of its own
+ */
+ ofnode_for_each_subnode(mdio, dev_ofnode(dev)) {
+ name = ofnode_get_name(mdio);
+
+ if (strcmp(name, "mdio"))
+ continue;
+
+ ret = device_bind_driver_to_node(dev, "fec_mdio",
+ name, mdio, &mdiodev);
+ if (ret) {
+ printf("%s bind %s failed: %d\n", __func__, name, ret);
+ break;
+ }
+
+ /* need to probe it as there is no compatible to do so */
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdiodev);
+ if (!ret)
+ return 0;
+ printf("%s probe %s failed: %d\n", __func__, name, ret);
+ }
+
+ return ret;
+}
+#endif
+
static int fecmxc_read_rom_hwaddr(struct udevice *dev)
{
struct fec_priv *priv = dev_get_priv(dev);
@@ -1082,7 +1159,7 @@ static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
{
- struct phy_device *phydev;
+ struct phy_device *phydev = NULL;
int addr;
addr = device_get_phy_addr(priv, dev);
@@ -1090,7 +1167,10 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
addr = CFG_FEC_MXC_PHYADDR;
#endif
- phydev = phy_connect(priv->bus, addr, dev, priv->interface);
+ if (IS_ENABLED(CONFIG_DM_MDIO))
+ phydev = dm_eth_phy_connect(dev);
+ if (!phydev)
+ phydev = phy_connect(priv->bus, addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
@@ -1125,7 +1205,7 @@ static int fecmxc_probe(struct udevice *dev)
uint32_t start;
int ret;
- if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+ if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
if (enet_fused((ulong)priv->eth)) {
printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
return -ENODEV;
@@ -1221,6 +1301,12 @@ static int fecmxc_probe(struct udevice *dev)
priv->dev_id = dev_seq(dev);
+#ifdef CONFIG_DM_MDIO
+ ret = dm_fec_bind_mdio(dev);
+ if (ret && ret != -ENODEV)
+ return ret;
+#endif
+
#ifdef CONFIG_DM_ETH_PHY
bus = eth_phy_get_mdio_bus(dev);
#endif
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 6b36860187..4f84403d95 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -356,8 +356,7 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
if (noff < 0) {
err = fdt_increase_size(blob, 200);
if (err) {
- printf("fdt_increase_size: err=%s\n",
- fdt_strerror(err));
+ printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
return err;
}
@@ -373,7 +372,7 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
"link_type", link_type_mode);
if (err) {
printf("fdt_appendprop_string: err=%s\n",
- fdt_strerror(err));
+ fdt_strerror(err));
return err;
}
}
@@ -527,7 +526,6 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
return 0;
}
-
static int mc_fixup_dpl(u64 dpl_addr)
{
void *blob = (void *)dpl_addr;
@@ -699,7 +697,6 @@ static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
printf("SUCCESS\n");
}
-
*final_reg_gsr = reg_gsr;
return 0;
}
@@ -812,7 +809,7 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
* Initialize the global default MC portal
* And check that the MC firmware is responding portal commands:
*/
- root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
+ root_mc_io = calloc(sizeof(struct fsl_mc_io), 1);
if (!root_mc_io) {
printf(" No memory: calloc() failed\n");
return -ENOMEM;
@@ -979,8 +976,7 @@ static int dpio_init(void)
int err = 0;
uint16_t major_ver, minor_ver;
- dflt_dpio = (struct fsl_dpio_obj *)calloc(
- sizeof(struct fsl_dpio_obj), 1);
+ dflt_dpio = calloc(sizeof(struct fsl_dpio_obj), 1);
if (!dflt_dpio) {
printf("No memory: calloc() failed\n");
err = -ENOMEM;
@@ -1038,7 +1034,7 @@ static int dpio_init(void)
}
#ifdef DEBUG
- printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+ printf("Init: DPIO.%d\n", dflt_dpio->dpio_id);
#endif
err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
if (err < 0) {
@@ -1107,7 +1103,7 @@ static int dpio_exit(void)
}
#ifdef DEBUG
- printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+ printf("Exit: DPIO.%d\n", dflt_dpio->dpio_id);
#endif
if (dflt_dpio)
@@ -1159,16 +1155,15 @@ static int dprc_init(void)
cfg.icid = DPRC_GET_ICID_FROM_POOL;
cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL;
err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
- root_dprc_handle,
- &cfg,
- &child_dprc_id,
- &mc_portal_offset);
+ root_dprc_handle, &cfg,
+ &child_dprc_id,
+ &mc_portal_offset);
if (err < 0) {
printf("dprc_create_container() failed: %d\n", err);
goto err_create;
}
- dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
+ dflt_mc_io = calloc(sizeof(struct fsl_mc_io), 1);
if (!dflt_mc_io) {
err = -ENOMEM;
printf(" No memory: calloc() failed\n");
@@ -1250,8 +1245,7 @@ static int dpbp_init(void)
struct dpbp_cfg dpbp_cfg;
uint16_t major_ver, minor_ver;
- dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
- sizeof(struct fsl_dpbp_obj), 1);
+ dflt_dpbp = calloc(sizeof(struct fsl_dpbp_obj), 1);
if (!dflt_dpbp) {
printf("No memory: calloc() failed\n");
err = -ENOMEM;
@@ -1312,7 +1306,7 @@ static int dpbp_init(void)
}
#ifdef DEBUG
- printf("Init: DPBP id=0x%x\n", dflt_dpbp->dpbp_attr.id);
+ printf("Init: DPBP.%d\n", dflt_dpbp->dpbp_attr.id);
#endif
err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
@@ -1351,7 +1345,7 @@ static int dpbp_exit(void)
}
#ifdef DEBUG
- printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
+ printf("Exit: DPBP.%d\n", dflt_dpbp->dpbp_attr.id);
#endif
if (dflt_dpbp)
@@ -1369,8 +1363,7 @@ static int dpni_init(void)
struct dpni_cfg dpni_cfg;
uint16_t major_ver, minor_ver;
- dflt_dpni = (struct fsl_dpni_obj *)calloc(
- sizeof(struct fsl_dpni_obj), 1);
+ dflt_dpni = calloc(sizeof(struct fsl_dpni_obj), 1);
if (!dflt_dpni) {
printf("No memory: calloc() failed\n");
err = -ENOMEM;
@@ -1422,7 +1415,7 @@ static int dpni_init(void)
}
#ifdef DEBUG
- printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+ printf("Init: DPNI.%d\n", dflt_dpni->dpni_id);
#endif
err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
@@ -1459,7 +1452,7 @@ static int dpni_exit(void)
}
#ifdef DEBUG
- printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+ printf("Exit: DPNI.%d\n", dflt_dpni->dpni_id);
#endif
if (dflt_dpni)
@@ -1796,7 +1789,6 @@ static void mc_dump_log(void)
if (size > bytes_end) {
print_k_bytes(cur_ptr, &bytes_end);
- cur_ptr = buf;
size -= bytes_end;
}
@@ -1962,7 +1954,6 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc,
default:
printf("Invalid option: %s\n", argv[1]);
goto usage;
- break;
}
return err;
usage:
diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c
index f213e0dd85..fce7393750 100644
--- a/drivers/net/fsl_ls_mdio.c
+++ b/drivers/net/fsl_ls_mdio.c
@@ -124,6 +124,9 @@ static int fsl_ls_mdio_probe(struct udevice *dev)
struct memac_mdio_controller *regs;
priv->regs_base = dev_read_addr_ptr(dev);
+ if (!priv->regs_base)
+ return -ENODEV;
+
regs = (struct memac_mdio_controller *)(priv->regs_base);
memac_setbits_32(&regs->mdio_stat,
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index f710c271c6..fae3adc3de 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -12,9 +12,13 @@
#include <env.h>
#include <malloc.h>
#include <net.h>
+#include <phy.h>
+#include <miiphy.h>
+#include <dm/device_compat.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include "ftmac100.h"
#include <dm.h>
@@ -23,12 +27,16 @@ DECLARE_GLOBAL_DATA_PTR;
#define ETH_ZLEN 60
+/* Timeout for a mdio read/write operation */
+#define FTMAC100_MDIO_TIMEOUT_USEC 10000
+
struct ftmac100_data {
struct ftmac100_txdes txdes[1];
struct ftmac100_rxdes rxdes[PKTBUFSRX];
int rx_index;
const char *name;
- phys_addr_t iobase;
+ struct ftmac100 *ftmac100;
+ struct mii_dev *bus;
};
/*
@@ -36,7 +44,7 @@ struct ftmac100_data {
*/
static void ftmac100_reset(struct ftmac100_data *priv)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
+ struct ftmac100 *ftmac100 = priv->ftmac100;
debug ("%s()\n", __func__);
@@ -57,7 +65,7 @@ static void ftmac100_reset(struct ftmac100_data *priv)
static void ftmac100_set_mac(struct ftmac100_data *priv ,
const unsigned char *mac)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
+ struct ftmac100 *ftmac100 = priv->ftmac100;
unsigned int maddr = mac[0] << 8 | mac[1];
unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
@@ -72,7 +80,7 @@ static void ftmac100_set_mac(struct ftmac100_data *priv ,
*/
static void _ftmac100_halt(struct ftmac100_data *priv)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
+ struct ftmac100 *ftmac100 = priv->ftmac100;
debug ("%s()\n", __func__);
writel (0, &ftmac100->maccr);
}
@@ -82,7 +90,7 @@ static void _ftmac100_halt(struct ftmac100_data *priv)
*/
static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6])
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
+ struct ftmac100 *ftmac100 = priv->ftmac100;
struct ftmac100_txdes *txdes = priv->txdes;
struct ftmac100_rxdes *rxdes = priv->rxdes;
unsigned int maccr;
@@ -187,7 +195,7 @@ static int __ftmac100_recv(struct ftmac100_data *priv)
*/
static int _ftmac100_send(struct ftmac100_data *priv, void *packet, int length)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
+ struct ftmac100 *ftmac100 = priv->ftmac100;
struct ftmac100_txdes *curr_des = priv->txdes;
ulong start;
@@ -314,7 +322,7 @@ static int ftmac100_of_to_plat(struct udevice *dev)
struct eth_pdata *pdata = dev_get_plat(dev);
const char *mac;
pdata->iobase = dev_read_addr(dev);
- priv->iobase = pdata->iobase;
+ priv->ftmac100 = phys_to_virt(pdata->iobase);
mac = dtbmacaddr(0);
if (mac)
memcpy(pdata->enetaddr , mac , 6);
@@ -322,10 +330,104 @@ static int ftmac100_of_to_plat(struct udevice *dev)
return 0;
}
+/*
+ * struct mii_bus functions
+ */
+static int ftmac100_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int reg)
+{
+ struct ftmac100_data *priv = bus->priv;
+ struct ftmac100 *ftmac100 = priv->ftmac100;
+ int phycr = FTMAC100_PHYCR_PHYAD(addr) |
+ FTMAC100_PHYCR_REGAD(reg) |
+ FTMAC100_PHYCR_MIIRD;
+ int ret;
+
+ writel(phycr, &ftmac100->phycr);
+
+ ret = readl_poll_timeout(&ftmac100->phycr, phycr,
+ !(phycr & FTMAC100_PHYCR_MIIRD),
+ FTMAC100_MDIO_TIMEOUT_USEC);
+ if (ret)
+ pr_err("%s: mdio read failed (addr=0x%x reg=0x%x)\n",
+ bus->name, addr, reg);
+ else
+ ret = phycr & FTMAC100_PHYCR_MIIRDATA;
+
+ return ret;
+}
+
+static int ftmac100_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 value)
+{
+ struct ftmac100_data *priv = bus->priv;
+ struct ftmac100 *ftmac100 = priv->ftmac100;
+ int phycr = FTMAC100_PHYCR_PHYAD(addr) |
+ FTMAC100_PHYCR_REGAD(reg) |
+ FTMAC100_PHYCR_MIIWR;
+ int ret;
+
+ writel(value, &ftmac100->phywdata);
+ writel(phycr, &ftmac100->phycr);
+
+ ret = readl_poll_timeout(&ftmac100->phycr, phycr,
+ !(phycr & FTMAC100_PHYCR_MIIWR),
+ FTMAC100_MDIO_TIMEOUT_USEC);
+ if (ret)
+ pr_err("%s: mdio write failed (addr=0x%x reg=0x%x)\n",
+ bus->name, addr, reg);
+
+ return ret;
+}
+
+static int ftmac100_mdio_init(struct udevice *dev)
+{
+ struct ftmac100_data *priv = dev_get_priv(dev);
+ struct mii_dev *bus;
+ int ret;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return -ENOMEM;
+
+ bus->read = ftmac100_mdio_read;
+ bus->write = ftmac100_mdio_write;
+ bus->priv = priv;
+
+ ret = mdio_register_seq(bus, dev_seq(dev));
+ if (ret) {
+ mdio_free(bus);
+ return ret;
+ }
+
+ priv->bus = bus;
+
+ return 0;
+}
+
static int ftmac100_probe(struct udevice *dev)
{
struct ftmac100_data *priv = dev_get_priv(dev);
priv->name = dev->name;
+ int ret = 0;
+
+ ret = ftmac100_mdio_init(dev);
+ if (ret) {
+ dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
+ goto out;
+ }
+
+out:
+ return ret;
+}
+
+static int ftmac100_remove(struct udevice *dev)
+{
+ struct ftmac100_data *priv = dev_get_priv(dev);
+
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
return 0;
}
@@ -348,12 +450,13 @@ static const struct udevice_id ftmac100_ids[] = {
};
U_BOOT_DRIVER(ftmac100) = {
- .name = "nds32_mac",
+ .name = "ftmac100",
.id = UCLASS_ETH,
.of_match = ftmac100_ids,
.bind = ftmac100_bind,
.of_to_plat = ftmac100_of_to_plat,
.probe = ftmac100_probe,
+ .remove = ftmac100_remove,
.ops = &ftmac100_ops,
.priv_auto = sizeof(struct ftmac100_data),
.plat_auto = sizeof(struct eth_pdata),
diff --git a/drivers/net/ftmac100.h b/drivers/net/ftmac100.h
index 75a49f628a..21d339f835 100644
--- a/drivers/net/ftmac100.h
+++ b/drivers/net/ftmac100.h
@@ -93,6 +93,15 @@ struct ftmac100 {
#define FTMAC100_MACCR_RX_BROADPKT (1 << 17)
/*
+ * PHY control register
+ */
+#define FTMAC100_PHYCR_MIIRDATA 0xffff
+#define FTMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
+#define FTMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
+#define FTMAC100_PHYCR_MIIWR BIT(27)
+#define FTMAC100_PHYCR_MIIRD BIT(26)
+
+/*
* Transmit descriptor, aligned to 16 bytes
*/
struct ftmac100_txdes {
diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c
index ed8f1895cb..fb5c76c600 100644
--- a/drivers/net/ksz9477.c
+++ b/drivers/net/ksz9477.c
@@ -62,7 +62,6 @@
struct ksz_dsa_priv {
struct udevice *dev;
- int active_port;
};
static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
@@ -382,9 +381,6 @@ static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy
data8 |= SW_START;
ksz_write8(priv->dev, REG_SW_OPERATION, data8);
- /* keep track of current enabled non-cpu port */
- priv->active_port = port;
-
return 0;
}
@@ -413,28 +409,9 @@ static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *p
*/
}
-static int ksz_xmit(struct udevice *dev, int port, void *packet, int length)
-{
- dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length);
-
- return 0;
-}
-
-static int ksz_recv(struct udevice *dev, int *port, void *packet, int length)
-{
- struct ksz_dsa_priv *priv = dev_get_priv(dev);
-
- dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length);
- *port = priv->active_port;
-
- return 0;
-};
-
static const struct dsa_ops ksz_dsa_ops = {
.port_enable = ksz_port_enable,
.port_disable = ksz_port_disable,
- .xmit = ksz_xmit,
- .rcv = ksz_recv,
};
static int ksz_probe_mdio(struct udevice *dev)
diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c
new file mode 100644
index 0000000000..64e860e324
--- /dev/null
+++ b/drivers/net/mv88e6xxx.c
@@ -0,0 +1,755 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022
+ * Gateworks Corporation <www.gateworks.com>
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * (C) Copyright 2015
+ * Elecsys Corporation <www.elecsyscorp.com>
+ * Kevin Smith <kevin.smith@elecsyscorp.com>
+ *
+ * Original driver:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+/*
+ * DSA driver for mv88e6xxx ethernet switches.
+ *
+ * This driver configures the mv88e6xxx for basic use as a DSA switch.
+ *
+ * This driver was adapted from drivers/net/phy/mv88e61xx and tested
+ * on the mv88e6176 via an SGMII interface.
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/of_extra.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <net/dsa.h>
+
+/* Device addresses */
+#define DEVADDR_PHY(p) (p)
+#define DEVADDR_SERDES 0x0F
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG 0x00
+#define SMI_DATA_REG 0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS 0x00
+#define GLOBAL1_CTRL 0x04
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD 0x18
+#define GLOBAL2_REG_PHY_DATA 0x19
+#define GLOBAL2_REG_SCRATCH 0x1A
+
+/* Port registers */
+#define PORT_REG_STATUS 0x00
+#define PORT_REG_PHYS_CTRL 0x01
+#define PORT_REG_SWITCH_ID 0x03
+#define PORT_REG_CTRL 0x04
+
+/* Phy registers */
+#define PHY_REG_PAGE 0x16
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER 0
+#define PHY_PAGE_SERDES 1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET BIT(15)
+
+#define PORT_REG_STATUS_SPEED_SHIFT 8
+#define PORT_REG_STATUS_SPEED_10 0
+#define PORT_REG_STATUS_SPEED_100 1
+#define PORT_REG_STATUS_SPEED_1000 2
+
+#define PORT_REG_STATUS_CMODE_MASK 0xF
+#define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
+#define PORT_REG_STATUS_CMODE_100BASE_X 0x8
+#define PORT_REG_STATUS_CMODE_RGMII 0x7
+#define PORT_REG_STATUS_CMODE_RMII 0x5
+#define PORT_REG_STATUS_CMODE_RMII_PHY 0x4
+#define PORT_REG_STATUS_CMODE_GMII 0x3
+#define PORT_REG_STATUS_CMODE_MII 0x2
+#define PORT_REG_STATUS_CMODE_MIIPHY 0x1
+
+#define PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK BIT(15)
+#define PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK BIT(14)
+#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
+#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
+#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
+#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
+#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
+#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
+#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
+#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
+#define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
+#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
+
+#define PORT_REG_CTRL_PSTATE_SHIFT 0
+#define PORT_REG_CTRL_PSTATE_MASK 3
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED 0
+#define PORT_REG_CTRL_PSTATE_FORWARD 3
+
+/*
+ * Macros for building commands for indirect addressing modes. These are valid
+ * for both the indirect multichip addressing mode and the PHY indirection
+ * required for the writes to any PHY register.
+ */
+#define SMI_BUSY BIT(15)
+#define SMI_CMD_CLAUSE_22 BIT(12)
+#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
+#define SMI_CMD_ADDR_SHIFT 5
+#define SMI_CMD_ADDR_MASK 0x1f
+#define SMI_CMD_REG_SHIFT 0
+#define SMI_CMD_REG_MASK 0x1f
+#define SMI_CMD_READ(addr, reg) \
+ (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \
+ (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
+ (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
+#define SMI_CMD_WRITE(addr, reg) \
+ (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \
+ (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
+ (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
+
+/* ID register values for different switch models */
+#define PORT_SWITCH_ID_6020 0x0200
+#define PORT_SWITCH_ID_6070 0x0700
+#define PORT_SWITCH_ID_6071 0x0710
+#define PORT_SWITCH_ID_6096 0x0980
+#define PORT_SWITCH_ID_6097 0x0990
+#define PORT_SWITCH_ID_6172 0x1720
+#define PORT_SWITCH_ID_6176 0x1760
+#define PORT_SWITCH_ID_6220 0x2200
+#define PORT_SWITCH_ID_6240 0x2400
+#define PORT_SWITCH_ID_6250 0x2500
+#define PORT_SWITCH_ID_6320 0x1150
+#define PORT_SWITCH_ID_6352 0x3520
+
+struct mv88e6xxx_priv {
+ int smi_addr;
+ int id;
+ int port_count; /* Number of switch ports */
+ int port_reg_base; /* Base of the switch port registers */
+ u8 global1; /* Offset of Switch Global 1 registers */
+ u8 global2; /* Offset of Switch Global 2 registers */
+};
+
+/* Wait for the current SMI indirect command to complete */
+static int mv88e6xxx_smi_wait(struct udevice *dev, int smi_addr)
+{
+ int val;
+ u32 timeout = 100;
+
+ do {
+ val = dm_mdio_read(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
+ if (val >= 0 && (val & SMI_BUSY) == 0)
+ return 0;
+
+ mdelay(1);
+ } while (--timeout);
+
+ dev_err(dev, "SMI busy timeout\n");
+ return -ETIMEDOUT;
+}
+
+/*
+ * The mv88e6xxx has three types of addresses: the smi bus address, the device
+ * address, and the register address. The smi bus address distinguishes it on
+ * the smi bus from other PHYs or switches. The device address determines
+ * which on-chip register set you are reading/writing (the various PHYs, their
+ * associated ports, or global configuration registers). The register address
+ * is the offset of the register you are reading/writing.
+ *
+ * When the mv88e6xxx is hardware configured to have address zero, it behaves in
+ * single-chip addressing mode, where it responds to all SMI addresses, using
+ * the smi address as its device address. This obviously only works when this
+ * is the only chip on the SMI bus. This allows the driver to access device
+ * registers without using indirection. When the chip is configured to a
+ * non-zero address, it only responds to that SMI address and requires indirect
+ * writes to access the different device addresses.
+ */
+static int mv88e6xxx_reg_read(struct udevice *dev, int addr, int reg)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int smi_addr = priv->smi_addr;
+ int res;
+
+ /* In single-chip mode, the device can be addressed directly */
+ if (smi_addr == 0)
+ return dm_mdio_read(dev->parent, addr, MDIO_DEVAD_NONE, reg);
+
+ /* Wait for the bus to become free */
+ res = mv88e6xxx_smi_wait(dev, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Issue the read command */
+ res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+ SMI_CMD_READ(addr, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for the read command to complete */
+ res = mv88e6xxx_smi_wait(dev, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Read the data */
+ res = dm_mdio_read(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
+ if (res < 0)
+ return res;
+
+ return res & 0xffff;
+}
+
+/* See the comment above mv88e6xxx_reg_read */
+static int mv88e6xxx_reg_write(struct udevice *dev, int addr, int reg, u16 val)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int smi_addr = priv->smi_addr;
+ int res;
+
+ /* In single-chip mode, the device can be addressed directly */
+ if (smi_addr == 0)
+ return dm_mdio_write(dev->parent, addr, MDIO_DEVAD_NONE, reg, val);
+
+ /* Wait for the bus to become free */
+ res = mv88e6xxx_smi_wait(dev, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Set the data to write */
+ res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE,
+ SMI_DATA_REG, val);
+ if (res < 0)
+ return res;
+
+ /* Issue the write command */
+ res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+ SMI_CMD_WRITE(addr, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for the write command to complete */
+ res = mv88e6xxx_smi_wait(dev, smi_addr);
+ if (res < 0)
+ return res;
+
+ return 0;
+}
+
+static int mv88e6xxx_phy_wait(struct udevice *dev)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int val;
+ u32 timeout = 100;
+
+ do {
+ val = mv88e6xxx_reg_read(dev, priv->global2, GLOBAL2_REG_PHY_CMD);
+ if (val >= 0 && (val & SMI_BUSY) == 0)
+ return 0;
+
+ mdelay(1);
+ } while (--timeout);
+
+ return -ETIMEDOUT;
+}
+
+static int mv88e6xxx_phy_read_indirect(struct udevice *dev, int phyad, int devad, int reg)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int res;
+
+ /* Issue command to read */
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_READ(phyad, reg));
+
+ /* Wait for data to be read */
+ res = mv88e6xxx_phy_wait(dev);
+ if (res < 0)
+ return res;
+
+ /* Read retrieved data */
+ return mv88e6xxx_reg_read(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA);
+}
+
+static int mv88e6xxx_phy_write_indirect(struct udevice *dev, int phyad,
+ int devad, int reg, u16 data)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int res;
+
+ /* Set the data to write */
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA, data);
+ if (res < 0)
+ return res;
+ /* Issue the write command */
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_WRITE(phyad, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for command to complete */
+ return mv88e6xxx_phy_wait(dev);
+}
+
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e6xxx_phy_read(struct udevice *dev, int phy, int reg)
+{
+ return mv88e6xxx_phy_read_indirect(dev, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg);
+}
+
+/* Wrapper function to make calls to phy_write_indirect simpler */
+static int mv88e6xxx_phy_write(struct udevice *dev, int phy, int reg, u16 val)
+{
+ return mv88e6xxx_phy_write_indirect(dev, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg, val);
+}
+
+static int mv88e6xxx_port_read(struct udevice *dev, u8 port, u8 reg)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+
+ return mv88e6xxx_reg_read(dev, priv->port_reg_base + port, reg);
+}
+
+static int mv88e6xxx_port_write(struct udevice *dev, u8 port, u8 reg, u16 val)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+
+ return mv88e6xxx_reg_write(dev, priv->port_reg_base + port, reg, val);
+}
+
+static int mv88e6xxx_set_page(struct udevice *dev, u8 phy, u8 page)
+{
+ return mv88e6xxx_phy_write(dev, phy, PHY_REG_PAGE, page);
+}
+
+static int mv88e6xxx_get_switch_id(struct udevice *dev)
+{
+ int res;
+
+ res = mv88e6xxx_port_read(dev, 0, PORT_REG_SWITCH_ID);
+ if (res < 0) {
+ dev_err(dev, "Failed to read switch ID: %d\n", res);
+ return res;
+ }
+ return res & 0xfff0;
+}
+
+static bool mv88e6xxx_6352_family(struct udevice *dev)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+
+ switch (priv->id) {
+ case PORT_SWITCH_ID_6172:
+ case PORT_SWITCH_ID_6176:
+ case PORT_SWITCH_ID_6240:
+ case PORT_SWITCH_ID_6352:
+ return true;
+ }
+ return false;
+}
+
+static int mv88e6xxx_get_cmode(struct udevice *dev, u8 port)
+{
+ int res;
+
+ res = mv88e6xxx_port_read(dev, port, PORT_REG_STATUS);
+ if (res < 0)
+ return res;
+ return res & PORT_REG_STATUS_CMODE_MASK;
+}
+
+static int mv88e6xxx_switch_reset(struct udevice *dev)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int time_ms;
+ int val;
+ u8 port;
+
+ /* Disable all ports */
+ for (port = 0; port < priv->port_count; port++) {
+ val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL);
+ if (val < 0)
+ return val;
+ val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT);
+ val |= (PORT_REG_CTRL_PSTATE_DISABLED << PORT_REG_CTRL_PSTATE_SHIFT);
+ val = mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val);
+ if (val < 0)
+ return val;
+ }
+
+ /* Wait 2 ms for queues to drain */
+ udelay(2000);
+
+ /* Reset switch */
+ val = mv88e6xxx_reg_read(dev, priv->global1, GLOBAL1_CTRL);
+ if (val < 0)
+ return val;
+ val |= GLOBAL1_CTRL_SWRESET;
+ val = mv88e6xxx_reg_write(dev, priv->global1, GLOBAL1_CTRL, val);
+ if (val < 0)
+ return val;
+
+ /* Wait up to 1 second for switch to reset complete */
+ for (time_ms = 1000; time_ms; time_ms--) {
+ val = mv88e6xxx_reg_read(dev, priv->global1, GLOBAL1_CTRL);
+ if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
+ break;
+ udelay(1000);
+ }
+ if (!time_ms)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int mv88e6xxx_serdes_init(struct udevice *dev)
+{
+ int val;
+
+ val = mv88e6xxx_set_page(dev, DEVADDR_SERDES, PHY_PAGE_SERDES);
+ if (val < 0)
+ return val;
+
+ /* Power up serdes module */
+ val = mv88e6xxx_phy_read(dev, DEVADDR_SERDES, MII_BMCR);
+ if (val < 0)
+ return val;
+ val &= ~(BMCR_PDOWN);
+ val = mv88e6xxx_phy_write(dev, DEVADDR_SERDES, MII_BMCR, val);
+ if (val < 0)
+ return val;
+
+ return 0;
+}
+
+/*
+ * This function is used to pre-configure the required register
+ * offsets, so that the indirect register access to the PHY registers
+ * is possible. This is necessary to be able to read the PHY ID
+ * while driver probing or in get_phy_id(). The globalN register
+ * offsets must be initialized correctly for a detected switch,
+ * otherwise detection of the PHY ID won't work!
+ */
+static int mv88e6xxx_priv_reg_offs_pre_init(struct udevice *dev)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+
+ /*
+ * Initial 'port_reg_base' value must be an offset of existing
+ * port register, then reading the ID should succeed. First, try
+ * to read via port registers with device address 0x10 (88E6096
+ * and compatible switches).
+ */
+ priv->port_reg_base = 0x10;
+ priv->id = mv88e6xxx_get_switch_id(dev);
+ if (priv->id != 0xfff0) {
+ priv->global1 = 0x1B;
+ priv->global2 = 0x1C;
+ return 0;
+ }
+
+ /*
+ * Now try via port registers with device address 0x08
+ * (88E6020 and compatible switches).
+ */
+ priv->port_reg_base = 0x08;
+ priv->id = mv88e6xxx_get_switch_id(dev);
+ if (priv->id != 0xfff0) {
+ priv->global1 = 0x0F;
+ priv->global2 = 0x07;
+ return 0;
+ }
+
+ dev_warn(dev, "%s Unknown ID 0x%x\n", __func__, priv->id);
+
+ return -ENODEV;
+}
+
+static int mv88e6xxx_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ return mv88e6xxx_phy_read_indirect(dev->parent, DEVADDR_PHY(addr),
+ MDIO_DEVAD_NONE, reg);
+}
+
+static int mv88e6xxx_mdio_write(struct udevice *dev, int addr, int devad,
+ int reg, u16 val)
+{
+ return mv88e6xxx_phy_write_indirect(dev->parent, DEVADDR_PHY(addr),
+ MDIO_DEVAD_NONE, reg, val);
+}
+
+static const struct mdio_ops mv88e6xxx_mdio_ops = {
+ .read = mv88e6xxx_mdio_read,
+ .write = mv88e6xxx_mdio_write,
+};
+
+static int mv88e6xxx_mdio_bind(struct udevice *dev)
+{
+ char name[32];
+ static int num_devices;
+
+ sprintf(name, "mv88e6xxx-mdio-%d", num_devices++);
+ device_set_name(dev, name);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(mv88e6xxx_mdio) = {
+ .name = "mv88e6xxx_mdio",
+ .id = UCLASS_MDIO,
+ .ops = &mv88e6xxx_mdio_ops,
+ .bind = mv88e6xxx_mdio_bind,
+ .plat_auto = sizeof(struct mdio_perdev_priv),
+};
+
+static int mv88e6xxx_port_probe(struct udevice *dev, int port, struct phy_device *phy)
+{
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int supported;
+
+ switch (priv->id) {
+ case PORT_SWITCH_ID_6020:
+ case PORT_SWITCH_ID_6070:
+ case PORT_SWITCH_ID_6071:
+ supported = PHY_BASIC_FEATURES | SUPPORTED_MII;
+ break;
+ default:
+ supported = PHY_GBIT_FEATURES;
+ break;
+ }
+
+ phy->supported &= supported;
+ phy->advertising &= supported;
+
+ return phy_config(phy);
+}
+
+static int mv88e6xxx_port_enable(struct udevice *dev, int port, struct phy_device *phy)
+{
+ int val, ret;
+
+ dev_dbg(dev, "%s P%d phy:0x%08x %s\n", __func__, port,
+ phy->phy_id, phy_string_for_interface(phy->interface));
+
+ if (phy->phy_id == PHY_FIXED_ID) {
+ /* Physical Control register: Table 62 */
+ val = mv88e6xxx_port_read(dev, port, PORT_REG_PHYS_CTRL);
+
+ /* configure RGMII delays for fixed link */
+ switch (phy->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ dev_dbg(dev, "configure internal RGMII delays\n");
+
+ /* RGMII delays */
+ val &= ~(PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK ||
+ PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK);
+ if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phy->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ val |= PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK;
+ if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phy->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ val |= PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK;
+ break;
+ default:
+ break;
+ }
+
+ /* Force Link */
+ val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
+ PORT_REG_PHYS_CTRL_LINK_FORCE;
+
+ ret = mv88e6xxx_port_write(dev, port, PORT_REG_PHYS_CTRL, val);
+ if (ret < 0)
+ return ret;
+
+ if (mv88e6xxx_6352_family(dev)) {
+ /* validate interface type */
+ dev_dbg(dev, "validate interface type\n");
+ val = mv88e6xxx_get_cmode(dev, port);
+ if (val < 0)
+ return val;
+ switch (phy->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ if (val != PORT_REG_STATUS_CMODE_RGMII)
+ goto mismatch;
+ break;
+ case PHY_INTERFACE_MODE_1000BASEX:
+ if (val != PORT_REG_STATUS_CMODE_1000BASE_X)
+ goto mismatch;
+ break;
+mismatch:
+ default:
+ dev_err(dev, "Mismatched PHY mode %s on port %d!\n",
+ phy_string_for_interface(phy->interface), port);
+ break;
+ }
+ }
+ }
+
+ /* enable port */
+ val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL);
+ if (val < 0)
+ return val;
+ val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT);
+ val |= (PORT_REG_CTRL_PSTATE_FORWARD << PORT_REG_CTRL_PSTATE_SHIFT);
+ val = mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val);
+ if (val < 0)
+ return val;
+
+ return phy_startup(phy);
+}
+
+static void mv88e6xxx_port_disable(struct udevice *dev, int port, struct phy_device *phy)
+{
+ int val;
+
+ dev_dbg(dev, "%s P%d phy:0x%08x %s\n", __func__, port,
+ phy->phy_id, phy_string_for_interface(phy->interface));
+
+ val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL);
+ val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT);
+ val |= (PORT_REG_CTRL_PSTATE_DISABLED << PORT_REG_CTRL_PSTATE_SHIFT);
+ mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val);
+}
+
+static const struct dsa_ops mv88e6xxx_dsa_ops = {
+ .port_probe = mv88e6xxx_port_probe,
+ .port_enable = mv88e6xxx_port_enable,
+ .port_disable = mv88e6xxx_port_disable,
+};
+
+/* bind and probe the switch mdios */
+static int mv88e6xxx_probe_mdio(struct udevice *dev)
+{
+ struct udevice *mdev;
+ const char *name;
+ ofnode node;
+ int ret;
+
+ /* bind phy ports of mdio child node to mv88e6xxx_mdio device */
+ node = dev_read_subnode(dev, "mdio");
+ if (!ofnode_valid(node))
+ return 0;
+
+ name = ofnode_get_name(node);
+ ret = device_bind_driver_to_node(dev,
+ "mv88e6xxx_mdio",
+ name, node, NULL);
+ if (ret) {
+ dev_err(dev, "failed to bind %s: %d\n", name, ret);
+ } else {
+ /* need to probe it as there is no compatible to do so */
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, node, &mdev);
+ if (ret)
+ dev_err(dev, "failed to probe %s: %d\n", name, ret);
+ }
+
+ return ret;
+}
+
+static int mv88e6xxx_probe(struct udevice *dev)
+{
+ struct dsa_pdata *dsa_pdata = dev_get_uclass_plat(dev);
+ struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ int val, ret;
+
+ if (ofnode_valid(dev_ofnode(dev)) &&
+ !ofnode_is_enabled(dev_ofnode(dev))) {
+ dev_dbg(dev, "switch disabled\n");
+ return -ENODEV;
+ }
+
+ /* probe internal mdio bus */
+ ret = mv88e6xxx_probe_mdio(dev);
+ if (ret)
+ return ret;
+
+ ret = mv88e6xxx_priv_reg_offs_pre_init(dev);
+ if (ret)
+ return ret;
+
+ dev_dbg(dev, "ID=0x%x PORT_BASE=0x%02x GLOBAL1=0x%02x GLOBAL2=0x%02x\n",
+ priv->id, priv->port_reg_base, priv->global1, priv->global2);
+ switch (priv->id) {
+ case PORT_SWITCH_ID_6096:
+ case PORT_SWITCH_ID_6097:
+ case PORT_SWITCH_ID_6172:
+ case PORT_SWITCH_ID_6176:
+ case PORT_SWITCH_ID_6240:
+ case PORT_SWITCH_ID_6352:
+ priv->port_count = 11;
+ break;
+ case PORT_SWITCH_ID_6020:
+ case PORT_SWITCH_ID_6070:
+ case PORT_SWITCH_ID_6071:
+ case PORT_SWITCH_ID_6220:
+ case PORT_SWITCH_ID_6250:
+ case PORT_SWITCH_ID_6320:
+ priv->port_count = 7;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ ret = mv88e6xxx_switch_reset(dev);
+ if (ret < 0)
+ return ret;
+
+ if (mv88e6xxx_6352_family(dev)) {
+ val = mv88e6xxx_get_cmode(dev, dsa_pdata->cpu_port);
+ if (val < 0)
+ return val;
+ /* initialize serdes */
+ if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
+ val == PORT_REG_STATUS_CMODE_1000BASE_X ||
+ val == PORT_REG_STATUS_CMODE_SGMII) {
+ ret = mv88e6xxx_serdes_init(dev);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mv88e6xxx_ids[] = {
+ { .compatible = "marvell,mv88e6085" },
+ { }
+};
+
+U_BOOT_DRIVER(mv88e6xxx) = {
+ .name = "mv88e6xxx",
+ .id = UCLASS_DSA,
+ .of_match = mv88e6xxx_ids,
+ .probe = mv88e6xxx_probe,
+ .ops = &mv88e6xxx_dsa_ops,
+ .priv_auto = sizeof(struct mv88e6xxx_priv),
+};
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index c28680565f..5a835cc06f 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -693,12 +693,6 @@ int ravb_of_to_plat(struct udevice *dev)
}
static const struct udevice_id ravb_ids[] = {
- { .compatible = "renesas,etheravb-r8a7795" },
- { .compatible = "renesas,etheravb-r8a7796" },
- { .compatible = "renesas,etheravb-r8a77965" },
- { .compatible = "renesas,etheravb-r8a77970" },
- { .compatible = "renesas,etheravb-r8a77990" },
- { .compatible = "renesas,etheravb-r8a77995" },
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ }
};