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-rw-r--r--drivers/net/Kconfig11
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/designware.c1
-rw-r--r--drivers/net/dwc_eth_qos.c28
-rw-r--r--drivers/net/fsl-mc/Kconfig25
-rw-r--r--drivers/net/fsl_enetc_mdio.c1
-rw-r--r--drivers/net/macb.c8
-rw-r--r--drivers/net/mdio_mux_i2creg.c108
-rw-r--r--drivers/net/mdio_sandbox.c4
-rw-r--r--drivers/net/mvmdio.c236
-rw-r--r--drivers/net/mvpp2.c8
-rw-r--r--drivers/net/pfe_eth/pfe_mdio.c3
12 files changed, 407 insertions, 27 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 084e095229..2ce3092db0 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,5 +1,6 @@
source "drivers/net/phy/Kconfig"
source "drivers/net/pfe_eth/Kconfig"
+source "drivers/net/fsl-mc/Kconfig"
config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
@@ -603,4 +604,14 @@ config MDIO_MUX_I2CREG
an I2C chip. The board it was developed for uses a mux controlled by
on-board FPGA which in turn is accessed as a chip over I2C.
+config MVMDIO
+ bool "Marvell MDIO interface support"
+ depends on DM_MDIO
+ help
+ This driver supports the MDIO interface found in the network
+ interface units of the Marvell EBU SoCs (Kirkwood, Orion5x,
+ Dove, Armada 370, Armada XP, Armada 37xx and Armada7K/8K/8KP).
+
+ This driver is used by the MVPP2 and MVNETA drivers.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 71c0889355..30991834ec 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
obj-$(CONFIG_MVGBE) += mvgbe.o
+obj-$(CONFIG_MVMDIO) += mvmdio.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index c4fe40b19a..145eeac45f 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -847,7 +847,6 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "allwinner,sun7i-a20-gmac" },
- { .compatible = "altr,socfpga-stmmac" },
{ .compatible = "amlogic,meson6-dwmac" },
{ .compatible = "amlogic,meson-gx-dwmac" },
{ .compatible = "amlogic,meson-gxbb-dwmac" },
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 07b36675a7..455709338c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -621,7 +621,7 @@ err:
return ret;
}
-void eqos_stop_clks_tegra186(struct udevice *dev)
+static void eqos_stop_clks_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -636,7 +636,7 @@ void eqos_stop_clks_tegra186(struct udevice *dev)
debug("%s: OK\n", __func__);
}
-void eqos_stop_clks_stm32(struct udevice *dev)
+static void eqos_stop_clks_stm32(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1290,7 +1290,7 @@ err:
return ret;
}
-void eqos_stop(struct udevice *dev)
+static void eqos_stop(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int i;
@@ -1344,7 +1344,7 @@ void eqos_stop(struct udevice *dev)
debug("%s: OK\n", __func__);
}
-int eqos_send(struct udevice *dev, void *packet, int length)
+static int eqos_send(struct udevice *dev, void *packet, int length)
{
struct eqos_priv *eqos = dev_get_priv(dev);
struct eqos_desc *tx_desc;
@@ -1385,7 +1385,7 @@ int eqos_send(struct udevice *dev, void *packet, int length)
return -ETIMEDOUT;
}
-int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
+static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct eqos_priv *eqos = dev_get_priv(dev);
struct eqos_desc *rx_desc;
@@ -1409,7 +1409,7 @@ int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
return length;
}
-int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
+static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct eqos_priv *eqos = dev_get_priv(dev);
uchar *packet_expected;
@@ -1591,8 +1591,8 @@ err_free_reset_eqos:
}
/* board-specific Ethernet Interface initializations. */
-__weak int board_interface_eth_init(int interface_type, bool eth_clk_sel_reg,
- bool eth_ref_clk_sel_reg)
+__weak int board_interface_eth_init(struct udevice *dev,
+ phy_interface_t interface_type)
{
return 0;
}
@@ -1602,8 +1602,6 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
phy_interface_t interface;
- bool eth_clk_sel_reg = false;
- bool eth_ref_clk_sel_reg = false;
debug("%s(dev=%p):\n", __func__, dev);
@@ -1614,15 +1612,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
return -EINVAL;
}
- /* Gigabit Ethernet 125MHz clock selection. */
- eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
-
- /* Ethernet 50Mhz RMII clock selection */
- eth_ref_clk_sel_reg =
- dev_read_bool(dev, "st,eth_ref_clk_sel");
-
- ret = board_interface_eth_init(interface, eth_clk_sel_reg,
- eth_ref_clk_sel_reg);
+ ret = board_interface_eth_init(dev, interface);
if (ret)
return -EINVAL;
diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig
new file mode 100644
index 0000000000..25a2cb8ffa
--- /dev/null
+++ b/drivers/net/fsl-mc/Kconfig
@@ -0,0 +1,25 @@
+#
+# NXP Management Complex
+#
+
+menuconfig FSL_MC_ENET
+ bool "NXP Management Complex"
+ depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+ default y
+ select RESV_RAM
+ help
+ Enable Management Complex (MC) network
+ This is NXP Management Complex menuconfig
+ that contains all MC related config options
+
+if FSL_MC_ENET
+
+config SYS_MC_RSV_MEM_ALIGN
+ hex "Management Complex reserved memory alignment"
+ depends on RESV_RAM
+ default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+ help
+ Reserved memory needs to be aligned for MC to use. Default value
+ is 512MB.
+
+endif # FSL_MC_ENET
diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c
index 60d21537b8..b4463a58a5 100644
--- a/drivers/net/fsl_enetc_mdio.c
+++ b/drivers/net/fsl_enetc_mdio.c
@@ -144,6 +144,7 @@ U_BOOT_DRIVER(enetc_mdio) = {
static struct pci_device_id enetc_mdio_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_MDIO) },
+ { }
};
U_BOOT_PCI_DEVICE(enetc_mdio, enetc_mdio_ids);
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index c99cf663a4..377188e361 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -296,13 +296,15 @@ static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
static inline void macb_flush_rx_buffer(struct macb_device *macb)
{
flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
- ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
+ ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
+ PKTALIGN));
}
static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
{
invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
- ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
+ ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
+ PKTALIGN));
}
#if defined(CONFIG_CMD_NET)
@@ -643,7 +645,7 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
/* First check for GMAC and that it is GiB capable */
if (gem_is_gigabit_capable(macb)) {
- lpa = macb_mdio_read(macb, MII_LPA);
+ lpa = macb_mdio_read(macb, MII_STAT1000);
if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
LPA_1000XHALF)) {
diff --git a/drivers/net/mdio_mux_i2creg.c b/drivers/net/mdio_mux_i2creg.c
new file mode 100644
index 0000000000..3e82898f46
--- /dev/null
+++ b/drivers/net/mdio_mux_i2creg.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <i2c.h>
+
+/*
+ * This driver is used for MDIO muxes driven by writing to a register of an I2C
+ * chip. The board it was developed for uses a mux controlled by on-board FPGA
+ * which in turn is accessed as a chip over I2C.
+ */
+
+struct mdio_mux_i2creg_priv {
+ struct udevice *chip;
+ int reg;
+ int mask;
+};
+
+static int mdio_mux_i2creg_select(struct udevice *mux, int cur, int sel)
+{
+ struct mdio_mux_i2creg_priv *priv = dev_get_priv(mux);
+ u8 val, val_old;
+
+ /* if last selection didn't change we're good to go */
+ if (cur == sel)
+ return 0;
+
+ val_old = dm_i2c_reg_read(priv->chip, priv->reg);
+ val = (val_old & ~priv->mask) | (sel & priv->mask);
+ debug("%s: chip %s, reg %x, val %x => %x\n", __func__, priv->chip->name,
+ priv->reg, val_old, val);
+ dm_i2c_reg_write(priv->chip, priv->reg, val);
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_i2creg_ops = {
+ .select = mdio_mux_i2creg_select,
+};
+
+static int mdio_mux_i2creg_probe(struct udevice *dev)
+{
+ struct mdio_mux_i2creg_priv *priv = dev_get_priv(dev);
+ ofnode chip_node, bus_node;
+ struct udevice *i2c_bus;
+ u32 reg_mask[2];
+ u32 chip_addr;
+ int err;
+
+ /* read the register addr/mask pair */
+ err = dev_read_u32_array(dev, "mux-reg-masks", reg_mask, 2);
+ if (err) {
+ debug("%s: error reading mux-reg-masks property\n", __func__);
+ return err;
+ }
+
+ /* parent should be an I2C chip, grandparent should be an I2C bus */
+ chip_node = ofnode_get_parent(dev->node);
+ bus_node = ofnode_get_parent(chip_node);
+
+ err = uclass_get_device_by_ofnode(UCLASS_I2C, bus_node, &i2c_bus);
+ if (err) {
+ debug("%s: can't find I2C bus for node %s\n", __func__,
+ ofnode_get_name(bus_node));
+ return err;
+ }
+
+ err = ofnode_read_u32(chip_node, "reg", &chip_addr);
+ if (err) {
+ debug("%s: can't read chip address in %s\n", __func__,
+ ofnode_get_name(chip_node));
+ return err;
+ }
+
+ err = i2c_get_chip(i2c_bus, (uint)chip_addr, 1, &priv->chip);
+ if (err) {
+ debug("%s: can't find i2c chip device for addr %x\n", __func__,
+ chip_addr);
+ return err;
+ }
+
+ priv->reg = (int)reg_mask[0];
+ priv->mask = (int)reg_mask[1];
+
+ debug("%s: chip %s, reg %x, mask %x\n", __func__, priv->chip->name,
+ priv->reg, priv->mask);
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_i2creg_ids[] = {
+ { .compatible = "mdio-mux-i2creg" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_i2creg) = {
+ .name = "mdio_mux_i2creg",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_i2creg_ids,
+ .probe = mdio_mux_i2creg_probe,
+ .ops = &mdio_mux_i2creg_ops,
+ .priv_auto_alloc_size = sizeof(struct mdio_mux_i2creg_priv),
+};
diff --git a/drivers/net/mdio_sandbox.c b/drivers/net/mdio_sandbox.c
index df053f5381..b731f60a98 100644
--- a/drivers/net/mdio_sandbox.c
+++ b/drivers/net/mdio_sandbox.c
@@ -27,7 +27,7 @@ static int mdio_sandbox_read(struct udevice *dev, int addr, int devad, int reg)
return -ENODEV;
if (devad != MDIO_DEVAD_NONE)
return -ENODEV;
- if (reg < 0 || reg > SANDBOX_PHY_REG_CNT)
+ if (reg < 0 || reg >= SANDBOX_PHY_REG_CNT)
return -ENODEV;
return priv->reg[reg];
@@ -45,7 +45,7 @@ static int mdio_sandbox_write(struct udevice *dev, int addr, int devad, int reg,
return -ENODEV;
if (devad != MDIO_DEVAD_NONE)
return -ENODEV;
- if (reg < 0 || reg > SANDBOX_PHY_REG_CNT)
+ if (reg < 0 || reg >= SANDBOX_PHY_REG_CNT)
return -ENODEV;
priv->reg[reg] = val;
diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c
new file mode 100644
index 0000000000..ec6805e536
--- /dev/null
+++ b/drivers/net/mvmdio.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ * Author: Ken Ma<make@marvell.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <wait_bit.h>
+
+#define MVMDIO_SMI_DATA_SHIFT 0
+#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
+#define MVMDIO_SMI_PHY_REG_SHIFT 21
+#define MVMDIO_SMI_READ_OPERATION BIT(26)
+#define MVMDIO_SMI_WRITE_OPERATION 0
+#define MVMDIO_SMI_READ_VALID BIT(27)
+#define MVMDIO_SMI_BUSY BIT(28)
+
+#define MVMDIO_XSMI_MGNT_REG 0x0
+#define MVMDIO_XSMI_PHYADDR_SHIFT 16
+#define MVMDIO_XSMI_DEVADDR_SHIFT 21
+#define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
+#define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
+#define MVMDIO_XSMI_READ_VALID BIT(29)
+#define MVMDIO_XSMI_BUSY BIT(30)
+#define MVMDIO_XSMI_ADDR_REG 0x8
+
+enum mvmdio_bus_type {
+ BUS_TYPE_SMI,
+ BUS_TYPE_XSMI
+};
+
+struct mvmdio_priv {
+ void *mdio_base;
+ enum mvmdio_bus_type type;
+};
+
+static int mvmdio_smi_read(struct udevice *dev, int addr,
+ int devad, int reg)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ u32 val;
+ int ret;
+
+ if (devad != MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
+ (reg << MVMDIO_SMI_PHY_REG_SHIFT) |
+ MVMDIO_SMI_READ_OPERATION),
+ priv->mdio_base);
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ val = readl(priv->mdio_base);
+ if (!(val & MVMDIO_SMI_READ_VALID)) {
+ pr_err("SMI bus read not valid\n");
+ return -ENODEV;
+ }
+
+ return val & GENMASK(15, 0);
+}
+
+static int mvmdio_smi_write(struct udevice *dev, int addr, int devad,
+ int reg, u16 value)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (devad != MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
+ (reg << MVMDIO_SMI_PHY_REG_SHIFT) |
+ MVMDIO_SMI_WRITE_OPERATION |
+ (value << MVMDIO_SMI_DATA_SHIFT)),
+ priv->mdio_base);
+
+ return 0;
+}
+
+static int mvmdio_xsmi_read(struct udevice *dev, int addr,
+ int devad, int reg)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (devad == MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
+ writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
+ (devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
+ MVMDIO_XSMI_READ_OPERATION),
+ priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ if (!(readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) &
+ MVMDIO_XSMI_READ_VALID)) {
+ pr_err("XSMI bus read not valid\n");
+ return -ENODEV;
+ }
+
+ return readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
+}
+
+static int mvmdio_xsmi_write(struct udevice *dev, int addr, int devad,
+ int reg, u16 value)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (devad == MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
+ writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
+ (devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
+ MVMDIO_XSMI_WRITE_OPERATION | value),
+ priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
+
+ return 0;
+}
+
+static int mvmdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int err = -ENOTSUPP;
+
+ switch (priv->type) {
+ case BUS_TYPE_SMI:
+ err = mvmdio_smi_read(dev, addr, devad, reg);
+ break;
+ case BUS_TYPE_XSMI:
+ err = mvmdio_xsmi_read(dev, addr, devad, reg);
+ break;
+ }
+
+ return err;
+}
+
+static int mvmdio_write(struct udevice *dev, int addr, int devad, int reg,
+ u16 value)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int err = -ENOTSUPP;
+
+ switch (priv->type) {
+ case BUS_TYPE_SMI:
+ err = mvmdio_smi_write(dev, addr, devad, reg, value);
+ break;
+ case BUS_TYPE_XSMI:
+ err = mvmdio_xsmi_write(dev, addr, devad, reg, value);
+ break;
+ }
+
+ return err;
+}
+
+/*
+ * Name the device, we use the device tree node name.
+ * This can be overwritten by MDIO class code if device-name property is
+ * present.
+ */
+static int mvmdio_bind(struct udevice *dev)
+{
+ if (ofnode_valid(dev->node))
+ device_set_name(dev, ofnode_get_name(dev->node));
+
+ return 0;
+}
+
+/* Get device base address and type, either C22 SMII or C45 XSMI */
+static int mvmdio_probe(struct udevice *dev)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+
+ priv->mdio_base = (void *)dev_read_addr(dev);
+ priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
+
+ return 0;
+}
+
+static const struct mdio_ops mvmdio_ops = {
+ .read = mvmdio_read,
+ .write = mvmdio_write,
+};
+
+static const struct udevice_id mvmdio_ids[] = {
+ { .compatible = "marvell,orion-mdio", .data = BUS_TYPE_SMI },
+ { .compatible = "marvell,xmdio", .data = BUS_TYPE_XSMI },
+ { }
+};
+
+U_BOOT_DRIVER(mvmdio) = {
+ .name = "mvmdio",
+ .id = UCLASS_MDIO,
+ .of_match = mvmdio_ids,
+ .bind = mvmdio_bind,
+ .probe = mvmdio_probe,
+ .ops = &mvmdio_ops,
+ .priv_auto_alloc_size = sizeof(struct mvmdio_priv),
+};
+
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index bcc6fe92a9..bd89725e77 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5321,6 +5321,13 @@ static void mvpp2_stop(struct udevice *dev)
mvpp2_cleanup_txqs(port);
}
+static int mvpp2_write_hwaddr(struct udevice *dev)
+{
+ struct mvpp2_port *port = dev_get_priv(dev);
+
+ return mvpp2_prs_update_mac_da(port, port->dev_addr);
+}
+
static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
{
writel(port->phyaddr, port->priv->iface_base +
@@ -5525,6 +5532,7 @@ static const struct eth_ops mvpp2_ops = {
.send = mvpp2_send,
.recv = mvpp2_recv,
.stop = mvpp2_stop,
+ .write_hwaddr = mvpp2_write_hwaddr
};
static struct driver mvpp2_driver = {
diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
index 2dde9e7ac8..62309670fa 100644
--- a/drivers/net/pfe_eth/pfe_mdio.c
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -110,7 +110,6 @@ static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
u32 phy;
u32 reg_data;
int timeout = MDIO_TIMEOUT;
- int val;
if (dev_addr == MDIO_DEVAD_NONE) {
reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
@@ -150,7 +149,7 @@ static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
reg_addr, data);
- return val;
+ return 0;
}
static void pfe_configure_serdes(struct pfe_eth_dev *priv)