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-rw-r--r--drivers/mtd/cfi_flash.c2
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/atmel_nand.c198
-rw-r--r--drivers/mtd/nand/fsl_elbc_spl.c27
-rw-r--r--drivers/mtd/nand/nand_util.c3
-rw-r--r--drivers/mtd/spi/Makefile1
-rw-r--r--drivers/mtd/spi/atmel.c10
-rw-r--r--drivers/mtd/spi/eon.c3
-rw-r--r--drivers/mtd/spi/fsl_espi_spl.c62
-rw-r--r--drivers/mtd/spi/gigadevice.c2
-rw-r--r--drivers/mtd/spi/ramtron.c8
-rw-r--r--drivers/mtd/spi/spansion.c5
-rw-r--r--drivers/mtd/spi/spi_flash.c13
-rw-r--r--drivers/mtd/spi/spi_spl_load.c2
-rw-r--r--drivers/mtd/spi/sst.c40
-rw-r--r--drivers/mtd/spi/stmicro.c12
-rw-r--r--drivers/mtd/spi/winbond.c2
17 files changed, 332 insertions, 59 deletions
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index a37663eeb4..a389cd101c 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -1803,7 +1803,7 @@ static int flash_detect_legacy(phys_addr_t base, int banknum)
break;
else
unmap_physmem((void *)info->start[0],
- MAP_NOCACHE);
+ info->portwidth);
}
}
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index e27e0b7050..366dee6670 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -23,6 +23,7 @@ COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
+COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o
else # not spl
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index f844990e38..96aca00ebc 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -16,6 +16,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
+#include <malloc.h>
#include <nand.h>
#include <watchdog.h>
@@ -50,13 +51,13 @@ struct atmel_nand_host {
void __iomem *pmecc_index_of;
/* data for pmecc computation */
- int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
- int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
- int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
- int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
- int pmecc_mu[CONFIG_PMECC_CAP + 1];
- int pmecc_dmu[CONFIG_PMECC_CAP + 1];
- int pmecc_delta[CONFIG_PMECC_CAP + 1];
+ int16_t *pmecc_smu;
+ int16_t *pmecc_partial_syn;
+ int16_t *pmecc_si;
+ int16_t *pmecc_lmu; /* polynomal order */
+ int *pmecc_mu;
+ int *pmecc_dmu;
+ int *pmecc_delta;
};
static struct atmel_nand_host pmecc_host;
@@ -109,6 +110,48 @@ static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
table_size * sizeof(int16_t);
}
+static void pmecc_data_free(struct atmel_nand_host *host)
+{
+ free(host->pmecc_partial_syn);
+ free(host->pmecc_si);
+ free(host->pmecc_lmu);
+ free(host->pmecc_smu);
+ free(host->pmecc_mu);
+ free(host->pmecc_dmu);
+ free(host->pmecc_delta);
+}
+
+static int pmecc_data_alloc(struct atmel_nand_host *host)
+{
+ const int cap = host->pmecc_corr_cap;
+ int size;
+
+ size = (2 * cap + 1) * sizeof(int16_t);
+ host->pmecc_partial_syn = malloc(size);
+ host->pmecc_si = malloc(size);
+ host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
+ host->pmecc_smu = malloc((cap + 2) * size);
+
+ size = (cap + 1) * sizeof(int);
+ host->pmecc_mu = malloc(size);
+ host->pmecc_dmu = malloc(size);
+ host->pmecc_delta = malloc(size);
+
+ if (host->pmecc_partial_syn &&
+ host->pmecc_si &&
+ host->pmecc_lmu &&
+ host->pmecc_smu &&
+ host->pmecc_mu &&
+ host->pmecc_dmu &&
+ host->pmecc_delta)
+ return 0;
+
+ /* error happened */
+ pmecc_data_free(host);
+ return -ENOMEM;
+
+}
+
static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
{
struct nand_chip *nand_chip = mtd->priv;
@@ -622,6 +665,99 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
}
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+/*
+ * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
+ * @ecc_bits: store the ONFI ECC correct bits capbility
+ * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
+ *
+ * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
+ * @sector_size are initialize to 0.
+ * Return 0 if success to get the ECC requirement.
+ */
+static int get_onfi_ecc_param(struct nand_chip *chip,
+ int *ecc_bits, int *sector_size)
+{
+ *ecc_bits = *sector_size = 0;
+
+ if (chip->onfi_params.ecc_bits == 0xff)
+ /* TODO: the sector_size and ecc_bits need to be find in
+ * extended ecc parameter, currently we don't support it.
+ */
+ return -1;
+
+ *ecc_bits = chip->onfi_params.ecc_bits;
+
+ /* The default sector size (ecc codeword size) is 512 */
+ *sector_size = 512;
+
+ return 0;
+}
+
+/*
+ * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
+ * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
+ * ONFI ECC parameters.
+ * @host: point to an atmel_nand_host structure.
+ * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
+ * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
+ * @chip: point to an nand_chip structure.
+ * @cap: store the ONFI ECC correct bits capbility
+ * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
+ *
+ * Return 0 if success. otherwise return the error code.
+ */
+static int pmecc_choose_ecc(struct atmel_nand_host *host,
+ struct nand_chip *chip,
+ int *cap, int *sector_size)
+{
+ /* Get ECC requirement from ONFI parameters */
+ *cap = *sector_size = 0;
+ if (chip->onfi_version) {
+ if (!get_onfi_ecc_param(chip, cap, sector_size)) {
+ MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
+ *cap, *sector_size);
+ } else {
+ dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
+ }
+ } else {
+ dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
+ }
+ if (*cap == 0 && *sector_size == 0) {
+ /* Non-ONFI compliant or use extended ONFI parameters */
+ *cap = 2;
+ *sector_size = 512;
+ }
+
+ /* If head file doesn't specify then use the one in ONFI parameters */
+ if (host->pmecc_corr_cap == 0) {
+ /* use the most fitable ecc bits (the near bigger one ) */
+ if (*cap <= 2)
+ host->pmecc_corr_cap = 2;
+ else if (*cap <= 4)
+ host->pmecc_corr_cap = 4;
+ else if (*cap <= 8)
+ host->pmecc_corr_cap = 8;
+ else if (*cap <= 12)
+ host->pmecc_corr_cap = 12;
+ else if (*cap <= 24)
+ host->pmecc_corr_cap = 24;
+ else
+ return -EINVAL;
+ }
+ if (host->pmecc_sector_size == 0) {
+ /* use the most fitable sector size (the near smaller one ) */
+ if (*sector_size >= 1024)
+ host->pmecc_sector_size = 1024;
+ else if (*sector_size >= 512)
+ host->pmecc_sector_size = 512;
+ else
+ return -EINVAL;
+ }
+ return 0;
+}
+#endif
+
static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
struct mtd_info *mtd)
{
@@ -635,9 +771,45 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
nand->ecc.correct = NULL;
nand->ecc.hwctl = NULL;
- cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP;
- sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
- host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+ host->pmecc_corr_cap = host->pmecc_sector_size = 0;
+
+#ifdef CONFIG_PMECC_CAP
+ host->pmecc_corr_cap = CONFIG_PMECC_CAP;
+#endif
+#ifdef CONFIG_PMECC_SECTOR_SIZE
+ host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
+#endif
+ /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
+ * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
+ * from ONFI.
+ */
+ if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
+ dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
+ cap, sector_size);
+ return -EINVAL;
+ }
+
+ if (cap > host->pmecc_corr_cap)
+ dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
+ host->pmecc_corr_cap, cap);
+ if (sector_size < host->pmecc_sector_size)
+ dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
+ host->pmecc_sector_size, sector_size);
+#else /* CONFIG_SYS_NAND_ONFI_DETECTION */
+ host->pmecc_corr_cap = CONFIG_PMECC_CAP;
+ host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
+#endif
+
+ cap = host->pmecc_corr_cap;
+ sector_size = host->pmecc_sector_size;
+
+ /* TODO: need check whether cap & sector_size is validate */
+
+ if (host->pmecc_sector_size == 512)
+ host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
+ else
+ host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
MTDDEBUG(MTD_DEBUG_LEVEL1,
"Initialize PMECC params, cap: %d, sector: %d\n",
@@ -691,6 +863,12 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
return 0;
}
+ /* Allocate data for PMECC computation */
+ if (pmecc_data_alloc(host)) {
+ dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
+ return -ENOMEM;
+ }
+
nand->ecc.read_page = atmel_nand_pmecc_read_page;
nand->ecc.write_page = atmel_nand_pmecc_write_page;
nand->ecc.strength = cap;
diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c
index 7e5599ac63..a7476b49bb 100644
--- a/drivers/mtd/nand/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/fsl_elbc_spl.c
@@ -34,7 +34,11 @@ static void nand_wait(void)
}
}
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -114,6 +118,15 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
}
/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+ nand_load_image(offs, uboot_size, vdst)
+#endif
+
+/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
* from NAND into SDRAM and starts it from there.
@@ -124,17 +137,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 1e0210a9a4..d149a6dae6 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -51,7 +51,6 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
struct jffs2_unknown_node cleanmarker;
erase_info_t erase;
unsigned long erase_length, erased_length; /* in blocks */
- int bbtest = 1;
int result;
int percent_complete = -1;
const char *mtd_device = meminfo->name;
@@ -102,7 +101,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
puts("Size of erase exceeds limit\n");
return -EFBIG;
}
- if (!opts->scrub && bbtest) {
+ if (!opts->scrub) {
int ret = mtd_block_isbad(meminfo, erase.addr);
if (ret > 0) {
if (!opts->quiet)
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index e537fcf54c..191138ad18 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -11,6 +11,7 @@ LIB := $(obj)libspi_flash.o
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
+COBJS-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c
index 6a92c4b774..f34df43f58 100644
--- a/drivers/mtd/spi/atmel.c
+++ b/drivers/mtd/spi/atmel.c
@@ -252,7 +252,7 @@ static int dataflash_write_p2(struct spi_flash *flash,
}
debug("SF: AT45: Successfully programmed %zu bytes @ 0x%x\n",
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -325,7 +325,7 @@ static int dataflash_write_at45(struct spi_flash *flash,
}
debug("SF: AT45: Successfully programmed %zu bytes @ 0x%x\n",
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -387,7 +387,7 @@ static int dataflash_erase_p2(struct spi_flash *flash, u32 offset, size_t len)
}
debug("SF: AT45: Successfully erased %zu bytes @ 0x%x\n",
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -450,7 +450,7 @@ static int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len)
}
debug("SF: AT45: Successfully erased %zu bytes @ 0x%x\n",
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -476,7 +476,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
if (i == ARRAY_SIZE(atmel_spi_flash_table)) {
debug("SF: Unsupported DataFlash ID %02x\n",
- idcode[1]);
+ idcode[1]);
return NULL;
}
diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c
index b16e7ab098..25cfc1252c 100644
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -54,8 +54,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
flash->page_size = 256;
flash->sector_size = 256 * 16 * 16;
- flash->size = 256 * 16
- * params->nr_sectors;
+ flash->size = 256 * 16 * params->nr_sectors;
return flash;
}
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
new file mode 100644
index 0000000000..6263d8c221
--- /dev/null
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi_flash.h>
+#include <malloc.h>
+
+#define ESPI_BOOT_IMAGE_SIZE 0x48
+#define ESPI_BOOT_IMAGE_ADDR 0x50
+#define CONFIG_CFG_DATA_SECTOR 0
+
+/*
+ * The main entry for SPI booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from SPI into SDRAM and starts it from there.
+ */
+void spi_boot(void)
+{
+ void (*uboot)(void) __noreturn;
+ u32 offset, code_len;
+ unsigned char *buf = NULL;
+ struct spi_flash *flash;
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (flash == NULL) {
+ puts("\nspi_flash_probe failed");
+ hang();
+ }
+
+ /*
+ * Load U-Boot image from SPI flash into RAM
+ */
+ buf = malloc(flash->page_size);
+ if (buf == NULL) {
+ puts("\nmalloc failed");
+ hang();
+ }
+ memset(buf, 0, flash->page_size);
+
+ spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR,
+ flash->page_size, (void *)buf);
+ offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
+ /* Skip spl code */
+ offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ /* Get the code size from offset 0x48 */
+ code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
+ /* Skip spl code */
+ code_len = code_len - CONFIG_SPL_MAX_SIZE;
+ /* copy code to DDR */
+ spi_flash_read(flash, offset, code_len,
+ (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
+ /*
+ * Jump to U-Boot image
+ */
+ flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
+ uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+ (*uboot)();
+}
diff --git a/drivers/mtd/spi/gigadevice.c b/drivers/mtd/spi/gigadevice.c
index 950c7770a9..b42581a70f 100644
--- a/drivers/mtd/spi/gigadevice.c
+++ b/drivers/mtd/spi/gigadevice.c
@@ -45,7 +45,7 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode)
if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) {
debug("SF: Unsupported Gigadevice ID %02x%02x\n",
- idcode[1], idcode[2]);
+ idcode[1], idcode[2]);
return NULL;
}
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
index f67ddd696b..38f9d69169 100644
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -230,7 +230,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
/* JEDEC conformant RAMTRON id */
for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
params = &ramtron_spi_fram_table[i];
- if (idcode[1] == params->id1 && idcode[2] == params->id2)
+ if (idcode[1] == params->id1 &&
+ idcode[2] == params->id2)
goto found;
}
break;
@@ -251,7 +252,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
/* now find the device */
for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
params = &ramtron_spi_fram_table[i];
- if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
+ if (!strcmp(params->name,
+ CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
goto found;
}
debug("SF: Unsupported non-JEDEC RAMTRON device "
@@ -264,7 +266,7 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
/* arriving here means no method has found a device we can handle */
debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n",
- idcode[0], idcode[1], idcode[2]);
+ idcode[0], idcode[1], idcode[2]);
return NULL;
found:
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 47a48976b9..fa7ac8c932 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -6,7 +6,7 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com),
* and Jason McMullan (mcmullan@netapp.com)
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -122,7 +122,8 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
}
if (i == ARRAY_SIZE(spansion_spi_flash_table)) {
- debug("SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec);
+ debug("SF: Unsupported SPANSION ID %04x %04x\n",
+ jedec, ext_jedec);
return NULL;
}
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37e0e..5d5055ff38 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -40,12 +40,13 @@ static int spi_flash_read_write(struct spi_slave *spi,
ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
if (ret) {
debug("SF: Failed to send command (%zu bytes): %d\n",
- cmd_len, ret);
+ cmd_len, ret);
} else if (data_len != 0) {
- ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END);
+ ret = spi_xfer(spi, data_len * 8, data_out, data_in,
+ SPI_XFER_END);
if (ret)
debug("SF: Failed to transfer %zu bytes of data: %d\n",
- data_len, ret);
+ data_len, ret);
}
return ret;
@@ -86,7 +87,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
if (ret) {
debug("SF: fail to read %s status register\n",
- cmd == CMD_READ_STATUS ? "read" : "flag");
+ cmd == CMD_READ_STATUS ? "read" : "flag");
return ret;
}
@@ -144,7 +145,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
ret = spi_flash_cmd_wait_ready(flash, timeout);
if (ret < 0) {
debug("SF: write %s timed out\n",
- timeout == SPI_FLASH_PROG_TIMEOUT ?
+ timeout == SPI_FLASH_PROG_TIMEOUT ?
"program" : "page erase");
return ret;
}
@@ -554,12 +555,14 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
goto err_manufacturer_probe;
}
#endif
+#ifndef CONFIG_SPL_BUILD
printf("SF: Detected %s with page size ", flash->name);
print_size(flash->sector_size, ", total ");
print_size(flash->size, "");
if (flash->memory_map)
printf(", mapped at %p", flash->memory_map);
puts("\n");
+#endif
#ifndef CONFIG_SPI_FLASH_BAR
if (flash->size > SPI_FLASH_16MB_BOUN) {
puts("SF: Warning - Only lower 16MiB accessible,");
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 7c799ca482..29355307f3 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -39,7 +39,7 @@ void spl_spi_load_image(void)
/* Load u-boot, mkimage header is 64 bytes. */
spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
- (void *) header);
+ (void *)header);
spl_parse_image_header(header);
spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c
index 95f5490c35..256867c844 100644
--- a/drivers/mtd/spi/sst.c
+++ b/drivers/mtd/spi/sst.c
@@ -19,7 +19,7 @@
#include "spi_flash_internal.h"
#define CMD_SST_BP 0x02 /* Byte Program */
-#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */
+#define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
#define SST_SR_WIP (1 << 0) /* Write-in-Progress */
#define SST_SR_WEL (1 << 1) /* Write enable */
@@ -50,47 +50,61 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = {
.flags = SST_FEAT_WP,
.nr_sectors = 128,
.name = "SST25VF040B",
- },{
+ },
+ {
.idcode1 = 0x8e,
.flags = SST_FEAT_WP,
.nr_sectors = 256,
.name = "SST25VF080B",
- },{
+ },
+ {
.idcode1 = 0x41,
.flags = SST_FEAT_WP,
.nr_sectors = 512,
.name = "SST25VF016B",
- },{
+ },
+ {
.idcode1 = 0x4a,
.flags = SST_FEAT_WP,
.nr_sectors = 1024,
.name = "SST25VF032B",
- },{
+ },
+ {
.idcode1 = 0x4b,
.flags = SST_FEAT_MBP,
.nr_sectors = 2048,
.name = "SST25VF064C",
- },{
+ },
+ {
.idcode1 = 0x01,
.flags = SST_FEAT_WP,
.nr_sectors = 16,
.name = "SST25WF512",
- },{
+ },
+ {
.idcode1 = 0x02,
.flags = SST_FEAT_WP,
.nr_sectors = 32,
.name = "SST25WF010",
- },{
+ },
+ {
.idcode1 = 0x03,
.flags = SST_FEAT_WP,
.nr_sectors = 64,
.name = "SST25WF020",
- },{
+ },
+ {
.idcode1 = 0x04,
.flags = SST_FEAT_WP,
.nr_sectors = 128,
.name = "SST25WF040",
},
+ {
+ .idcode1 = 0x05,
+ .flags = SST_FEAT_WP,
+ .nr_sectors = 256,
+ .name = "SST25WF080",
+ },
};
static int
@@ -105,7 +119,7 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
};
debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
+ spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
@@ -152,11 +166,11 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
for (; actual < len - 1; actual += 2) {
debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0],
- offset);
+ spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
+ cmd[0], offset);
ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
- buf + actual, 2);
+ buf + actual, 2);
if (ret) {
debug("SF: sst word program failed\n");
break;
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 0ca00f158c..c5fa64e376 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -8,7 +8,7 @@
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -18,7 +18,7 @@
#include "spi_flash_internal.h"
/* M25Pxx-specific commands */
-#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */
+#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */
struct stmicro_spi_flash_params {
u16 id;
@@ -150,7 +150,7 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = {
},
};
-struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
+struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode)
{
const struct stmicro_spi_flash_params *params;
struct spi_flash *flash;
@@ -166,17 +166,17 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
idcode[0] = 0x20;
idcode[1] = 0x20;
idcode[2] = idcode[3] + 1;
- } else
+ } else {
return NULL;
+ }
}
id = ((idcode[1] << 8) | idcode[2]);
for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) {
params = &stmicro_spi_flash_table[i];
- if (params->id == id) {
+ if (params->id == id)
break;
- }
}
if (i == ARRAY_SIZE(stmicro_spi_flash_table)) {
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index c399bf14d1..b31911a405 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -123,7 +123,7 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
if (i == ARRAY_SIZE(winbond_spi_flash_table)) {
debug("SF: Unsupported Winbond ID %02x%02x\n",
- idcode[1], idcode[2]);
+ idcode[1], idcode[2]);
return NULL;
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-01 05:16:43 +0000