diff options
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/Kconfig | 28 | ||||
| -rw-r--r-- | drivers/mtd/cfi_flash.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/mtd_uboot.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/core.c | 3 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/atmel_nand.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/fsl_ifc_spl.c | 6 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 14 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 16 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/mxc_nand.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/mxs_nand_spl.c | 2 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 7 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_spl_loaders.c | 2 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/octeontx_bch.c | 5 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/octeontx_nand.c | 5 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/omap_gpmc.c | 68 | ||||
| -rw-r--r-- | drivers/mtd/ubi/Kconfig | 12 |
17 files changed, 118 insertions, 73 deletions
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index d8e2dec0a8..af45ef00da 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -77,6 +77,15 @@ config SYS_FLASH_CFI_WIDTH help This must be kept in sync with the table in include/flash.h +config FLASH_SHOW_PROGRESS + int "Print out a countdown durinng writes" + depends on FLASH_CFI_DRIVER + default 45 + help + If set to a non-zero value, print out countdown digits and dots. + Recommended value: 45 (9..1) for 80 column displays, 15 (3..1) for 40 + column displays. + config CFI_FLASH bool "Enable Driver Model for CFI Flash driver" depends on DM_MTD @@ -110,6 +119,13 @@ config SYS_FLASH_EMPTY_INFO bool "Enable displaying empty sectors in flash info" depends on FLASH_CFI_DRIVER +config FLASH_SPANSION_S29WS_N + bool "Non-standard s29ws-n MirrorBit flash" + depends on FLASH_CFI_DRIVER + help + Enable this if the s29ws-n MirrorBit flash has non-standard addresses + for buffered write commands. + config FLASH_CFI_MTD bool "Enable CFI MTD driver" depends on FLASH_CFI_DRIVER @@ -147,6 +163,18 @@ config SYS_FLASH_CHECKSUM If the variable flashchecksum is set in the environment, perform a CRC of the flash and print the value to console. +config FLASH_VERIFY + bool "Compare writes to NOR flash with source location" + depends on MTD_NOR_FLASH + help + If enabled, the content of the flash (destination) is compared + against the source after the write operation. An error message will + be printed when the contents are not identical. Please note that + this option is useless in nearly all cases, since such flash + programming errors usually are detected earlier while + unprotecting/erasing/programming. Please only enable this option if + you really know what you are doing. + config ALTERA_QSPI bool "Altera Generic Quad SPI Controller" depends on DM_MTD diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index c1cdd2cbc3..f378f6fb61 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1292,7 +1292,7 @@ void flash_print_info(flash_info_t *info) * effect updates to digit and dots. Repeated code is nasty too, so * we define it once here. */ -#ifdef CONFIG_FLASH_SHOW_PROGRESS +#if CONFIG_FLASH_SHOW_PROGRESS #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ if (flash_verbose) { \ dots -= dots_sub; \ @@ -1325,7 +1325,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE int buffered_size; #endif -#ifdef CONFIG_FLASH_SHOW_PROGRESS +#if CONFIG_FLASH_SHOW_PROGRESS int digit = CONFIG_FLASH_SHOW_PROGRESS; int scale = 0; int dots = 0; diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index dd0b0242f9..14ce726b10 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -30,8 +30,6 @@ static const char *get_mtdids(void) #if defined(CONFIG_SYS_MTDPARTS_RUNTIME) board_mtdparts_default(&mtdids, &mtdparts); -#elif defined(MTDIDS_DEFAULT) - mtdids = MTDIDS_DEFAULT; #elif defined(CONFIG_MTDIDS_DEFAULT) mtdids = CONFIG_MTDIDS_DEFAULT; #endif @@ -147,8 +145,6 @@ static const char *get_mtdparts(void) #if defined(CONFIG_SYS_MTDPARTS_RUNTIME) board_mtdparts_default(&mtdids, &mtdparts); -#elif defined(MTDPARTS_DEFAULT) - mtdparts = MTDPARTS_DEFAULT; #elif defined(CONFIG_MTDPARTS_DEFAULT) mtdparts = CONFIG_MTDPARTS_DEFAULT; #endif diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 99c29670c7..4b9dd6a926 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -129,7 +129,7 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved); * * Return: 0 in case of success, a negative error code otherwise. */ -int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) +static int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) { unsigned int entry; @@ -147,7 +147,6 @@ int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) return nand->ops->erase(nand, pos); } -EXPORT_SYMBOL_GPL(nanddev_erase); /** * nanddev_mtd_erase() - Generic mtd->_erase() implementation for NAND devices diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 0f2eaebfdb..ab719a2ff1 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -205,6 +205,7 @@ config NAND_DENALI config NAND_DENALI_DT bool "Support Denali NAND controller as a DT device" select NAND_DENALI + select SPL_SYS_NAND_SELF_INIT depends on OF_CONTROL && DM_MTD help Enable the driver for NAND flash on platforms using a Denali NAND @@ -259,7 +260,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" - depends on ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can @@ -487,6 +488,10 @@ config SYS_NAND_SIZE depends on NAND_MXC && SPL_NAND_SUPPORT default 268435456 +config MXC_NAND_HWECC + bool "Hardware ECC support in MXC NAND" + depends on NAND_MXC + config NAND_MXS bool "MXS NAND support" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 9fbb0b57cf..b7e473c598 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -38,10 +38,6 @@ #ifdef CONFIG_ATMEL_NAND_HW_PMECC -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_SYS_NAND_ONFI_DETECTION -#endif - struct atmel_nand_host { struct pmecc_regs __iomem *pmecc; struct pmecc_errloc_regs __iomem *pmerrloc; diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 3b464ce10c..60a865b566 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -278,11 +278,11 @@ void nand_boot(void) * U-Boot header is appended at end of U-boot image, so * calculate U-boot header address using U-boot header size. */ -#define CONFIG_U_BOOT_HDR_ADDR \ +#define FSL_U_BOOT_HDR_ADDR \ ((CFG_SYS_NAND_U_BOOT_START + \ CFG_SYS_NAND_U_BOOT_SIZE) - \ - CONFIG_U_BOOT_HDR_SIZE) - spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, + FSL_U_BOOT_HDR_SIZE) + spl_validate_uboot(FSL_U_BOOT_HDR_ADDR, CFG_SYS_NAND_U_BOOT_START); /* * In case of failure in validation, spl_validate_uboot would diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index a884c65d18..2854117760 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -141,13 +141,13 @@ static void lpc32xx_nand_init(void) clk = get_hclk_clk_rate(); writel( - clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), + clkdiv(CFG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | + clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | + clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | + clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | + clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | + clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | + clkdiv(CFG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), &lpc32xx_nand_mlc_registers->time_reg); } diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index f4f1b22f5e..356f8d9440 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -126,14 +126,14 @@ static void lpc32xx_nand_init(void) &lpc32xx_nand_slc_regs->icr); /* Configure NAND flash timings */ - writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) | - TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | - TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | - TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | - TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) | - TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | - TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | - TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), + writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | + TAC_W_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_WWIDTH) | + TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | + TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) | + TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | + TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | + TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | + TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP), &lpc32xx_nand_slc_regs->tac); } diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 8aa5f73421..051ded6a24 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1172,10 +1172,10 @@ int board_nand_init(struct nand_chip *this) this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; - host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; + host->regs = (struct mxc_nand_regs __iomem *)CFG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 host->ip_regs = - (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE; + (struct mxc_nand_ip_regs __iomem *)CFG_MXC_NAND_IP_REGS_BASE; #endif host->clk_act = 1; diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index ef03b7789d..300662994c 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -257,7 +257,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) while (block <= lastblock && size > 0) { if (!is_badblock(mtd, mtd->erasesize * block, 1)) { /* Skip bad blocks */ - while (page < nand_page_per_block) { + while (page < nand_page_per_block && size) { int curr_page = nand_page_per_block * block + page; if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) { diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 215b9ba84f..bc61ad03eb 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4171,10 +4171,13 @@ static void nand_manufacturer_detect(struct nand_chip *chip) * nand_decode_ext_id() otherwise. */ if (chip->manufacturer.desc && chip->manufacturer.desc->ops && - chip->manufacturer.desc->ops->detect) + chip->manufacturer.desc->ops->detect) { + /* The 3rd id byte holds MLC / multichip data */ + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->manufacturer.desc->ops->detect(chip); - else + } else { nand_decode_ext_id(chip); + } } /* diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c index 4befc75c04..156b44d835 100644 --- a/drivers/mtd/nand/raw/nand_spl_loaders.c +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c @@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) if (unlikely(page_offset)) { memmove(dst, dst + page_offset, CONFIG_SYS_NAND_PAGE_SIZE); - dst = (void *)((int)dst - page_offset); + dst = (void *)(dst - page_offset); page_offset = 0; } dst += CONFIG_SYS_NAND_PAGE_SIZE; diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c index c1d721cabf..fc16b77416 100644 --- a/drivers/mtd/nand/raw/octeontx_bch.c +++ b/drivers/mtd/nand/raw/octeontx_bch.c @@ -27,11 +27,6 @@ #include <asm/arch/clock.h> #include "octeontx_bch.h" -#ifdef DEBUG -# undef CONFIG_LOGLEVEL -# define CONFIG_LOGLEVEL 8 -#endif - LIST_HEAD(octeontx_bch_devices); static unsigned int num_vfs = BCH_NR_VF; static void *bch_pf; diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c index b338b204f3..1ffadad9ca 100644 --- a/drivers/mtd/nand/raw/octeontx_nand.c +++ b/drivers/mtd/nand/raw/octeontx_nand.c @@ -31,11 +31,6 @@ #include <asm/arch/clock.h> #include "octeontx_bch.h" -#ifdef DEBUG -# undef CONFIG_LOGLEVEL -# define CONFIG_LOGLEVEL 8 -#endif - /* * The NDF_CMD queue takes commands between 16 - 128 bit. * All commands must be 16 bit aligned and are little endian. diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b7d261d8ce..be3cb3c601 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -8,7 +8,11 @@ #include <log.h> #include <asm/io.h> #include <linux/errno.h> + +#ifdef CONFIG_ARCH_OMAP2PLUS #include <asm/arch/mem.h> +#endif + #include <linux/mtd/omap_gpmc.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/rawnand.h> @@ -17,6 +21,10 @@ #include <nand.h> #include <linux/mtd/omap_elm.h> +#ifndef GPMC_MAX_CS +#define GPMC_MAX_CS 4 +#endif + #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 #define ECCCLEAR (0x1 << 8) @@ -29,7 +37,6 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 0x97, 0x79, 0xe5, 0x24, 0xb5}; #endif static uint8_t cs_next; -static __maybe_unused struct nand_ecclayout omap_ecclayout; #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = @@ -47,6 +54,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */ + void __iomem *fifo; }; /* We are wasting a bit of memory but al least we are safe */ @@ -342,6 +350,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; } +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); + u32 alignment = ((uintptr_t)buf | len) & 3; + + if (alignment & 1) + readsb(info->fifo, buf, len); + else if (alignment & 3) + readsw(info->fifo, buf, len >> 1); + else + readsl(info->fifo, buf, len >> 2); +} + #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH #define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -407,7 +429,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt); for (i = 0; i < cnt / 4; i++) { - *buf++ = readl(CFG_SYS_NAND_BASE); + *buf++ = readl(info->fifo); len -= 4; } } while (len); @@ -417,29 +439,19 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; } -static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->options & NAND_BUSWIDTH_16) - nand_read_buf16(mtd, buf, len); - else - nand_read_buf(mtd, buf, len); -} - static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; - uint32_t head, tail; + uintptr_t head, tail; struct nand_chip *chip = mtd_to_nand(mtd); /* * If the destination buffer is unaligned, start with reading * the overlap byte-wise. */ - head = ((uint32_t) buf) % 4; + head = ((uintptr_t)buf) % 4; if (head) { - omap_nand_read(mtd, buf, head); + omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; } @@ -453,10 +465,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */ - omap_nand_read(mtd, buf, len); + omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail; - omap_nand_read(mtd, buf, tail); + omap_nand_read_buf(mtd, buf, tail); } } #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -740,7 +752,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { struct omap_nand_info *info = nand_get_controller_data(nand); - struct nand_ecclayout *ecclayout = &omap_ecclayout; + struct nand_ecclayout *ecclayout = nand->ecc.layout; int eccsteps = pagesize / SECTOR_BYTES; int i; @@ -993,6 +1005,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0; + struct omap_nand_info *info; + /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -1021,14 +1035,19 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - omap_nand_info[cs].control = NULL; - omap_nand_info[cs].cs = cs; - omap_nand_info[cs].ws = wscfg[cs]; + + info = &omap_nand_info[cs]; + info->control = NULL; + info->cs = cs; + info->ws = wscfg[cs]; + info->fifo = (void __iomem *)CFG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; nand->chip_delay = 100; - nand->ecc.layout = &omap_ecclayout; + nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL); + if (!nand->ecc.layout) + return -ENOMEM; /* configure driver and controller based on NAND device bus-width */ gpmc_config = readl(&gpmc_cfg->cs[cs].config1); @@ -1054,10 +1073,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else - if (nand->options & NAND_BUSWIDTH_16) - nand->read_buf = nand_read_buf16; - else - nand->read_buf = nand_read_buf; + nand->read_buf = omap_nand_read_buf; #endif nand->dev_ready = omap_dev_ready; diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 67a3cf1d7a..5783d36c04 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -20,6 +20,18 @@ config MTD_UBI if MTD_UBI +config MTD_UBI_BLOCK + def_bool n + +config MTD_UBI_MODULE + def_bool y + help + ubi_init() disables returning error codes when built into the Linux + kernel so that it doesn't hang the Linux kernel boot process. Since + the U-Boot driver code depends on getting valid error codes from this + function we just tell the UBI layer that we are building as a module + (which only enables the additional error reporting). + config MTD_UBI_WL_THRESHOLD int "UBI wear-leveling threshold" default 4096 |