diff options
Diffstat (limited to 'drivers/mtd/nand/raw')
| -rw-r--r-- | drivers/mtd/nand/raw/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/fsl_elbc_nand.c | 6 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 30 |
3 files changed, 28 insertions, 14 deletions
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 4129a33866..190300fc17 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -73,6 +73,7 @@ config PMECC_SECTOR_SIZE config SPL_GENERATE_ATMEL_PMECC_HEADER bool "Atmel PMECC Header Generation" + depends on SPL select ATMEL_NAND_HWECC select ATMEL_NAND_HW_PMECC help @@ -647,7 +648,7 @@ config SYS_NAND_U_BOOT_OFFS_REDUND config SPL_NAND_AM33XX_BCH bool "Enables SPL-NAND driver which supports ELM based" - depends on NAND_OMAP_GPMC && !OMAP34XX + depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX default y help Hardware ECC correction. This is useful for platforms which have ELM @@ -658,6 +659,7 @@ config SPL_NAND_AM33XX_BCH config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" + depends on SPL_NAND_SUPPORT help This is a small implementation of the Denali NAND controller for use on SPL. @@ -673,7 +675,7 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES config SPL_NAND_SIMPLE bool "Use simple SPL NAND driver" - depends on !SPL_NAND_AM33XX_BCH + depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT help Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface. diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index b0e3eb607e..48a3687f27 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -745,7 +745,11 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) return ret; /* If nand_scan_ident() has not selected ecc.mode, do it now */ - if (nand->ecc.mode == NAND_ECC_NONE) { + if (nand->ecc.mode == 0 +#if CONFIG_IS_ENABLED(OF_CONTROL) + && !ofnode_read_string(nand->flash_node, "nand-ecc-mode") +#endif + ) { /* If CS Base Register selects full hardware ECC then use it */ if ((br & BR_DECC) == BR_DECC_CHK_GEN) { nand->ecc.mode = NAND_ECC_HW; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6f81257cf1..e8ece0a4a0 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -974,6 +974,22 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) return ret; } +static int nand_onfi_set_timings(struct mtd_info *mtd, struct nand_chip *chip) +{ + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) + return 0; + + u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { + chip->onfi_timing_mode_default, + }; + + return chip->onfi_set_features(mtd, chip, + ONFI_FEATURE_ADDR_TIMING_MODE, + tmode_param); +} + /** * nand_setup_data_interface - Setup the best data interface and timings * @chip: The NAND chip @@ -999,17 +1015,9 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) * Ensure the timing mode has been changed on the chip side * before changing timings on the controller side. */ - if (chip->onfi_version) { - u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { - chip->onfi_timing_mode_default, - }; - - ret = chip->onfi_set_features(mtd, chip, - ONFI_FEATURE_ADDR_TIMING_MODE, - tmode_param); - if (ret) - goto err; - } + ret = nand_onfi_set_timings(mtd, chip); + if (ret) + goto err; ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); err: |