2 files changed, 31 insertions, 7 deletions

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 4a1accebfc..34119f949a 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -977,34 +977,50 @@ static int renesas_sdhi_probe(struct udevice *dev)
 
 	/* optional SDnH clock */
 	ret = clk_get_by_name(dev, "clkh", &priv->clkh);
-	if (ret < 0)
+	if (ret < 0) {
 		dev_dbg(dev, "failed to get clkh\n");
+	} else {
+		ret = clk_set_rate(&priv->clkh, 800000000);
+		if (ret < 0) {
+			dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret);
+			goto err_clk;
+		}
+	}
 
 	/* set to max rate */
 	ret = clk_set_rate(&priv->clk, 200000000);
 	if (ret < 0) {
-		dev_err(dev, "failed to set rate for host clock\n");
-		clk_free(&priv->clk);
-		return ret;
+		dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret);
+		goto err_clkh;
 	}
 
 	ret = clk_enable(&priv->clk);
 	if (ret) {
-		dev_err(dev, "failed to enable host clock\n");
-		return ret;
+		dev_err(dev, "failed to enable SDn clock (%d)\n", ret);
+		goto err_clkh;
 	}
 
 	priv->quirks = quirks;
 	ret = tmio_sd_probe(dev, quirks);
+	if (ret)
+		goto err_tmio_probe;
 
 	renesas_sdhi_filter_caps(dev);
 
 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
-	if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
+	if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
 		renesas_sdhi_reset_tuning(priv);
 #endif
+	return 0;
+
+err_tmio_probe:
+	clk_disable(&priv->clk);
+err_clkh:
+	clk_free(&priv->clkh);
+err_clk:
+	clk_free(&priv->clk);
 	return ret;
 }
 
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 573bf16c87..3661ce3314 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -41,6 +41,14 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	int ret;
 
+	/*
+	 * The clock frequency chosen here affects CLKDIV in the dw_mmc core.
+	 * That can be either 0 or 1, but it must be set to 1 for eMMC DDR52
+	 * 8-bit mode.  It will be set to 0 for all other modes.
+	 */
+	if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
+		freq *= 2;
+
 	ret = clk_set_rate(&priv->clk, freq);
 	if (ret < 0) {
 		debug("%s: err=%d\n", __func__, ret);