diff options
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/Kconfig | 10 | ||||
| -rw-r--r-- | drivers/mmc/Makefile | 1 | ||||
| -rw-r--r-- | drivers/mmc/mtk-sd.c | 23 | ||||
| -rw-r--r-- | drivers/mmc/omap_hsmmc.c | 21 | ||||
| -rw-r--r-- | drivers/mmc/snps_dw_mmc.c | 199 |
5 files changed, 239 insertions, 15 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 04a4e7716f..c34dd5d187 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -222,6 +222,16 @@ config MMC_DW_SOCFPGA Synopsys DesignWare Memory Card Interface driver. Select this option for platforms based on Altera SOCFPGA. +config MMC_DW_SNPS + bool "Extensions for DW Memory Card Interface used in Synopsys ARC devboards" + depends on MMC_DW + depends on DM_MMC + depends on OF_CONTROL + depends on CLK + help + This selects support for Synopsys DesignWare Memory Card Interface driver + extensions used in various Synopsys ARC devboards. + config MMC_MESON_GX bool "Meson GX EMMC controller support" depends on DM_MMC && BLK && ARCH_MESON diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 7892c468f0..0076fc393b 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o +obj-$(CONFIG_MMC_DW_SNPS) += snps_dw_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index d3f0778368..e0ac3e9d69 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -247,6 +247,7 @@ struct msdc_host { struct msdc_compatible *dev_comp; struct clk src_clk; /* for SD/MMC bus clock */ + struct clk src_clk_cg; /* optional, MSDC source clock control gate */ struct clk h_clk; /* MSDC core clock */ u32 src_clk_freq; /* source clock */ @@ -269,7 +270,7 @@ struct msdc_host { bool builtin_cd; /* card detection / write protection GPIOs */ -#if IS_ENABLED(DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc gpio_wp; struct gpio_desc gpio_cd; #endif @@ -849,7 +850,7 @@ static int msdc_ops_get_cd(struct udevice *dev) return !(val & MSDC_PS_CDSTS); } -#if IS_ENABLED(DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) if (!host->gpio_cd.dev) return 1; @@ -861,7 +862,7 @@ static int msdc_ops_get_cd(struct udevice *dev) static int msdc_ops_get_wp(struct udevice *dev) { -#if IS_ENABLED(DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) struct msdc_host *host = dev_get_priv(dev); if (!host->gpio_wp.dev) @@ -1269,6 +1270,8 @@ static void msdc_ungate_clock(struct msdc_host *host) { clk_enable(&host->src_clk); clk_enable(&host->h_clk); + if (host->src_clk_cg.dev) + clk_enable(&host->src_clk_cg); } static int msdc_drv_probe(struct udevice *dev) @@ -1332,7 +1335,9 @@ static int msdc_ofdata_to_platdata(struct udevice *dev) if (ret < 0) return ret; -#if IS_ENABLED(DM_GPIO) + clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */ + +#if CONFIG_IS_ENABLED(DM_GPIO) gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN); gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN); #endif @@ -1376,8 +1381,18 @@ static const struct msdc_compatible mt7623_compat = { .enhance_rx = false }; +static const struct msdc_compatible mt8516_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, +}; + static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, + { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, {} }; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 826a39fad7..133cdc1352 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -264,7 +264,7 @@ static unsigned char mmc_board_init(struct mmc *mmc) !CONFIG_IS_ENABLED(DM_REGULATOR) /* PBIAS config needed for MMC1 only */ if (mmc_get_blk_desc(mmc)->devnum == 0) - vmmc_pbias_config(LDO_VOLT_3V0); + vmmc_pbias_config(LDO_VOLT_3V3); #endif return 0; @@ -418,7 +418,7 @@ static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage) switch (signal_voltage) { case MMC_SIGNAL_VOLTAGE_330: - hctl |= SDVS_3V0; + hctl |= SDVS_3V3; break; case MMC_SIGNAL_VOLTAGE_180: hctl |= SDVS_1V8; @@ -514,10 +514,9 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc) return -EINVAL; if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { - /* Use 3.0V rather than 3.3V */ - mv = 3000; - capa_mask = VS30_3V0SUP; - palmas_ldo_volt = LDO_VOLT_3V0; + mv = 3300; + capa_mask = VS33_3V3SUP; + palmas_ldo_volt = LDO_VOLT_3V3; } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { capa_mask = VS18_1V8SUP; palmas_ldo_volt = LDO_VOLT_1V8; @@ -556,13 +555,13 @@ static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc) val = readl(&mmc_base->capa); if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { - val |= (VS30_3V0SUP | VS18_1V8SUP); + val |= (VS33_3V3SUP | VS18_1V8SUP); } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) { - val |= VS30_3V0SUP; + val |= VS33_3V3SUP; val &= ~VS18_1V8SUP; } else { val |= VS18_1V8SUP; - val &= ~VS30_3V0SUP; + val &= ~VS33_3V3SUP; } writel(val, &mmc_base->capa); @@ -842,11 +841,11 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) #if CONFIG_IS_ENABLED(DM_MMC) reg_val = omap_hsmmc_set_capabilities(mmc); - omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ? + omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ? MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180); #else writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); - writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, + writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP, &mmc_base->capa); #endif diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c new file mode 100644 index 0000000000..5a413f0ec7 --- /dev/null +++ b/drivers/mmc/snps_dw_mmc.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Synopsys DesignWare Multimedia Card Interface driver + * extensions used in various Synopsys ARC devboards. + * + * Copyright (C) 2019 Synopsys + * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/libfdt.h> +#include <linux/err.h> +#include <malloc.h> + +#define CLOCK_MIN 400000 /* 400 kHz */ +#define FIFO_MIN 8 +#define FIFO_MAX 4096 + +struct snps_dwmci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct snps_dwmci_priv_data { + struct dwmci_host host; + u32 f_max; +}; + +static int snps_dwmmc_clk_setup(struct udevice *dev) +{ + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + + struct clk clk_ciu, clk_biu; + int ret; + + ret = clk_get_by_name(dev, "ciu", &clk_ciu); + if (ret) + goto clk_err; + + ret = clk_enable(&clk_ciu); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) + goto clk_err_ciu; + + host->bus_hz = clk_get_rate(&clk_ciu); + if (host->bus_hz < CLOCK_MIN) { + ret = -EINVAL; + goto clk_err_ciu_dis; + } + + ret = clk_get_by_name(dev, "biu", &clk_biu); + if (ret) + goto clk_err_ciu_dis; + + ret = clk_enable(&clk_biu); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) + goto clk_err_biu; + + return 0; + +clk_err_biu: + clk_free(&clk_biu); +clk_err_ciu_dis: + clk_disable(&clk_ciu); +clk_err_ciu: + clk_free(&clk_ciu); +clk_err: + dev_err(dev, "failed to setup clocks, ret %d\n", ret); + + return ret; +} + +static int snps_dwmmc_ofdata_to_platdata(struct udevice *dev) +{ + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + u32 fifo_depth; + int ret; + + host->ioaddr = devfdt_get_addr_ptr(dev); + + /* + * If fifo-depth is unset don't set fifoth_val - we will try to + * auto detect it. + */ + ret = dev_read_u32(dev, "fifo-depth", &fifo_depth); + if (!ret) { + if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX) + return -EINVAL; + + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(fifo_depth / 2 - 1) | + TX_WMARK(fifo_depth / 2); + } + + host->buswidth = dev_read_u32_default(dev, "bus-width", 4); + if (host->buswidth != 1 && host->buswidth != 4 && host->buswidth != 8) + return -EINVAL; + + /* + * If max-frequency is unset don't set priv->f_max - we will use + * host->bus_hz in probe() instead. + */ + ret = dev_read_u32(dev, "max-frequency", &priv->f_max); + if (!ret && priv->f_max < CLOCK_MIN) + return -EINVAL; + + host->fifo_mode = dev_read_bool(dev, "fifo-mode"); + host->name = dev->name; + host->dev_index = 0; + host->priv = priv; + + return 0; +} + +int snps_dwmmc_getcd(struct udevice *dev) +{ + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + +struct dm_mmc_ops snps_dwmci_dm_ops; + +static int snps_dwmmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_BLK + struct snps_dwmci_plat *plat = dev_get_platdata(dev); +#endif + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct snps_dwmci_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + unsigned int clock_max; + int ret; + + /* Extend generic 'dm_dwmci_ops' with our 'getcd' implementation */ + memcpy(&snps_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops)); + snps_dwmci_dm_ops.get_cd = snps_dwmmc_getcd; + + ret = snps_dwmmc_clk_setup(dev); + if (ret) + return ret; + + if (!priv->f_max) + clock_max = host->bus_hz; + else + clock_max = min_t(unsigned int, host->bus_hz, priv->f_max); + +#ifdef CONFIG_BLK + dwmci_setup_cfg(&plat->cfg, host, clock_max, CLOCK_MIN); + host->mmc = &plat->mmc; +#else + ret = add_dwmci(host, clock_max, CLOCK_MIN); + if (ret) + return ret; +#endif + host->mmc->priv = &priv->host; + upriv->mmc = host->mmc; + host->mmc->dev = dev; + + return dwmci_probe(dev); +} + +static int snps_dwmmc_bind(struct udevice *dev) +{ +#ifdef CONFIG_BLK + struct snps_dwmci_plat *plat = dev_get_platdata(dev); + int ret; + + ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; +#endif + + return 0; +} + +static const struct udevice_id snps_dwmmc_ids[] = { + { .compatible = "snps,dw-mshc" }, + { } +}; + +U_BOOT_DRIVER(snps_dwmmc_drv) = { + .name = "snps_dw_mmc", + .id = UCLASS_MMC, + .of_match = snps_dwmmc_ids, + .ofdata_to_platdata = snps_dwmmc_ofdata_to_platdata, + .ops = &snps_dwmci_dm_ops, + .bind = snps_dwmmc_bind, + .probe = snps_dwmmc_probe, + .priv_auto_alloc_size = sizeof(struct snps_dwmci_priv_data), + .platdata_auto_alloc_size = sizeof(struct snps_dwmci_plat), +}; |