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-rw-r--r--drivers/mmc/Kconfig5
-rw-r--r--drivers/mmc/fsl_esdhc_imx.c17
-rw-r--r--drivers/mmc/ftsdc010_mci.c45
-rw-r--r--drivers/mmc/mxsmmc.c4
-rw-r--r--drivers/mmc/omap_hsmmc.c10
-rw-r--r--drivers/mmc/rockchip_dw_mmc.c8
6 files changed, 40 insertions, 49 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 1569e8c44a..e0927ce1c9 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -123,7 +123,6 @@ config MMC_IO_VOLTAGE
config SPL_MMC_IO_VOLTAGE
bool "Support IO voltage configuration in SPL"
- default n
help
IO voltage configuration allows selecting the voltage level of the IO
lines (not the level of main supply). This is required for UHS
@@ -193,7 +192,6 @@ config MMC_VERBOSE
config MMC_TRACE
bool "MMC debugging"
- default n
help
This is an option for use by developer. Enable MMC core debugging.
@@ -221,7 +219,6 @@ config MMC_DW_CORTINA
depends on DM_MMC
depends on MMC_DW
depends on BLK
- default n
help
This selects support for Cortina SoC specific extensions to the
Synopsys DesignWare Memory Card Interface driver. Select this option
@@ -770,7 +767,6 @@ config FTSDC010
config FTSDC010_SDIO
bool "Support ftsdc010 sdio"
- default n
depends on FTSDC010
help
This can enable ftsdc010 sdio function.
@@ -805,7 +801,6 @@ config FSL_ESDHC_SUPPORT_ADMA2
config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
bool "enable eSDHC workaround for 3.3v IO reliability issue"
depends on FSL_ESDHC && DM_MMC
- default n
help
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index aabf39535f..5dfd484ef9 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1411,7 +1411,6 @@ __weak void init_clk_usdhc(u32 index)
static int fsl_esdhc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
@@ -1419,10 +1418,12 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
#endif
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
-
fdt_addr_t addr;
unsigned int val;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -1494,7 +1495,7 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
priv->vs18_enable = 1;
}
#endif
-#endif
+
return 0;
}
@@ -1598,11 +1599,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = mmc_of_parse(dev, &plat->cfg);
- if (ret)
- return ret;
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+ }
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
index 0fa037224f..570d54cf9d 100644
--- a/drivers/mmc/ftsdc010_mci.c
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -30,8 +30,6 @@
#include <syscon.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
@@ -392,34 +390,29 @@ static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswid
static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
- chip->name = dev->name;
- chip->ioaddr = dev_read_addr_ptr(dev);
- chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "bus-width", 4);
- chip->priv = dev;
- priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "fifo-depth", 0);
- priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
- "fifo-mode");
- if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
- "clock-freq-min-max", priv->minmax, 2)) {
- int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "max-frequency", -EINVAL);
- if (val < 0)
- return val;
-
- priv->minmax[0] = 400000; /* 400 kHz */
- priv->minmax[1] = val;
- } else {
- debug("%s: 'clock-freq-min-max' property was deprecated.\n",
- __func__);
+
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ chip->name = dev->name;
+ chip->ioaddr = dev_read_addr_ptr(dev);
+ chip->buswidth = dev_read_u32_default(dev, "bus-width", 4);
+ chip->priv = dev;
+ priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
+ priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
+ if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
+ if (dev_read_u32(dev, "max-frequency", &priv->minmax[1]))
+ return -EINVAL;
+
+ priv->minmax[0] = 400000; /* 400 kHz */
+ } else {
+ debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+ __func__);
+ }
}
-#endif
chip->sclk = priv->minmax[1];
chip->regs = chip->ioaddr;
+
return 0;
}
@@ -440,7 +433,7 @@ static int ftsdc010_mmc_probe(struct udevice *dev)
chip->priv = dev;
chip->dev_index = 1;
memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
+ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
if (ret < 0)
return ret;
#endif
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 8fd4176415..35a8e21058 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -665,7 +665,7 @@ static const struct dm_mmc_ops mxsmmc_ops = {
.set_ios = mxsmmc_set_ios,
};
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int mxsmmc_of_to_plat(struct udevice *bus)
{
struct mxsmmc_plat *plat = dev_get_plat(bus);
@@ -709,7 +709,7 @@ static const struct udevice_id mxsmmc_ids[] = {
U_BOOT_DRIVER(fsl_imx23_mmc) = {
.name = "fsl_imx23_mmc",
.id = UCLASS_MMC,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = mxsmmc_ids,
.of_to_plat = mxsmmc_of_to_plat,
#endif
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 306ce0fe1e..820065800f 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -42,7 +42,7 @@
#include <asm/arch/mux_dra7xx.h>
#include <asm/arch/dra7xx_iodelay.h>
#endif
-#if !defined(CONFIG_SOC_KEYSTONE)
+#if !defined(CONFIG_ARCH_KEYSTONE)
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#endif
@@ -1559,7 +1559,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
+ defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
@@ -1891,7 +1891,7 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
}
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
#ifdef CONFIG_OMAP54XX
__weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
{
@@ -2009,7 +2009,7 @@ static int omap_hsmmc_probe(struct udevice *dev)
return omap_hsmmc_init_setup(mmc);
}
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct omap_mmc_of_data dra7_mmc_of_data = {
.controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
@@ -2027,7 +2027,7 @@ static const struct udevice_id omap_hsmmc_ids[] = {
U_BOOT_DRIVER(omap_hsmmc) = {
.name = "omap_hsmmc",
.id = UCLASS_MMC,
-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = omap_hsmmc_ids,
.of_to_plat = omap_hsmmc_of_to_plat,
.plat_auto = sizeof(struct omap_hsmmc_plat),
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index d7d5361fd5..7f8dea1e34 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -52,10 +52,12 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
@@ -95,7 +97,7 @@ static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
-#endif
+
return 0;
}
@@ -121,7 +123,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = dtplat->max_frequency;
- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
+ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
if (ret < 0)
return ret;
#else
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-16 01:37:13 +0000