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-rw-r--r--drivers/misc/imx8ulp/Makefile4
-rw-r--r--drivers/misc/imx8ulp/fuse.c198
-rw-r--r--drivers/misc/imx8ulp/imx8ulp_mu.c234
-rw-r--r--drivers/misc/imx8ulp/s400_api.c244
4 files changed, 680 insertions, 0 deletions
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
new file mode 100644
index 0000000000..927cc55216
--- /dev/null
+++ b/drivers/misc/imx8ulp/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += s400_api.o imx8ulp_mu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/imx8ulp/fuse.c
new file mode 100644
index 0000000000..d1feb62ab5
--- /dev/null
+++ b/drivers/misc/imx8ulp/fuse.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <console.h>
+#include <errno.h>
+#include <fuse.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include <env.h>
+#include <asm/arch/s400_api.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FUSE_BANKS 64
+#define WORDS_PER_BANKS 8
+
+struct fsb_map_entry {
+ s32 fuse_bank;
+ u32 fuse_words;
+ bool redundancy;
+};
+
+struct s400_map_entry {
+ s32 fuse_bank;
+ u32 fuse_words;
+ u32 fuse_offset;
+ u32 s400_index;
+};
+
+struct fsb_map_entry fsb_mapping_table[] = {
+ { 3, 8 },
+ { 4, 8 },
+ { 5, 8 },
+ { 6, 8 },
+ { -1, 48 }, /* Reserve 48 words */
+ { 8, 4, true },
+ { 24, 4, true },
+ { 26, 4, true },
+ { 27, 4, true },
+ { 28, 8 },
+ { 29, 8 },
+ { 30, 8 },
+ { 31, 8 },
+ { 37, 8 },
+ { 38, 8 },
+ { 39, 8 },
+ { 40, 8 },
+ { 41, 8 },
+ { 42, 8 },
+ { 43, 8 },
+ { 44, 8 },
+ { 45, 8 },
+ { 46, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+ { 1, 8 }, /* LOCK */
+ { 2, 8 }, /* ECID */
+ { 7, 4, 0, 1 }, /* OTP_UNIQ_ID */
+ { 23, 1, 4, 2 }, /* OTFAD */
+};
+
+static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
+{
+ s32 size = ARRAY_SIZE(fsb_mapping_table);
+ s32 i, word_pos = 0;
+
+ /* map the fuse from ocotp fuse map to FSB*/
+ for (i = 0; i < size; i++) {
+ if (fsb_mapping_table[i].fuse_bank != -1 &&
+ fsb_mapping_table[i].fuse_bank == bank) {
+ break;
+ }
+
+ word_pos += fsb_mapping_table[i].fuse_words;
+ }
+
+ if (i == size)
+ return -1; /* Failed to find */
+
+ if (fsb_mapping_table[i].redundancy) {
+ *redundancy = true;
+ return (word >> 1) + word_pos;
+ }
+
+ *redundancy = false;
+ return word + word_pos;
+}
+
+static s32 map_s400_fuse_index(u32 bank, u32 word)
+{
+ s32 size = ARRAY_SIZE(s400_api_mapping_table);
+ s32 i;
+
+ /* map the fuse from ocotp fuse map to FSB*/
+ for (i = 0; i < size; i++) {
+ if (s400_api_mapping_table[i].fuse_bank != -1 &&
+ s400_api_mapping_table[i].fuse_bank == bank) {
+ if (word >= s400_api_mapping_table[i].fuse_offset &&
+ word < (s400_api_mapping_table[i].fuse_offset +
+ s400_api_mapping_table[i].fuse_words))
+ break;
+ }
+ }
+
+ if (i == size)
+ return -1; /* Failed to find */
+
+ if (s400_api_mapping_table[i].s400_index != 0)
+ return s400_api_mapping_table[i].s400_index;
+
+ return s400_api_mapping_table[i].fuse_bank * 8 + word;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ s32 word_index;
+ bool redundancy;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+
+ return 0;
+ }
+
+ word_index = map_s400_fuse_index(bank, word);
+ if (word_index >= 0) {
+ u32 data[4];
+ u32 res, size = 4;
+ int ret;
+
+ /* Only UID return 4 words */
+ if (word_index != 1)
+ size = 1;
+
+ ret = ahab_read_common_fuse(word_index, data, size, &res);
+ if (ret) {
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ if (word_index == 1) {
+ *val = data[word]; /* UID */
+ } else if (word_index == 2) {
+ /*
+ * OTFAD 3 bits as follow:
+ * bit 0: OTFAD_ENABLE
+ * bit 1: OTFAD_DISABLE_OVERRIDE
+ * bit 2: KEY_BLOB_EN
+ */
+ *val = data[0] << 3;
+ } else {
+ *val = data[0];
+ }
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ return fuse_sense(bank, word, val);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ u32 res;
+ int ret;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ ret = ahab_write_fuse((bank * 8 + word), val, false, &res);
+ if (ret) {
+ printf("ahab write fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ return 0;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ printf("Override fuse to i.MX8ULP in u-boot is forbidden\n");
+ return -EPERM;
+}
diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c
new file mode 100644
index 0000000000..333ebdf576
--- /dev/null
+++ b/drivers/misc/imx8ulp/imx8ulp_mu.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
+#include <asm/arch/s400_api.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/iopoll.h>
+#include <misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct imx8ulp_mu {
+ struct mu_type *base;
+};
+
+#define MU_SR_TE0_MASK BIT(0)
+#define MU_SR_RF0_MASK BIT(0)
+#define MU_TR_COUNT 4
+#define MU_RR_COUNT 4
+
+void mu_hal_init(ulong base)
+{
+ struct mu_type *mu_base = (struct mu_type *)base;
+
+ writel(0, &mu_base->tcr);
+ writel(0, &mu_base->rcr);
+}
+
+int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
+{
+ struct mu_type *mu_base = (struct mu_type *)base;
+ u32 mask = MU_SR_TE0_MASK << reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ debug("sendmsg sr 0x%x\n", readl(&mu_base->sr));
+
+ /* Wait TX register to be empty. */
+ ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000);
+ if (ret < 0) {
+ debug("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ debug("tr[%d] 0x%x\n", reg_index, msg);
+
+ writel(msg, &mu_base->tr[reg_index]);
+
+ return 0;
+}
+
+int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
+{
+ struct mu_type *mu_base = (struct mu_type *)base;
+ u32 mask = MU_SR_RF0_MASK << reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));
+
+ /* Wait RX register to be full. */
+ ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000);
+ if (ret < 0) {
+ debug("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ *msg = readl(&mu_base->rr[reg_index]);
+
+ debug("rr[%d] 0x%x\n", reg_index, *msg);
+
+ return 0;
+}
+
+static int imx8ulp_mu_read(struct mu_type *base, void *data)
+{
+ struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
+ int ret;
+ u8 count = 0;
+
+ if (!msg)
+ return -EINVAL;
+
+ /* Read first word */
+ ret = mu_hal_receivemsg((ulong)base, 0, (u32 *)msg);
+ if (ret)
+ return ret;
+ count++;
+
+ /* Check size */
+ if (msg->size > S400_MAX_MSG) {
+ *((u32 *)msg) = 0;
+ return -EINVAL;
+ }
+
+ /* Read remaining words */
+ while (count < msg->size) {
+ ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT,
+ &msg->data[count - 1]);
+ if (ret)
+ return ret;
+ count++;
+ }
+
+ return 0;
+}
+
+static int imx8ulp_mu_write(struct mu_type *base, void *data)
+{
+ struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
+ int ret;
+ u8 count = 0;
+
+ if (!msg)
+ return -EINVAL;
+
+ /* Check size */
+ if (msg->size > S400_MAX_MSG)
+ return -EINVAL;
+
+ /* Write first word */
+ ret = mu_hal_sendmsg((ulong)base, 0, *((u32 *)msg));
+ if (ret)
+ return ret;
+ count++;
+
+ /* Write remaining words */
+ while (count < msg->size) {
+ ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT,
+ msg->data[count - 1]);
+ if (ret)
+ return ret;
+ count++;
+ }
+
+ return 0;
+}
+
+/*
+ * Note the function prototype use msgid as the 2nd parameter, here
+ * we take it as no_resp.
+ */
+static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg,
+ int tx_size, void *rx_msg, int rx_size)
+{
+ struct imx8ulp_mu *priv = dev_get_priv(dev);
+ u32 result;
+ int ret;
+
+ /* Expect tx_msg, rx_msg are the same value */
+ if (rx_msg && tx_msg != rx_msg)
+ printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
+
+ ret = imx8ulp_mu_write(priv->base, tx_msg);
+ if (ret)
+ return ret;
+ if (!no_resp) {
+ ret = imx8ulp_mu_read(priv->base, rx_msg);
+ if (ret)
+ return ret;
+ }
+
+ result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0];
+ if ((result & 0xff) == 0xd6)
+ return 0;
+
+ return -EIO;
+}
+
+static int imx8ulp_mu_probe(struct udevice *dev)
+{
+ struct imx8ulp_mu *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = (struct mu_type *)addr;
+
+ debug("mu base 0x%lx\n", (ulong)priv->base);
+
+ /* U-Boot not enable interrupts, so need to enable RX interrupts */
+ mu_hal_init((ulong)priv->base);
+
+ gd->arch.s400_dev = dev;
+
+ return 0;
+}
+
+static int imx8ulp_mu_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+static int imx8ulp_mu_bind(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+static struct misc_ops imx8ulp_mu_ops = {
+ .call = imx8ulp_mu_call,
+};
+
+static const struct udevice_id imx8ulp_mu_ids[] = {
+ { .compatible = "fsl,imx8ulp-mu" },
+ { }
+};
+
+U_BOOT_DRIVER(imx8ulp_mu) = {
+ .name = "imx8ulp_mu",
+ .id = UCLASS_MISC,
+ .of_match = imx8ulp_mu_ids,
+ .probe = imx8ulp_mu_probe,
+ .bind = imx8ulp_mu_bind,
+ .remove = imx8ulp_mu_remove,
+ .ops = &imx8ulp_mu_ops,
+ .priv_auto = sizeof(struct imx8ulp_mu),
+};
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
new file mode 100644
index 0000000000..d76a95febe
--- /dev/null
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <asm/arch/s400_api.h>
+#include <misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ if (xrdc)
+ msg.data[0] = (0x78 << 8) | core_id;
+ else
+ msg.data[0] = (0x74 << 8) | core_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, core id %u, response 0x%x\n",
+ __func__, ret, core_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 3;
+ msg.command = AHAB_AUTH_OEM_CTNR_CID;
+ msg.data[0] = upper_32_bits(ctnr_addr);
+ msg.data[1] = lower_32_bits(ctnr_addr);
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n",
+ __func__, ret, ctnr_addr, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_release_container(u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_RELEASE_CTNR_CID;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_verify_image(u32 img_id, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_VERIFY_IMG_CID;
+ msg.data[0] = 1 << img_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, img_id %u, response 0x%x\n",
+ __func__, ret, img_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID;
+ msg.data[0] = life_cycle;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n",
+ __func__, ret, life_cycle, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!fuse_words) {
+ printf("Invalid parameters for fuse read\n");
+ return -EINVAL;
+ }
+
+ if ((fuse_id != 1 && fuse_num != 1) ||
+ (fuse_id == 1 && fuse_num != 4)) {
+ printf("Invalid fuse number parameter\n");
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_READ_FUSE_REQ_CID;
+ msg.data[0] = fuse_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ fuse_words[0] = msg.data[1];
+ if (fuse_id == 1) {
+ /* OTP_UNIQ_ID */
+ fuse_words[1] = msg.data[2];
+ fuse_words[2] = msg.data[3];
+ fuse_words[3] = msg.data[4];
+ }
+
+ return ret;
+}
+
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 3;
+ msg.command = AHAB_WRITE_FUSE_REQ_CID;
+ msg.data[0] = (32 << 16) | (fuse_id << 5);
+ if (lock)
+ msg.data[0] |= (1 << 31);
+
+ msg.data[1] = fuse_val;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
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