diff options
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/Kconfig | 27 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 2 | ||||
| -rw-r--r-- | drivers/i2c/at91_i2c.c | 338 | ||||
| -rw-r--r-- | drivers/i2c/at91_i2c.h | 77 | ||||
| -rw-r--r-- | drivers/i2c/cros_ec_ldo.c | 1 | ||||
| -rw-r--r-- | drivers/i2c/cros_ec_tunnel.c | 1 | ||||
| -rw-r--r-- | drivers/i2c/fsl_i2c.c | 9 | ||||
| -rw-r--r-- | drivers/i2c/i2c-uclass-compat.c | 2 | ||||
| -rw-r--r-- | drivers/i2c/i2c-uclass.c | 21 | ||||
| -rw-r--r-- | drivers/i2c/i2c-uniphier-f.c | 17 | ||||
| -rw-r--r-- | drivers/i2c/i2c-uniphier.c | 17 | ||||
| -rw-r--r-- | drivers/i2c/intel_i2c.c | 291 | ||||
| -rw-r--r-- | drivers/i2c/muxes/i2c-mux-uclass.c | 1 | ||||
| -rw-r--r-- | drivers/i2c/mvtwsi.c | 777 | ||||
| -rw-r--r-- | drivers/i2c/omap24xx_i2c.c | 407 | ||||
| -rw-r--r-- | drivers/i2c/s3c24x0_i2c.c | 2 | ||||
| -rw-r--r-- | drivers/i2c/sandbox_i2c.c | 4 | ||||
| -rw-r--r-- | drivers/i2c/tegra186_bpmp_i2c.c | 129 | ||||
| -rw-r--r-- | drivers/i2c/tegra_i2c.c | 89 |
19 files changed, 1791 insertions, 421 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 6e22bbadff..1537b673fe 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,16 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt +config SYS_I2C_AT91 + bool "Atmel I2C driver" + depends on DM_I2C && ARCH_AT91 + help + Add support for the Atmel I2C driver. A serious problem is that there + is no documented way to issue repeated START conditions for more than + two messages, as needed to support combined I2C messages. Use the + i2c-gpio driver unless your system can cope with this limitation. + Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt + config SYS_I2C_FSL bool "Freescale I2C bus driver" depends on DM_I2C @@ -154,6 +164,23 @@ config SYS_I2C_UNIPHIER_F Support for UniPhier FIFO-builtin I2C controller driver. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. +config SYS_I2C_MVTWSI + bool "Marvell I2C driver" + depends on DM_I2C + help + Support for Marvell I2C controllers as used on the orion5x and + kirkwood SoC families. + +config TEGRA186_BPMP_I2C + bool "Enable Tegra186 BPMP-based I2C driver" + depends on TEGRA186_BPMP + help + Support for Tegra I2C controllers managed by the BPMP (Boot and + Power Management Processor). On Tegra186, some I2C controllers are + directly controlled by the main CPU, whereas others are controlled + by the BPMP, and can only be accessed by the main CPU via IPC + requests to the BPMP. This driver covers the latter case. + source "drivers/i2c/muxes/Kconfig" endmenu diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 167424db98..2987081991 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o @@ -41,5 +42,6 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o +obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c new file mode 100644 index 0000000000..8e9c3ad552 --- /dev/null +++ b/drivers/i2c/at91_i2c.c @@ -0,0 +1,338 @@ +/* + * Atmel I2C driver. + * + * (C) Copyright 2016 Songjun Wu <songjun.wu@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <common.h> +#include <clk_client.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <i2c.h> +#include <linux/bitops.h> +#include <mach/clk.h> + +#include "at91_i2c.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define I2C_TIMEOUT_MS 100 + +static int at91_wait_for_xfer(struct at91_i2c_bus *bus, u32 status) +{ + struct at91_i2c_regs *reg = bus->regs; + ulong start_time = get_timer(0); + u32 sr; + + bus->status = 0; + + do { + sr = readl(®->sr); + bus->status |= sr; + + if (sr & TWI_SR_NACK) + return -EREMOTEIO; + else if (sr & status) + return 0; + } while (get_timer(start_time) < I2C_TIMEOUT_MS); + + return -ETIMEDOUT; +} + +static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg) +{ + struct at91_i2c_regs *reg = bus->regs; + bool is_read = msg->flags & I2C_M_RD; + u32 i; + int ret = 0; + + readl(®->sr); + if (is_read) { + writel(TWI_CR_START, ®->cr); + + for (i = 0; !ret && i < (msg->len - 1); i++) { + ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); + msg->buf[i] = readl(®->rhr); + } + + if (ret) + goto error; + + writel(TWI_CR_STOP, ®->cr); + + ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); + if (ret) + goto error; + + msg->buf[i] = readl(®->rhr); + + } else { + writel(msg->buf[0], ®->thr); + for (i = 1; !ret && (i < msg->len); i++) { + writel(msg->buf[i], ®->thr); + ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY); + } + + if (ret) + goto error; + + writel(TWI_CR_STOP, ®->cr); + } + + if (!ret) + ret = at91_wait_for_xfer(bus, TWI_SR_TXCOMP); + + if (ret) + goto error; + + if (bus->status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_LOCK)) { + ret = -EIO; + goto error; + } + + return 0; + +error: + if (bus->status & TWI_SR_LOCK) + writel(TWI_CR_LOCKCLR, ®->cr); + + return ret; +} + +static int at91_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + struct at91_i2c_regs *reg = bus->regs; + struct i2c_msg *m_start = msg; + bool is_read; + u32 int_addr_flag = 0; + int ret = 0; + + if (nmsgs == 2) { + int internal_address = 0; + int i; + + /* 1st msg is put into the internal address, start with 2nd */ + m_start = &msg[1]; + + /* the max length of internal address is 3 bytes */ + if (msg->len > 3) + return -EFAULT; + + for (i = 0; i < msg->len; ++i) { + const unsigned addr = msg->buf[msg->len - 1 - i]; + + internal_address |= addr << (8 * i); + int_addr_flag += TWI_MMR_IADRSZ_1; + } + + writel(internal_address, ®->iadr); + } + + is_read = m_start->flags & I2C_M_RD; + + writel((m_start->addr << 16) | int_addr_flag | + (is_read ? TWI_MMR_MREAD : 0), ®->mmr); + + ret = at91_i2c_xfer_msg(bus, m_start); + + return ret; +} + +/* + * Calculate symmetric clock as stated in datasheet: + * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) + */ +static void at91_calc_i2c_clock(struct udevice *dev, int i2c_clk) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + const struct at91_i2c_pdata *pdata = bus->pdata; + int offset = pdata->clk_offset; + int max_ckdiv = pdata->clk_max_div; + int ckdiv, cdiv, div; + unsigned long src_rate; + + src_rate = bus->bus_clk_rate; + + div = max(0, (int)DIV_ROUND_UP(src_rate, 2 * i2c_clk) - offset); + ckdiv = fls(div >> 8); + cdiv = div >> ckdiv; + + if (ckdiv > max_ckdiv) { + ckdiv = max_ckdiv; + cdiv = 255; + } + + bus->speed = DIV_ROUND_UP(src_rate, + (cdiv * (1 << ckdiv) + offset) * 2); + + bus->cwgr_val = (ckdiv << 16) | (cdiv << 8) | cdiv; +} + +static int at91_i2c_enable_clk(struct udevice *dev) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + struct udevice *dev_clk; + struct clk clk; + ulong clk_rate; + int periph; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev_clk, 0, &clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -ENODEV; + + bus->bus_clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +} + +static int at91_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + struct at91_i2c_regs *reg = bus->regs; + int ret; + + ret = at91_i2c_enable_clk(dev); + if (ret) + return ret; + + writel(TWI_CR_SWRST, ®->cr); + + at91_calc_i2c_clock(dev, bus->clock_frequency); + + writel(bus->cwgr_val, ®->cwgr); + writel(TWI_CR_MSEN, ®->cr); + writel(TWI_CR_SVDIS, ®->cr); + + return 0; +} + +static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + + at91_calc_i2c_clock(dev, speed); + + writel(bus->cwgr_val, &bus->regs->cwgr); + + return 0; +} + +int at91_i2c_get_bus_speed(struct udevice *dev) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + + return bus->speed; +} + +static int at91_i2c_ofdata_to_platdata(struct udevice *dev) +{ + const void *blob = gd->fdt_blob; + struct at91_i2c_bus *bus = dev_get_priv(dev); + int node = dev->of_offset; + + bus->regs = (struct at91_i2c_regs *)dev_get_addr(dev); + bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev); + bus->clock_frequency = fdtdec_get_int(blob, node, + "clock-frequency", 100000); + + return 0; +} + +static const struct dm_i2c_ops at91_i2c_ops = { + .xfer = at91_i2c_xfer, + .probe_chip = at91_i2c_probe, + .set_bus_speed = at91_i2c_set_bus_speed, + .get_bus_speed = at91_i2c_get_bus_speed, +}; + +static const struct at91_i2c_pdata at91rm9200_config = { + .clk_max_div = 5, + .clk_offset = 3, +}; + +static const struct at91_i2c_pdata at91sam9261_config = { + .clk_max_div = 5, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9260_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9g20_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9g10_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9x5_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata sama5d4_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata sama5d2_config = { + .clk_max_div = 7, + .clk_offset = 3, +}; + +static const struct udevice_id at91_i2c_ids[] = { +{ .compatible = "atmel,at91rm9200-i2c", .data = (long)&at91rm9200_config }, +{ .compatible = "atmel,at91sam9260-i2c", .data = (long)&at91sam9260_config }, +{ .compatible = "atmel,at91sam9261-i2c", .data = (long)&at91sam9261_config }, +{ .compatible = "atmel,at91sam9g20-i2c", .data = (long)&at91sam9g20_config }, +{ .compatible = "atmel,at91sam9g10-i2c", .data = (long)&at91sam9g10_config }, +{ .compatible = "atmel,at91sam9x5-i2c", .data = (long)&at91sam9x5_config }, +{ .compatible = "atmel,sama5d4-i2c", .data = (long)&sama5d4_config }, +{ .compatible = "atmel,sama5d2-i2c", .data = (long)&sama5d2_config }, +{ } +}; + +U_BOOT_DRIVER(i2c_at91) = { + .name = "i2c_at91", + .id = UCLASS_I2C, + .of_match = at91_i2c_ids, + .ofdata_to_platdata = at91_i2c_ofdata_to_platdata, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .priv_auto_alloc_size = sizeof(struct at91_i2c_bus), + .ops = &at91_i2c_ops, +}; diff --git a/drivers/i2c/at91_i2c.h b/drivers/i2c/at91_i2c.h new file mode 100644 index 0000000000..87f02bfaf3 --- /dev/null +++ b/drivers/i2c/at91_i2c.h @@ -0,0 +1,77 @@ +#ifndef _AT91_I2C_H +#define _AT91_I2C_H + +#define TWI_CR_START BIT(0) /* Send a Start Condition */ +#define TWI_CR_MSEN BIT(2) /* Master Transfer Enable */ +#define TWI_CR_STOP BIT(1) /* Send a Stop Condition */ +#define TWI_CR_SVDIS BIT(5) /* Slave Transfer Disable */ +#define TWI_CR_SWRST BIT(7) /* Software Reset */ +#define TWI_CR_ACMEN BIT(16) /* Alternative Command Mode Enable */ +#define TWI_CR_ACMDIS BIT(17) /* Alternative Command Mode Disable */ +#define TWI_CR_LOCKCLR BIT(26) /* Lock Clear */ + +#define TWI_MMR_MREAD BIT(12) /* Master Read Direction */ +#define TWI_MMR_IADRSZ_1 BIT(8) /* Internal Device Address Size */ + +#define TWI_SR_TXCOMP BIT(0) /* Transmission Complete */ +#define TWI_SR_RXRDY BIT(1) /* Receive Holding Register Ready */ +#define TWI_SR_TXRDY BIT(2) /* Transmit Holding Register Ready */ +#define TWI_SR_OVRE BIT(6) /* Overrun Error */ +#define TWI_SR_UNRE BIT(7) /* Underrun Error */ +#define TWI_SR_NACK BIT(8) /* Not Acknowledged */ +#define TWI_SR_LOCK BIT(23) /* TWI Lock due to Frame Errors */ + +#define TWI_ACR_DATAL(len) ((len) & 0xff) +#define TWI_ACR_DIR_READ BIT(8) + +#define TWI_CWGR_HOLD_MAX 0x1f +#define TWI_CWGR_HOLD(x) (((x) & TWI_CWGR_HOLD_MAX) << 24) + +struct at91_i2c_regs { + u32 cr; + u32 mmr; + u32 smr; + u32 iadr; + u32 cwgr; + u32 rev_0[3]; + u32 sr; + u32 ier; + u32 idr; + u32 imr; + u32 rhr; + u32 thr; + u32 smbtr; + u32 rev_1; + u32 acr; + u32 filtr; + u32 rev_2; + u32 swmr; + u32 fmr; + u32 flr; + u32 rev_3; + u32 fsr; + u32 fier; + u32 fidr; + u32 fimr; + u32 rev_4[29]; + u32 wpmr; + u32 wpsr; + u32 rev_5[6]; +}; + +struct at91_i2c_pdata { + unsigned clk_max_div; + unsigned clk_offset; +}; + +struct at91_i2c_bus { + struct at91_i2c_regs *regs; + u32 status; + ulong bus_clk_rate; + u32 clock_frequency; + u32 speed; + u32 cwgr_val; + const struct at91_i2c_pdata *pdata; +}; + +#endif diff --git a/drivers/i2c/cros_ec_ldo.c b/drivers/i2c/cros_ec_ldo.c index b817c61f1c..a4cd660406 100644 --- a/drivers/i2c/cros_ec_ldo.c +++ b/drivers/i2c/cros_ec_ldo.c @@ -72,6 +72,5 @@ U_BOOT_DRIVER(cros_ec_ldo) = { .name = "cros_ec_ldo_tunnel", .id = UCLASS_I2C, .of_match = cros_ec_i2c_ids, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &cros_ec_i2c_ops, }; diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c index 7ab1fd898a..e2c6e44795 100644 --- a/drivers/i2c/cros_ec_tunnel.c +++ b/drivers/i2c/cros_ec_tunnel.c @@ -36,6 +36,5 @@ U_BOOT_DRIVER(cros_ec_tunnel) = { .name = "cros_ec_tunnel", .id = UCLASS_I2C, .of_match = cros_ec_i2c_ids, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &cros_ec_i2c_ops, }; diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index b8cc647bd3..c3f826d68c 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -583,12 +583,11 @@ static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) { struct fsl_i2c_dev *dev = dev_get_priv(bus); - u64 reg; - u32 addr, size; + fdt_addr_t addr; + fdt_size_t size; - reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg"); - addr = reg >> 32; - size = reg & 0xFFFFFFFF; + addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, bus->of_offset, + "reg", 0, &size, false); dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size); diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c index 5606d1f807..de78db6a88 100644 --- a/drivers/i2c/i2c-uclass-compat.c +++ b/drivers/i2c/i2c-uclass-compat.c @@ -9,7 +9,7 @@ #include <errno.h> #include <i2c.h> -static int cur_busnum; +static int cur_busnum __attribute__((section(".data"))); static int i2c_compat_get_device(uint chip_addr, int alen, struct udevice **devp) diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 50b99ead3d..dbd3789747 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -12,7 +12,6 @@ #include <malloc.h> #include <dm/device-internal.h> #include <dm/lists.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -467,6 +466,7 @@ int i2c_deblock(struct udevice *bus) return ops->deblock(bus); } +#if CONFIG_IS_ENABLED(OF_CONTROL) int i2c_chip_ofdata_to_platdata(const void *blob, int node, struct dm_i2c_chip *chip) { @@ -482,38 +482,43 @@ int i2c_chip_ofdata_to_platdata(const void *blob, int node, return 0; } +#endif static int i2c_post_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_CONTROL) struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock-frequency", 100000); return dm_i2c_set_bus_speed(dev, i2c->speed_hz); -} - -static int i2c_post_bind(struct udevice *dev) -{ - /* Scan the bus for devices */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +#else + return 0; +#endif } static int i2c_child_post_bind(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_CONTROL) struct dm_i2c_chip *plat = dev_get_parent_platdata(dev); if (dev->of_offset == -1) return 0; return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat); +#else + return 0; +#endif } UCLASS_DRIVER(i2c) = { .id = UCLASS_I2C, .name = "i2c", .flags = DM_UC_FLAG_SEQ_ALIAS, - .post_bind = i2c_post_bind, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .post_bind = dm_scan_fdt_dev, +#endif .post_probe = i2c_post_probe, .per_device_auto_alloc_size = sizeof(struct dm_i2c_bus), .per_child_platdata_auto_alloc_size = sizeof(struct dm_i2c_chip), diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c index aebdcfcec3..a56e058d56 100644 --- a/drivers/i2c/i2c-uniphier-f.c +++ b/drivers/i2c/i2c-uniphier-f.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,7 +15,6 @@ #include <dm/root.h> #include <i2c.h> #include <fdtdec.h> -#include <mapmem.h> struct uniphier_fi2c_regs { u32 cr; /* control register */ @@ -118,7 +119,7 @@ static int uniphier_fi2c_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->regs = map_sysmem(addr, SZ_128); + priv->regs = devm_ioremap(dev, addr, SZ_128); if (!priv->regs) return -ENOMEM; @@ -134,15 +135,6 @@ static int uniphier_fi2c_probe(struct udevice *dev) return 0; } -static int uniphier_fi2c_remove(struct udevice *dev) -{ - struct uniphier_fi2c_dev *priv = dev_get_priv(dev); - - unmap_sysmem(priv->regs); - - return 0; -} - static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags, bool *stop) { @@ -359,7 +351,6 @@ U_BOOT_DRIVER(uniphier_fi2c) = { .id = UCLASS_I2C, .of_match = uniphier_fi2c_of_match, .probe = uniphier_fi2c_probe, - .remove = uniphier_fi2c_remove, .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev), .ops = &uniphier_fi2c_ops, }; diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c index f8221da82e..39a3ebdfc1 100644 --- a/drivers/i2c/i2c-uniphier.c +++ b/drivers/i2c/i2c-uniphier.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,7 +15,6 @@ #include <dm/root.h> #include <i2c.h> #include <fdtdec.h> -#include <mapmem.h> struct uniphier_i2c_regs { u32 dtrm; /* data transmission */ @@ -53,7 +54,7 @@ static int uniphier_i2c_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->regs = map_sysmem(addr, SZ_64); + priv->regs = devm_ioremap(dev, addr, SZ_64); if (!priv->regs) return -ENOMEM; @@ -65,15 +66,6 @@ static int uniphier_i2c_probe(struct udevice *dev) return 0; } -static int uniphier_i2c_remove(struct udevice *dev) -{ - struct uniphier_i2c_dev *priv = dev_get_priv(dev); - - unmap_sysmem(priv->regs); - - return 0; -} - static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm) { writel(dtrm, &dev->regs->dtrm); @@ -220,7 +212,6 @@ U_BOOT_DRIVER(uniphier_i2c) = { .id = UCLASS_I2C, .of_match = uniphier_i2c_of_match, .probe = uniphier_i2c_probe, - .remove = uniphier_i2c_remove, .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev), .ops = &uniphier_i2c_ops, }; diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c index 3d777ff23e..a0182dc1cc 100644 --- a/drivers/i2c/intel_i2c.c +++ b/drivers/i2c/intel_i2c.c @@ -2,54 +2,290 @@ * Copyright (c) 2015 Google, Inc * Written by Simon Glass <sjg@chromium.org> * + * SMBus block read/write support added by Stefan Roese: + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <dm.h> #include <i2c.h> +#include <pci.h> #include <asm/io.h> -#include <asm/arch/pch.h> -int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_BASE 0x20 +#define HOSTC 0x40 +#define HST_EN (1 << 0) +#define SMB_RCV_SLVA 0x09 + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMBAUXCTL 0xd +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +/* I801 Hosts Status register bits */ +#define SMBHSTSTS_BYTE_DONE 0x80 +#define SMBHSTSTS_INUSE_STS 0x40 +#define SMBHSTSTS_SMBALERT_STS 0x20 +#define SMBHSTSTS_FAILED 0x10 +#define SMBHSTSTS_BUS_ERR 0x08 +#define SMBHSTSTS_DEV_ERR 0x04 +#define SMBHSTSTS_INTR 0x02 +#define SMBHSTSTS_HOST_BUSY 0x01 + +/* I801 Host Control register bits */ +#define SMBHSTCNT_INTREN 0x01 +#define SMBHSTCNT_KILL 0x02 +#define SMBHSTCNT_LAST_BYTE 0x20 +#define SMBHSTCNT_START 0x40 +#define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ + +/* Auxiliary control register bits, ICH4+ only */ +#define SMBAUXCTL_CRC 1 +#define SMBAUXCTL_E32B 2 + +#define SMBUS_TIMEOUT 100 /* 100 ms */ + +struct intel_i2c { + u32 base; + int running; +}; + +static int smbus_wait_until_ready(u32 base) { - return -ENOSYS; + unsigned long ts; + u8 byte; + + ts = get_timer(0); + do { + byte = inb(base + SMBHSTSTAT); + if (!(byte & 1)) + return 0; + } while (get_timer(ts) < SMBUS_TIMEOUT); + + return -ETIMEDOUT; } -int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags) +static int smbus_wait_until_done(u32 base) { - return -ENOSYS; + unsigned long ts; + u8 byte; + + ts = get_timer(0); + do { + byte = inb(base + SMBHSTSTAT); + if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0)) + return 0; + } while (get_timer(ts) < SMBUS_TIMEOUT); + + return -ETIMEDOUT; } -int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +static int smbus_block_read(u32 base, u8 dev, u8 *buffer, + int offset, int len) { + u8 buf_temp[32]; + int count; + int i; + + debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n", + __func__, __LINE__, dev, offset, len); + if (smbus_wait_until_ready(base) < 0) + return -ETIMEDOUT; + + /* Setup transaction */ + + /* Reset the data buffer index */ + inb(base + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD); + /* Set the command/address... */ + outb(offset & 0xff, base + SMBHSTCMD); + /* Set up for a block read */ + outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2), + (base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); + + /* Start the command */ + outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(base) < 0) { + printf("SMBUS read transaction timeout (dev=0x%x)\n", dev); + return -ETIMEDOUT; + } + + count = inb(base + SMBHSTDAT0); + debug("%s (%d): count=%d (len=%d)\n", __func__, __LINE__, count, len); + if (count == 0) { + debug("ERROR: len=0 on read\n"); + return -EIO; + } + + if (count < len) { + debug("ERROR: too few bytes read\n"); + return -EIO; + } + + if (count > 32) { + debug("ERROR: count=%d too high\n", count); + return -EIO; + } + + /* Read all available bytes from buffer */ + for (i = 0; i < count; i++) + buf_temp[i] = inb(base + SMBBLKDAT); + + memcpy(buffer, buf_temp, len); + + /* Return results of transaction */ + if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR)) + return -EIO; + return 0; } -static int intel_i2c_probe(struct udevice *dev) +static int smbus_block_write(u32 base, u8 dev, u8 *buffer, + int offset, int len) { + int i; + + debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n", + __func__, __LINE__, dev, offset, len); + if (smbus_wait_until_ready(base) < 0) + return -ETIMEDOUT; + + /* Setup transaction */ + /* Set the device I'm talking too */ + outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD); + /* Set the command/address... */ + outb(offset, base + SMBHSTCMD); + /* Set up for a block write */ + outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2), + (base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); + + /* Write count in DAT0 register */ + outb(len, base + SMBHSTDAT0); + + /* Write data bytes... */ + for (i = 0; i < len; i++) + outb(*buffer++, base + SMBBLKDAT); + + /* Start the command */ + outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(base) < 0) { + printf("SMBUS write transaction timeout (dev=0x%x)\n", dev); + return -ETIMEDOUT; + } + + /* Return results of transaction */ + if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR)) + return -EIO; + + return 0; +} + +static int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct intel_i2c *i2c = dev_get_priv(bus); + struct i2c_msg *dmsg, *omsg, dummy; + + debug("i2c_xfer: %d messages\n", nmsgs); + + memset(&dummy, 0, sizeof(struct i2c_msg)); + /* - * So far this is just setup code for ivybridge SMbus. When we have - * a full I2C driver this may need to be moved, generalised or made - * dependant on a particular compatible string. - * - * Set SMBus I/O base + * We expect either two messages (one with an offset and one with the + * actucal data) or one message (just data) */ - dm_pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + if (nmsgs > 2 || nmsgs == 0) { + debug("%s: Only one or two messages are supported", __func__); + return -EIO; + } + + omsg = nmsgs == 1 ? &dummy : msg; + dmsg = nmsgs == 1 ? msg : msg + 1; + + if (dmsg->flags & I2C_M_RD) + return smbus_block_read(i2c->base, dmsg->addr, &dmsg->buf[0], + omsg->buf[0], dmsg->len); + else + return smbus_block_write(i2c->base, dmsg->addr, &dmsg->buf[1], + dmsg->buf[0], dmsg->len - 1); +} + +static int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct intel_i2c *i2c = dev_get_priv(bus); + u8 buf[4]; + + return smbus_block_read(i2c->base, chip_addr, buf, 0, 1); +} + +static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + return 0; +} + +static int intel_i2c_probe(struct udevice *dev) +{ + struct intel_i2c *priv = dev_get_priv(dev); + u32 base; + + /* Save base address from PCI BAR */ + priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, + PCI_REGION_IO); + base = priv->base; /* Set SMBus enable. */ dm_pci_write_config8(dev, HOSTC, HST_EN); - /* Set SMBus I/O space enable. */ - dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + /* Disable interrupts */ + outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + /* Set 32-byte data buffer mode */ + outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - debug("SMBus controller enabled\n"); + return 0; +} + +static int intel_i2c_bind(struct udevice *dev) +{ + static int num_cards __attribute__ ((section(".data"))); + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + /* + * ToDo: + * Setting req_seq in the driver is probably not recommended. + * But without a DT alias the number is not configured. And + * using this driver is impossible for PCIe I2C devices. + * This can be removed, once a better (correct) way for this + * is found and implemented. + */ + dev->req_seq = num_cards; + sprintf(name, "intel_i2c#%u", num_cards++); + device_set_name(dev, name); + } return 0; } @@ -69,7 +305,18 @@ U_BOOT_DRIVER(intel_i2c) = { .name = "i2c_intel", .id = UCLASS_I2C, .of_match = intel_i2c_ids, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &intel_i2c_ops, + .priv_auto_alloc_size = sizeof(struct intel_i2c), + .bind = intel_i2c_bind, .probe = intel_i2c_probe, }; + +static struct pci_device_id intel_smbus_pci_supported[] = { + /* Intel BayTrail SMBus on the PCI bus */ + { PCI_VDEVICE(INTEL, 0x0f12) }, + /* Intel IvyBridge (Panther Point PCH) SMBus on the PCI bus */ + { PCI_VDEVICE(INTEL, 0x1e22) }, + {}, +}; + +U_BOOT_PCI_DEVICE(intel_i2c, intel_smbus_pci_supported); diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c b/drivers/i2c/muxes/i2c-mux-uclass.c index 3f52bff2fb..7a698b62b5 100644 --- a/drivers/i2c/muxes/i2c-mux-uclass.c +++ b/drivers/i2c/muxes/i2c-mux-uclass.c @@ -183,7 +183,6 @@ static const struct dm_i2c_ops i2c_mux_bus_ops = { U_BOOT_DRIVER(i2c_mux_bus) = { .name = "i2c_mux_bus_drv", .id = UCLASS_I2C, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &i2c_mux_bus_ops, }; diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index bf4443287f..ab7481a0d4 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -12,12 +12,19 @@ #include <i2c.h> #include <asm/errno.h> #include <asm/io.h> +#include <linux/compat.h> +#ifdef CONFIG_DM_I2C +#include <dm.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; /* - * include a file that will provide CONFIG_I2C_MVTWSI_BASE* - * and possibly other settings + * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other + * settings */ +#ifndef CONFIG_DM_I2C #if defined(CONFIG_ORION5X) #include <asm/arch/orion5x.h> #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) @@ -27,6 +34,7 @@ #else #error Driver mvtwsi not supported by SoC or board #endif +#endif /* CONFIG_DM_I2C */ /* * TWSI register structure @@ -51,8 +59,8 @@ struct mvtwsi_registers { u32 data; u32 control; union { - u32 status; /* when reading */ - u32 baudrate; /* when writing */ + u32 status; /* When reading */ + u32 baudrate; /* When writing */ }; u32 xtnd_slave_addr; u32 reserved[2]; @@ -61,20 +69,43 @@ struct mvtwsi_registers { #endif +#ifdef CONFIG_DM_I2C +struct mvtwsi_i2c_dev { + /* TWSI Register base for the device */ + struct mvtwsi_registers *base; + /* Number of the device (determined from cell-index property) */ + int index; + /* The I2C slave address for the device */ + u8 slaveadd; + /* The configured I2C speed in Hz */ + uint speed; + /* The current length of a clock period (depending on speed) */ + uint tick; +}; +#endif /* CONFIG_DM_I2C */ + /* - * Control register fields + * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control + * register */ - -#define MVTWSI_CONTROL_ACK 0x00000004 -#define MVTWSI_CONTROL_IFLG 0x00000008 -#define MVTWSI_CONTROL_STOP 0x00000010 -#define MVTWSI_CONTROL_START 0x00000020 -#define MVTWSI_CONTROL_TWSIEN 0x00000040 -#define MVTWSI_CONTROL_INTEN 0x00000080 +enum mvtwsi_ctrl_register_fields { + /* Acknowledge bit */ + MVTWSI_CONTROL_ACK = 0x00000004, + /* Interrupt flag */ + MVTWSI_CONTROL_IFLG = 0x00000008, + /* Stop bit */ + MVTWSI_CONTROL_STOP = 0x00000010, + /* Start bit */ + MVTWSI_CONTROL_START = 0x00000020, + /* I2C enable */ + MVTWSI_CONTROL_TWSIEN = 0x00000040, + /* Interrupt enable */ + MVTWSI_CONTROL_INTEN = 0x00000080, +}; /* - * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1, - * on other platforms it is a normal r/w bit which is cleared by writing 0. + * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1; + * on other platforms, it is a normal r/w bit, which is cleared by writing 0. */ #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -84,53 +115,95 @@ struct mvtwsi_registers { #endif /* - * Status register values -- only those expected in normal master - * operation on non-10-bit-address devices; whatever status we don't - * expect in nominal conditions (bus errors, arbitration losses, - * missing ACKs...) we just pass back to the caller as an error + * enum mvstwsi_status_values - Possible values of I2C controller's status + * register + * + * Only those statuses expected in normal master operation on + * non-10-bit-address devices are specified. + * + * Every status that's unexpected during normal operation (bus errors, + * arbitration losses, missing ACKs...) is passed back to the caller as an error * code. */ +enum mvstwsi_status_values { + /* START condition transmitted */ + MVTWSI_STATUS_START = 0x08, + /* Repeated START condition transmitted */ + MVTWSI_STATUS_REPEATED_START = 0x10, + /* Address + write bit transmitted, ACK received */ + MVTWSI_STATUS_ADDR_W_ACK = 0x18, + /* Data transmitted, ACK received */ + MVTWSI_STATUS_DATA_W_ACK = 0x28, + /* Address + read bit transmitted, ACK received */ + MVTWSI_STATUS_ADDR_R_ACK = 0x40, + /* Address + read bit transmitted, ACK not received */ + MVTWSI_STATUS_ADDR_R_NAK = 0x48, + /* Data received, ACK transmitted */ + MVTWSI_STATUS_DATA_R_ACK = 0x50, + /* Data received, ACK not transmitted */ + MVTWSI_STATUS_DATA_R_NAK = 0x58, + /* No relevant status */ + MVTWSI_STATUS_IDLE = 0xF8, +}; -#define MVTWSI_STATUS_START 0x08 -#define MVTWSI_STATUS_REPEATED_START 0x10 -#define MVTWSI_STATUS_ADDR_W_ACK 0x18 -#define MVTWSI_STATUS_DATA_W_ACK 0x28 -#define MVTWSI_STATUS_ADDR_R_ACK 0x40 -#define MVTWSI_STATUS_ADDR_R_NAK 0x48 -#define MVTWSI_STATUS_DATA_R_ACK 0x50 -#define MVTWSI_STATUS_DATA_R_NAK 0x58 -#define MVTWSI_STATUS_IDLE 0xF8 +/* + * enum mvstwsi_ack_flags - Determine whether a read byte should be + * acknowledged or not. + */ +enum mvtwsi_ack_flags { + /* Send NAK after received byte */ + MVTWSI_READ_NAK = 0, + /* Send ACK after received byte */ + MVTWSI_READ_ACK = 1, +}; /* - * MVTWSI controller base + * calc_tick() - Calculate the duration of a clock cycle from the I2C speed + * + * @speed: The speed in Hz to calculate the clock cycle duration for. + * @return The duration of a clock cycle in ns. */ +inline uint calc_tick(uint speed) +{ + /* One tick = the duration of a period at the specified speed in ns (we + * add 100 ns to be on the safe side) */ + return (1000000000u / speed) + 100; +} +#ifndef CONFIG_DM_I2C + +/* + * twsi_get_base() - Get controller register base for specified adapter + * + * @adap: Adapter to get the register base for. + * @return Register base for the specified adapter. + */ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { #ifdef CONFIG_I2C_MVTWSI_BASE0 case 0: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; #endif #ifdef CONFIG_I2C_MVTWSI_BASE1 case 1: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; #endif #ifdef CONFIG_I2C_MVTWSI_BASE2 case 2: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2; #endif #ifdef CONFIG_I2C_MVTWSI_BASE3 case 3: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3; #endif #ifdef CONFIG_I2C_MVTWSI_BASE4 case 4: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4; #endif #ifdef CONFIG_I2C_MVTWSI_BASE5 case 5: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5; #endif default: printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); @@ -139,30 +212,48 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) return NULL; } +#endif /* - * Returned statuses are 0 for success and nonzero otherwise. - * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. - * Thus to ease debugging, the return status contains some debug info: - * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'. - * - bits 23..16 are the last value of the control register. - * - bits 15..8 are the last value of the status register. - * - bits 7..0 are the expected value of the status register. + * enum mvtwsi_error_class - types of I2C errors */ +enum mvtwsi_error_class { + /* The controller returned a different status than expected */ + MVTWSI_ERROR_WRONG_STATUS = 0x01, + /* The controller timed out */ + MVTWSI_ERROR_TIMEOUT = 0x02, +}; -#define MVTWSI_ERROR_WRONG_STATUS 0x01 -#define MVTWSI_ERROR_TIMEOUT 0x02 - -#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \ - ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF)) +/* + * mvtwsi_error() - Build I2C return code from error information + * + * For debugging purposes, this function packs some information of an occurred + * error into a return code. These error codes are returned from I2C API + * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.). + * + * @ec: The error class of the error (enum mvtwsi_error_class). + * @lc: The last value of the control register. + * @ls: The last value of the status register. + * @es: The expected value of the status register. + * @return The generated error code. + */ +inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es) +{ + return ((ec << 24) & 0xFF000000) + | ((lc << 16) & 0x00FF0000) + | ((ls << 8) & 0x0000FF00) + | (es & 0xFF); +} /* - * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, - * return 0 (ok) or return 'wrong status'. + * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out. + * + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred, or the status was not the expected one. */ -static int twsi_wait(struct i2c_adapter *adap, int expected_status) +static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, + uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); int control, status; int timeout = 1000; @@ -173,105 +264,140 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status) if (status == expected_status) return 0; else - return MVTWSI_ERROR( + return mvtwsi_error( MVTWSI_ERROR_WRONG_STATUS, control, status, expected_status); } - udelay(10); /* one clock cycle at 100 kHz */ + ndelay(tick); /* One clock cycle */ } while (timeout--); status = readl(&twsi->status); - return MVTWSI_ERROR( - MVTWSI_ERROR_TIMEOUT, control, status, expected_status); + return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, + expected_status); } /* - * Assert the START condition, either in a single I2C transaction - * or inside back-to-back ones (repeated starts). + * twsi_start() - Assert a START condition on the bus. + * + * This function is used in both single I2C transactions and inside + * back-to-back transactions (repeated starts). + * + * @twsi: The MVTWSI register structure to use. + * @expected_status: The I2C bus status expected to be asserted after the + * operation completion. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred or the status was not the expected one. */ -static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags) +static int twsi_start(struct mvtwsi_registers *twsi, int expected_status, + uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* globally set TWSIEN in case it was not */ - *flags |= MVTWSI_CONTROL_TWSIEN; - /* assert START */ - writel(*flags | MVTWSI_CONTROL_START | - MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for controller to process START */ - return twsi_wait(adap, expected_status); + /* Assert START */ + writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START | + MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); + /* Wait for controller to process START */ + return twsi_wait(twsi, expected_status, tick); } /* - * Send a byte (i2c address or data). + * twsi_send() - Send a byte on the I2C bus. + * + * The byte may be part of an address byte or data. + * + * @twsi: The MVTWSI register structure to use. + * @byte: The byte to send. + * @expected_status: The I2C bus status expected to be asserted after the + * operation completion. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred or the status was not the expected one. */ -static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status, - u8 *flags) +static int twsi_send(struct mvtwsi_registers *twsi, u8 byte, + int expected_status, uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* put byte in data register for sending */ + /* Write byte to data register for sending */ writel(byte, &twsi->data); - /* clear any pending interrupt -- that'll cause sending */ - writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for controller to receive byte and check ACK */ - return twsi_wait(adap, expected_status); + /* Clear any pending interrupt -- that will cause sending */ + writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG, + &twsi->control); + /* Wait for controller to receive byte, and check ACK */ + return twsi_wait(twsi, expected_status, tick); } /* - * Receive a byte. - * Global mvtwsi_control_flags variable says if we should ack or nak. + * twsi_recv() - Receive a byte on the I2C bus. + * + * The static variable mvtwsi_control_flags controls whether we ack or nak. + * + * @twsi: The MVTWSI register structure to use. + * @byte: The byte to send. + * @ack_flag: Flag that determines whether the received byte should + * be acknowledged by the controller or not (sent ACK/NAK). + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred or the status was not the expected one. */ -static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags) +static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag, + uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - int expected_status, status; - - /* compute expected status based on ACK bit in global control flags */ - if (*flags & MVTWSI_CONTROL_ACK) - expected_status = MVTWSI_STATUS_DATA_R_ACK; - else - expected_status = MVTWSI_STATUS_DATA_R_NAK; - /* acknowledge *previous state* and launch receive */ - writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for controller to receive byte and assert ACK or NAK */ - status = twsi_wait(adap, expected_status); - /* if we did receive expected byte then store it */ + int expected_status, status, control; + + /* Compute expected status based on passed ACK flag */ + expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK : + MVTWSI_STATUS_DATA_R_NAK; + /* Acknowledge *previous state*, and launch receive */ + control = MVTWSI_CONTROL_TWSIEN; + control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0; + writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); + /* Wait for controller to receive byte, and assert ACK or NAK */ + status = twsi_wait(twsi, expected_status, tick); + /* If we did receive the expected byte, store it */ if (status == 0) *byte = readl(&twsi->data); - /* return status */ return status; } /* - * Assert the STOP condition. - * This is also used to force the bus back in idle (SDA=SCL=1). + * twsi_stop() - Assert a STOP condition on the bus. + * + * This function is also used to force the bus back to idle state (SDA = + * SCL = 1). + * + * @twsi: The MVTWSI register structure to use. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out + * occurred. */ -static int twsi_stop(struct i2c_adapter *adap, int status) +static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); int control, stop_status; + int status = 0; int timeout = 1000; - /* assert STOP */ + /* Assert STOP */ control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ + /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */ do { stop_status = readl(&twsi->status); if (stop_status == MVTWSI_STATUS_IDLE) break; - udelay(10); /* one clock cycle at 100 kHz */ + ndelay(tick); /* One clock cycle */ } while (timeout--); control = readl(&twsi->control); if (stop_status != MVTWSI_STATUS_IDLE) - if (status == 0) - status = MVTWSI_ERROR( - MVTWSI_ERROR_TIMEOUT, - control, status, MVTWSI_STATUS_IDLE); + status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT, + control, status, MVTWSI_STATUS_IDLE); return status; } -static unsigned int twsi_calc_freq(const int n, const int m) +/* + * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters. + * + * @n: Parameter 'n' for the frequency calculation algorithm. + * @m: Parameter 'm' for the frequency calculation algorithm. + * @return The I2C frequency corresponding to the passed m and n parameters. + */ +static uint twsi_calc_freq(const int n, const int m) { #ifdef CONFIG_SUNXI return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); @@ -281,176 +407,303 @@ static unsigned int twsi_calc_freq(const int n, const int m) } /* - * Reset controller. - * Controller reset also resets the baud rate and slave address, so - * they must be re-established afterwards. + * twsi_reset() - Reset the I2C controller. + * + * Resetting the controller also resets the baud rate and slave address, hence + * they must be re-established after the reset. + * + * @twsi: The MVTWSI register structure to use. */ -static void twsi_reset(struct i2c_adapter *adap) +static void twsi_reset(struct mvtwsi_registers *twsi) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* reset controller */ + /* Reset controller */ writel(0, &twsi->soft_reset); - /* wait 2 ms -- this is what the Marvell LSP does */ + /* Wait 2 ms -- this is what the Marvell LSP does */ udelay(20000); } /* - * I2C init called by cmd_i2c when doing 'i2c reset'. - * Sets baud to the highest possible value not exceeding requested one. + * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller. + * + * This function sets baud rate to the highest possible value that does not + * exceed the requested rate. + * + * @twsi: The MVTWSI register structure to use. + * @requested_speed: The desired frequency the controller should run at + * in Hz. + * @return The actual frequency the controller was configured to. */ -static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int requested_speed) +static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi, + uint requested_speed) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - unsigned int tmp_speed, highest_speed, n, m; - unsigned int baud = 0x44; /* baudrate at controller reset */ + uint tmp_speed, highest_speed, n, m; + uint baud = 0x44; /* Baud rate after controller reset */ - /* use actual speed to collect progressively higher values */ highest_speed = 0; - /* compute m, n setting for highest speed not above requested speed */ + /* Successively try m, n combinations, and use the combination + * resulting in the largest speed that's not above the requested + * speed */ for (n = 0; n < 8; n++) { for (m = 0; m < 16; m++) { tmp_speed = twsi_calc_freq(n, m); - if ((tmp_speed <= requested_speed) - && (tmp_speed > highest_speed)) { + if ((tmp_speed <= requested_speed) && + (tmp_speed > highest_speed)) { highest_speed = tmp_speed; baud = (m << 3) | n; } } } writel(baud, &twsi->baudrate); - return 0; + + /* Wait for controller for one tick */ +#ifdef CONFIG_DM_I2C + ndelay(calc_tick(highest_speed)); +#else + ndelay(10000); +#endif + return highest_speed; } -static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +/* + * __twsi_i2c_init() - Initialize the I2C controller. + * + * @twsi: The MVTWSI register structure to use. + * @speed: The initial frequency the controller should run at + * in Hz. + * @slaveadd: The I2C address to be set for the I2C master. + * @actual_speed: A output parameter that receives the actual frequency + * in Hz the controller was set to by the function. + * @return Zero if the operation succeeded, or a non-zero code if a time out + * occurred. + */ +static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, + int slaveadd, uint *actual_speed) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* reset controller */ - twsi_reset(adap); - /* set speed */ - twsi_i2c_set_bus_speed(adap, speed); - /* set slave address even though we don't use it */ + /* Reset controller */ + twsi_reset(twsi); + /* Set speed */ + *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed); + /* Set slave address; even though we don't use it */ writel(slaveadd, &twsi->slave_address); writel(0, &twsi->xtnd_slave_addr); - /* assert STOP but don't care for the result */ - (void) twsi_stop(adap, 0); + /* Assert STOP, but don't care for the result */ +#ifdef CONFIG_DM_I2C + (void) twsi_stop(twsi, calc_tick(*actual_speed)); +#else + (void) twsi_stop(twsi, 10000); +#endif } /* - * Begin I2C transaction with expected start status, at given address. - * Common to i2c_probe, i2c_read and i2c_write. - * Expected address status will derive from direction bit (bit 0) in addr. + * i2c_begin() - Start a I2C transaction. + * + * Begin a I2C transaction with a given expected start status and chip address. + * A START is asserted, and the address byte is sent to the I2C controller. The + * expected address status will be derived from the direction bit (bit 0) of + * the address byte. + * + * @twsi: The MVTWSI register structure to use. + * @expected_start_status: The I2C status the controller is expected to + * assert after the address byte was sent. + * @addr: The address byte to be sent. + * @tick: The duration of a clock cycle at the current + * I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int i2c_begin(struct i2c_adapter *adap, int expected_start_status, - u8 addr, u8 *flags) +static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status, + u8 addr, uint tick) { int status, expected_addr_status; - /* compute expected address status from direction bit in addr */ - if (addr & 1) /* reading */ + /* Compute the expected address status from the direction bit in + * the address byte */ + if (addr & 1) /* Reading */ expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; - else /* writing */ + else /* Writing */ expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; - /* assert START */ - status = twsi_start(adap, expected_start_status, flags); - /* send out the address if the start went well */ + /* Assert START */ + status = twsi_start(twsi, expected_start_status, tick); + /* Send out the address if the start went well */ if (status == 0) - status = twsi_send(adap, addr, expected_addr_status, - flags); - /* return ok or status of first failure to caller */ + status = twsi_send(twsi, addr, expected_addr_status, tick); + /* Return 0, or the status of the first failure */ return status; } /* - * I2C probe called by cmd_i2c when doing 'i2c probe'. - * Begin read, nak data byte, end. + * __twsi_i2c_probe_chip() - Probe the given I2C chip address. + * + * This function begins a I2C read transaction, does a dummy read and NAKs; if + * the procedure succeeds, the chip is considered to be present. + * + * @twsi: The MVTWSI register structure to use. + * @chip: The chip address to probe. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) +static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip, + uint tick) { u8 dummy_byte; - u8 flags = 0; int status; - /* begin i2c read */ - status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags); - /* dummy read was accepted: receive byte but NAK it. */ + /* Begin i2c read */ + status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick); + /* Dummy read was accepted: receive byte, but NAK it. */ if (status == 0) - status = twsi_recv(adap, &dummy_byte, &flags); + status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick); /* Stop transaction */ - twsi_stop(adap, 0); - /* return 0 or status of first failure */ + twsi_stop(twsi, tick); + /* Return 0, or the status of the first failure */ return status; } /* - * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c - * Begin write, send address byte(s), begin read, receive data bytes, end. - * - * NOTE: some EEPROMS want a stop right before the second start, while - * some will choke if it is there. Deciding which we should do is eeprom - * stuff, not i2c, but at the moment the APIs won't let us put it in - * cmd_eeprom, so we have to choose here, and for the moment that'll be - * a repeated start without a preceding stop. + * __twsi_i2c_read() - Read data from a I2C chip. + * + * This function begins a I2C write transaction, and transmits the address + * bytes; then begins a I2C read transaction, and receives the data bytes. + * + * NOTE: Some devices want a stop right before the second start, while some + * will choke if it is there. Since deciding this is not yet supported in + * higher level APIs, we need to make a decision here, and for the moment that + * will be a repeated start without a preceding stop. + * + * @twsi: The MVTWSI register structure to use. + * @chip: The chip address to read from. + * @addr: The address bytes to send. + * @alen: The length of the address bytes in bytes. + * @data: The buffer to receive the data read from the chip (has to have + * a size of at least 'length' bytes). + * @length: The amount of data to be read from the chip in bytes. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *data, int length) +static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, + u8 *addr, int alen, uchar *data, int length, + uint tick) { - int status; - u8 flags = 0; - - /* begin i2c write to send the address bytes */ - status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags); - /* send addr bytes */ - while ((status == 0) && alen--) - status = twsi_send(adap, addr >> (8*alen), - MVTWSI_STATUS_DATA_W_ACK, &flags); - /* begin i2c read to receive eeprom data bytes */ - if (status == 0) - status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START, - (chip << 1) | 1, &flags); - /* prepare ACK if at least one byte must be received */ - if (length > 0) - flags |= MVTWSI_CONTROL_ACK; - /* now receive actual bytes */ - while ((status == 0) && length--) { - /* reset NAK if we if no more to read now */ - if (length == 0) - flags &= ~MVTWSI_CONTROL_ACK; - /* read current byte */ - status = twsi_recv(adap, data++, &flags); + int status = 0; + int stop_status; + int expected_start = MVTWSI_STATUS_START; + + if (alen > 0) { + /* Begin i2c write to send the address bytes */ + status = i2c_begin(twsi, expected_start, (chip << 1), tick); + /* Send address bytes */ + while ((status == 0) && alen--) + status = twsi_send(twsi, *(addr++), + MVTWSI_STATUS_DATA_W_ACK, tick); + /* Send repeated STARTs after the initial START */ + expected_start = MVTWSI_STATUS_REPEATED_START; } + /* Begin i2c read to receive data bytes */ + if (status == 0) + status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick); + /* Receive actual data bytes; set NAK if we if we have nothing more to + * read */ + while ((status == 0) && length--) + status = twsi_recv(twsi, data++, + length > 0 ? + MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick); /* Stop transaction */ - status = twsi_stop(adap, status); - /* return 0 or status of first failure */ - return status; + stop_status = twsi_stop(twsi, tick); + /* Return 0, or the status of the first failure */ + return status != 0 ? status : stop_status; } /* - * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c - * Begin write, send address byte(s), send data bytes, end. + * __twsi_i2c_write() - Send data to a I2C chip. + * + * This function begins a I2C write transaction, and transmits the address + * bytes; then begins a new I2C write transaction, and sends the data bytes. + * + * @twsi: The MVTWSI register structure to use. + * @chip: The chip address to read from. + * @addr: The address bytes to send. + * @alen: The length of the address bytes in bytes. + * @data: The buffer containing the data to be sent to the chip. + * @length: The length of data to be sent to the chip in bytes. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *data, int length) +static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, + u8 *addr, int alen, uchar *data, int length, + uint tick) { - int status; - u8 flags = 0; - - /* begin i2c write to send the eeprom adress bytes then data bytes */ - status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags); - /* send addr bytes */ - while ((status == 0) && alen--) - status = twsi_send(adap, addr >> (8*alen), - MVTWSI_STATUS_DATA_W_ACK, &flags); - /* send data bytes */ + int status, stop_status; + + /* Begin i2c write to send first the address bytes, then the + * data bytes */ + status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick); + /* Send address bytes */ + while ((status == 0) && (alen-- > 0)) + status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK, + tick); + /* Send data bytes */ while ((status == 0) && (length-- > 0)) - status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK, - &flags); + status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK, + tick); /* Stop transaction */ - status = twsi_stop(adap, status); - /* return 0 or status of first failure */ - return status; + stop_status = twsi_stop(twsi, tick); + /* Return 0, or the status of the first failure */ + return status != 0 ? status : stop_status; +} + +#ifndef CONFIG_DM_I2C +static void twsi_i2c_init(struct i2c_adapter *adap, int speed, + int slaveadd) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + __twsi_i2c_init(twsi, speed, slaveadd, NULL); +} + +static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap, + uint requested_speed) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + __twsi_i2c_set_bus_speed(twsi, requested_speed); + return 0; +} + +static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + return __twsi_i2c_probe_chip(twsi, chip, 10000); +} + +static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + u8 addr_bytes[4]; + + addr_bytes[0] = (addr >> 0) & 0xFF; + addr_bytes[1] = (addr >> 8) & 0xFF; + addr_bytes[2] = (addr >> 16) & 0xFF; + addr_bytes[3] = (addr >> 24) & 0xFF; + + return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length, + 10000); +} + +static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + u8 addr_bytes[4]; + + addr_bytes[0] = (addr >> 0) & 0xFF; + addr_bytes[1] = (addr >> 8) & 0xFF; + addr_bytes[2] = (addr >> 16) & 0xFF; + addr_bytes[3] = (addr >> 24) & 0xFF; + + return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length, + 10000); } #ifdef CONFIG_I2C_MVTWSI_BASE0 @@ -494,3 +747,99 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) #endif +#else /* CONFIG_DM_I2C */ + +static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr, + u32 chip_flags) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick); +} + +static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + + dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed); + dev->tick = calc_tick(dev->speed); + + return 0; +} + +static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + + dev->base = dev_get_addr_ptr(bus); + + if (!dev->base) + return -ENOMEM; + + dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset, + "cell-index", -1); + dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset, + "u-boot,i2c-slave-addr", 0x0); + dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset, + "clock-frequency", 100000); + return 0; +} + +static int mvtwsi_i2c_probe(struct udevice *bus) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + uint actual_speed; + + __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); + dev->speed = actual_speed; + dev->tick = calc_tick(dev->speed); + return 0; +} + +static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + struct i2c_msg *dmsg, *omsg, dummy; + + memset(&dummy, 0, sizeof(struct i2c_msg)); + + /* We expect either two messages (one with an offset and one with the + * actual data) or one message (just data or offset/data combined) */ + if (nmsgs > 2 || nmsgs == 0) { + debug("%s: Only one or two messages are supported.", __func__); + return -1; + } + + omsg = nmsgs == 1 ? &dummy : msg; + dmsg = nmsgs == 1 ? msg : msg + 1; + + if (dmsg->flags & I2C_M_RD) + return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len, + dev->tick); + else + return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len, + dev->tick); +} + +static const struct dm_i2c_ops mvtwsi_i2c_ops = { + .xfer = mvtwsi_i2c_xfer, + .probe_chip = mvtwsi_i2c_probe_chip, + .set_bus_speed = mvtwsi_i2c_set_bus_speed, +}; + +static const struct udevice_id mvtwsi_i2c_ids[] = { + { .compatible = "marvell,mv64xxx-i2c", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(i2c_mvtwsi) = { + .name = "i2c_mvtwsi", + .id = UCLASS_I2C, + .of_match = mvtwsi_i2c_ids, + .probe = mvtwsi_i2c_probe, + .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev), + .ops = &mvtwsi_i2c_ops, +}; +#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a7f3fb4a79..0006343104 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -39,6 +39,7 @@ */ #include <common.h> +#include <dm.h> #include <i2c.h> #include <asm/arch/i2c.h> @@ -53,10 +54,14 @@ DECLARE_GLOBAL_DATA_PTR; /* Absolutely safe for status update at 100 kHz I2C: */ #define I2C_WAIT 200 -static int wait_for_bb(struct i2c_adapter *adap); -static struct i2c *omap24_get_base(struct i2c_adapter *adap); -static u16 wait_for_event(struct i2c_adapter *adap); -static void flush_fifo(struct i2c_adapter *adap); +struct omap_i2c { + struct udevice *clk; + struct i2c *regs; + unsigned int speed; + int waitdelay; + int clk_id; +}; + static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) { unsigned int sampleclk, prescaler; @@ -90,9 +95,96 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) } return -1; } -static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) + +/* + * Wait for the bus to be free by checking the Bus Busy (BB) + * bit to become clear + */ +static int wait_for_bb(struct i2c *i2c_base, int waitdelay) +{ + int timeout = I2C_TIMEOUT; + u16 stat; + + writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { +#else + /* Read RAW status */ + while ((stat = readw(&i2c_base->irqstatus_raw) & + I2C_STAT_BB) && timeout--) { +#endif + writew(stat, &i2c_base->stat); + udelay(waitdelay); + } + + if (timeout <= 0) { + printf("Timed out in wait_for_bb: status=%04x\n", + stat); + return 1; + } + writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ + return 0; +} + +/* + * Wait for the I2C controller to complete current action + * and update status + */ +static u16 wait_for_event(struct i2c *i2c_base, int waitdelay) +{ + u16 status; + int timeout = I2C_TIMEOUT; + + do { + udelay(waitdelay); +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + status = readw(&i2c_base->stat); +#else + /* Read RAW status */ + status = readw(&i2c_base->irqstatus_raw); +#endif + } while (!(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf("Timed out in wait_for_event: status=%04x\n", + status); + /* + * If status is still 0 here, probably the bus pads have + * not been configured for I2C, and/or pull-ups are missing. + */ + printf("Check if pads/pull-ups of bus are properly configured\n"); + writew(0xFFFF, &i2c_base->stat); + status = 0; + } + + return status; +} + +static void flush_fifo(struct i2c *i2c_base) +{ + u16 stat; + + /* + * note: if you try and read data when its not there or ready + * you get a bus error + */ + while (1) { + stat = readw(&i2c_base->stat); + if (stat == I2C_STAT_RRDY) { + readb(&i2c_base->data); + writew(I2C_STAT_RRDY, &i2c_base->stat); + udelay(1000); + } else + break; + } +} + +static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, + int *waitdelay) { - struct i2c *i2c_base = omap24_get_base(adap); int psc, fsscll = 0, fssclh = 0; int hsscll = 0, hssclh = 0; u32 scll = 0, sclh = 0; @@ -142,8 +234,7 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) } } - adap->speed = speed; - adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ + *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ writew(0, &i2c_base->con); writew(psc, &i2c_base->psc); writew(scll, &i2c_base->scll); @@ -154,9 +245,8 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) return 0; } -static void omap24_i2c_deblock(struct i2c_adapter *adap) +static void omap24_i2c_deblock(struct i2c *i2c_base) { - struct i2c *i2c_base = omap24_get_base(adap); int i; u16 systest; u16 orgsystest; @@ -200,9 +290,9 @@ static void omap24_i2c_deblock(struct i2c_adapter *adap) writew(orgsystest, &i2c_base->systest); } -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd, + int *waitdelay) { - struct i2c *i2c_base = omap24_get_base(adap); int timeout = I2C_TIMEOUT; int deblock = 1; @@ -224,7 +314,7 @@ retry: udelay(1000); } - if (0 != omap24_i2c_setspeed(adap, speed)) { + if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) { printf("ERROR: failed to setup I2C bus-speed!\n"); return; } @@ -241,45 +331,24 @@ retry: I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); /* Handle possible failed I2C state */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, *waitdelay)) if (deblock == 1) { - omap24_i2c_deblock(adap); + omap24_i2c_deblock(i2c_base); deblock = 0; goto retry; } } -static void flush_fifo(struct i2c_adapter *adap) -{ - struct i2c *i2c_base = omap24_get_base(adap); - u16 stat; - - /* - * note: if you try and read data when its not there or ready - * you get a bus error - */ - while (1) { - stat = readw(&i2c_base->stat); - if (stat == I2C_STAT_RRDY) { - readb(&i2c_base->data); - writew(I2C_STAT_RRDY, &i2c_base->stat); - udelay(1000); - } else - break; - } -} - /* * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ -static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) +static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip) { - struct i2c *i2c_base = omap24_get_base(adap); u16 status; int res = 1; /* default = fail */ @@ -287,7 +356,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) return res; /* Wait until bus is free */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, waitdelay)) return res; /* No data transfer, slave addr only */ @@ -296,7 +365,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* @@ -306,8 +375,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) * following 'if' section: */ if (status == I2C_STAT_XRDY) - printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n", + status); goto pr_exit; } @@ -315,7 +384,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { res = 0; /* Device found */ - udelay(adap->waitdelay);/* Required by AM335X in SPL */ + udelay(waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); @@ -323,7 +392,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) I2C_CON_STP, &i2c_base->con); /* STP */ } pr_exit: - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); return res; } @@ -341,10 +410,9 @@ pr_exit: * or that do not need a register address at all (such as some clock * distributors). */ -static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) +static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, + uint addr, int alen, uchar *buffer, int len) { - struct i2c *i2c_base = omap24_get_base(adap); int i2c_error = 0; u16 status; @@ -389,7 +457,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, #endif /* Wait until bus not busy */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, waitdelay)) return 1; /* Zero, one or two bytes reg address (offset) */ @@ -410,12 +478,12 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, #endif /* Send register offset */ while (1) { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; - printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n", + status); goto rd_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { @@ -450,7 +518,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, /* Receive data */ while (1) { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); /* * Try to identify bus that is not padconf'd for I2C. This * state could be left over from previous transactions if @@ -458,8 +526,8 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, */ if (status == I2C_STAT_XRDY) { i2c_error = 2; - printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n", + status); goto rd_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { @@ -477,16 +545,15 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, } rd_exit: - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); return i2c_error; } /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ -static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) +static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, + uint addr, int alen, uchar *buffer, int len) { - struct i2c *i2c_base = omap24_get_base(adap); int i; u16 status; int i2c_error = 0; @@ -536,7 +603,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, #endif /* Wait until bus not busy */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, waitdelay)) return 1; /* Start address phase - will write regoffset + len bytes data */ @@ -549,12 +616,12 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, while (alen) { /* Must write reg offset (one or two bytes) */ - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; - printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_write: pads on bus probably not configured (status=0x%x)\n", + status); goto wr_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { @@ -576,7 +643,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, } /* Address phase is over, now write data */ for (i = 0; i < len; i++) { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", @@ -598,87 +665,22 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, * transferred on the bus. */ do { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); } while (!(status & I2C_STAT_ARDY) && timeout--); if (timeout <= 0) printf("i2c_write: timed out writig last byte!\n"); wr_exit: - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); return i2c_error; } +#ifndef CONFIG_DM_I2C /* - * Wait for the bus to be free by checking the Bus Busy (BB) - * bit to become clear - */ -static int wait_for_bb(struct i2c_adapter *adap) -{ - struct i2c *i2c_base = omap24_get_base(adap); - int timeout = I2C_TIMEOUT; - u16 stat; - - writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { -#else - /* Read RAW status */ - while ((stat = readw(&i2c_base->irqstatus_raw) & - I2C_STAT_BB) && timeout--) { -#endif - writew(stat, &i2c_base->stat); - udelay(adap->waitdelay); - } - - if (timeout <= 0) { - printf("Timed out in wait_for_bb: status=%04x\n", - stat); - return 1; - } - writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ - return 0; -} - -/* - * Wait for the I2C controller to complete current action - * and update status + * The legacy I2C functions. These need to get removed once + * all users of this driver are converted to DM. */ -static u16 wait_for_event(struct i2c_adapter *adap) -{ - struct i2c *i2c_base = omap24_get_base(adap); - u16 status; - int timeout = I2C_TIMEOUT; - - do { - udelay(adap->waitdelay); -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - status = readw(&i2c_base->stat); -#else - /* Read RAW status */ - status = readw(&i2c_base->irqstatus_raw); -#endif - } while (!(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); - - if (timeout <= 0) { - printf("Timed out in wait_for_event: status=%04x\n", - status); - /* - * If status is still 0 here, probably the bus pads have - * not been configured for I2C, and/or pull-ups are missing. - */ - printf("Check if pads/pull-ups of bus %d are properly configured\n", - adap->hwadapnr); - writew(0xFFFF, &i2c_base->stat); - status = 0; - } - - return status; -} - static struct i2c *omap24_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { @@ -710,6 +712,56 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap) return NULL; } + +static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr, + alen, buffer, len); +} + + +static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr, + alen, buffer, len); +} + +static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int ret; + + ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay); + if (ret) { + error("%s: set i2c speed failed\n", __func__); + return ret; + } + + adap->speed = speed; + + return 0; +} + +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay); +} + +static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip); +} + #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED #endif @@ -769,3 +821,92 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, #endif #endif #endif + +#else /* CONFIG_DM_I2C */ + +static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct omap_i2c *priv = dev_get_priv(bus); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = __omap24_i2c_read(priv->regs, priv->waitdelay, + msg->addr, 0, 0, msg->buf, + msg->len); + } else { + ret = __omap24_i2c_write(priv->regs, priv->waitdelay, + msg->addr, 0, 0, msg->buf, + msg->len); + } + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + } + + return 0; +} + +static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + priv->speed = speed; + + return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay); +} + +static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr); +} + +static int omap_i2c_probe(struct udevice *bus) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay); + + return 0; +} + +static int omap_i2c_ofdata_to_platdata(struct udevice *bus) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + priv->regs = map_physmem(dev_get_addr(bus), sizeof(void *), + MAP_NOCACHE); + priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED; + + return 0; +} + +static const struct dm_i2c_ops omap_i2c_ops = { + .xfer = omap_i2c_xfer, + .probe_chip = omap_i2c_probe_chip, + .set_bus_speed = omap_i2c_set_bus_speed, +}; + +static const struct udevice_id omap_i2c_ids[] = { + { .compatible = "ti,omap4-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_omap) = { + .name = "i2c_omap", + .id = UCLASS_I2C, + .of_match = omap_i2c_ids, + .ofdata_to_platdata = omap_i2c_ofdata_to_platdata, + .probe = omap_i2c_probe, + .priv_auto_alloc_size = sizeof(struct omap_i2c), + .ops = &omap_i2c_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index dc9b661c1c..eab49d09ba 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -1433,7 +1433,6 @@ U_BOOT_DRIVER(i2c_s3c) = { .id = UCLASS_I2C, .of_match = s3c_i2c_ids, .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), .ops = &s3c_i2c_ops, }; @@ -1458,7 +1457,6 @@ U_BOOT_DRIVER(hs_i2c) = { .id = UCLASS_I2C, .of_match = exynos_hs_i2c_ids, .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), .ops = &exynos_hs_i2c_ops, }; diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index 2c84c41643..4696a1ae62 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -14,7 +14,6 @@ #include <asm/test.h> #include <dm/lists.h> #include <dm/device-internal.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -33,8 +32,7 @@ static int get_emul(struct udevice *dev, struct udevice **devp, *opsp = NULL; plat = dev_get_parent_platdata(dev); if (!plat->emul) { - ret = dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, - false); + ret = dm_scan_fdt_dev(dev); if (ret) return ret; diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c new file mode 100644 index 0000000000..88e8413d9e --- /dev/null +++ b/drivers/i2c/tegra186_bpmp_i2c.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <misc.h> +#include <asm/arch-tegra/bpmp_abi.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct tegra186_bpmp_i2c { + uint32_t bpmp_bus_id; +}; + +static inline void serialize_u16(uint8_t **p, uint16_t val) +{ + (*p)[0] = val & 0xff; + (*p)[1] = val >> 8; + (*p) += 2; +} + +/* These just happen to have the same values as I2C_M_* and SERIALI2C_* */ +#define SUPPORTED_FLAGS \ + (I2C_M_TEN | \ + I2C_M_RD | \ + I2C_M_STOP | \ + I2C_M_NOSTART | \ + I2C_M_REV_DIR_ADDR | \ + I2C_M_IGNORE_NAK | \ + I2C_M_NO_RD_ACK | \ + I2C_M_RECV_LEN) + +static int tegra186_bpmp_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct tegra186_bpmp_i2c *priv = dev_get_priv(dev); + struct mrq_i2c_request req; + struct mrq_i2c_response resp; + uint8_t *p; + int left, i, ret; + + req.cmd = CMD_I2C_XFER; + req.xfer.bus_id = priv->bpmp_bus_id; + p = &req.xfer.data_buf[0]; + left = ARRAY_SIZE(req.xfer.data_buf); + for (i = 0; i < nmsgs; i++) { + int len = 6; + if (!(msg[i].flags & I2C_M_RD)) + len += msg[i].len; + if ((len >= BIT(16)) || (len > left)) + return -ENOSPC; + + if (msg[i].flags & ~SUPPORTED_FLAGS) + return -EINVAL; + + serialize_u16(&p, msg[i].addr); + serialize_u16(&p, msg[i].flags); + serialize_u16(&p, msg[i].len); + if (!(msg[i].flags & I2C_M_RD)) { + memcpy(p, msg[i].buf, msg[i].len); + p += msg[i].len; + } + } + req.xfer.data_size = p - &req.xfer.data_buf[0]; + + ret = misc_call(dev->parent, MRQ_I2C, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + p = &resp.xfer.data_buf[0]; + left = resp.xfer.data_size; + if (left > ARRAY_SIZE(resp.xfer.data_buf)) + return -EINVAL; + for (i = 0; i < nmsgs; i++) { + if (msg[i].flags & I2C_M_RD) { + memcpy(msg[i].buf, p, msg[i].len); + p += msg[i].len; + } + } + + return 0; +} + +static int tegra186_bpmp_i2c_probe(struct udevice *dev) +{ + struct tegra186_bpmp_i2c *priv = dev_get_priv(dev); + int ret; + struct fdtdec_phandle_args args; + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + "nvidia,bpmp", NULL, 0, 0, &args); + if (ret < 0) { + debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n", + __func__, ret); + return ret; + } + + priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "nvidia,bpmp-bus-id", U32_MAX); + if (priv->bpmp_bus_id == U32_MAX) { + debug("%s: could not parse nvidia,bpmp-bus-id\n", __func__); + return -ENODEV; + } + + return 0; +} + +static const struct dm_i2c_ops tegra186_bpmp_i2c_ops = { + .xfer = tegra186_bpmp_i2c_xfer, +}; + +static const struct udevice_id tegra186_bpmp_i2c_ids[] = { + { .compatible = "nvidia,tegra186-bpmp-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_gpio) = { + .name = "tegra186_bpmp_i2c", + .id = UCLASS_I2C, + .of_match = tegra186_bpmp_i2c_ids, + .probe = tegra186_bpmp_i2c_probe, + .priv_auto_alloc_size = sizeof(struct tegra186_bpmp_i2c), + .ops = &tegra186_bpmp_i2c_ops, +}; diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 2fa07f9c57..31ba263b72 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -12,13 +12,27 @@ #include <fdtdec.h> #include <i2c.h> #include <asm/io.h> +#ifdef CONFIG_TEGRA186 +#include <clk.h> +#include <reset.h> +#else #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h> +#endif +#include <asm/arch/gpio.h> #include <asm/arch-tegra/tegra_i2c.h> +/* + * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that + * should not be present. These are needed because newer Tegra SoCs support + * only the standard clock/reset APIs, whereas older Tegra SoCs support only + * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be + * fixed to implement the standard APIs, and all drivers converted to solely + * use the new standard APIs, with no ifdefs. + */ + DECLARE_GLOBAL_DATA_PTR; enum i2c_type { @@ -30,7 +44,12 @@ enum i2c_type { /* Information about i2c controller */ struct i2c_bus { int id; +#ifdef CONFIG_TEGRA186 + struct reset_ctl reset_ctl; + struct clk clk; +#else enum periph_id periph_id; +#endif int speed; int pinmux_config; struct i2c_control *control; @@ -62,12 +81,41 @@ static void set_packet_mode(struct i2c_bus *i2c_bus) static void i2c_reset_controller(struct i2c_bus *i2c_bus) { /* Reset I2C controller. */ +#ifdef CONFIG_TEGRA186 + reset_assert(&i2c_bus->reset_ctl); + udelay(1); + reset_deassert(&i2c_bus->reset_ctl); + udelay(1); +#else reset_periph(i2c_bus->periph_id, 1); +#endif /* re-program config register to packet mode */ set_packet_mode(i2c_bus); } +#ifdef CONFIG_TEGRA186 +static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate) +{ + int ret; + + ret = reset_assert(&i2c_bus->reset_ctl); + if (ret) + return ret; + ret = clk_enable(&i2c_bus->clk); + if (ret) + return ret; + ret = clk_set_rate(&i2c_bus->clk, rate); + if (IS_ERR_VALUE(ret)) + return ret; + ret = reset_deassert(&i2c_bus->reset_ctl); + if (ret) + return ret; + + return 0; +} +#endif + static void i2c_init_controller(struct i2c_bus *i2c_bus) { if (!i2c_bus->speed) @@ -78,8 +126,12 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * here, in section 23.3.1, but in fact we seem to need a factor of * 16 to get the right frequency. */ +#ifdef CONFIG_TEGRA186 + i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8); +#else clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, i2c_bus->speed * 2 * 8); +#endif if (i2c_bus->type == TYPE_114) { /* @@ -94,12 +146,17 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * is running, we hang, and we need it for the new calc. */ int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; + unsigned rate = CLK_MULT_STD_FAST_MODE * + (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2; debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, clk_div_stdfst_mode); +#ifdef CONFIG_TEGRA186 + i2c_init_clock(i2c_bus, rate); +#else clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, - CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * - i2c_bus->speed * 2); + rate); +#endif } /* Reset I2C controller. */ @@ -112,7 +169,9 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); } +#ifndef CONFIG_TEGRA186 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); +#endif } static void send_packet_headers( @@ -333,8 +392,12 @@ static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) static int tegra_i2c_probe(struct udevice *dev) { struct i2c_bus *i2c_bus = dev_get_priv(dev); +#ifdef CONFIG_TEGRA186 + int ret; +#else const void *blob = gd->fdt_blob; int node = dev->of_offset; +#endif bool is_dvc; i2c_bus->id = dev->seq; @@ -345,6 +408,18 @@ static int tegra_i2c_probe(struct udevice *dev) * We don't have a binding for pinmux yet. Leave it out for now. So * far no one needs anything other than the default. */ +#ifdef CONFIG_TEGRA186 + ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl); + if (ret) { + error("reset_get_by_name() failed: %d\n", ret); + return ret; + } + ret = clk_get_by_name(dev, "i2c", &i2c_bus->clk); + if (ret) { + error("clk_get_by_name() failed: %d\n", ret); + return ret; + } +#else i2c_bus->pinmux_config = FUNCMUX_DEFAULT; i2c_bus->periph_id = clock_decode_periph_id(blob, node); @@ -359,6 +434,7 @@ static int tegra_i2c_probe(struct udevice *dev) */ if (i2c_bus->periph_id == -1) return -EINVAL; +#endif is_dvc = dev_get_driver_data(dev) == TYPE_DVC; if (is_dvc) { @@ -370,7 +446,12 @@ static int tegra_i2c_probe(struct udevice *dev) i2c_init_controller(i2c_bus); debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, - i2c_bus->periph_id, i2c_bus->speed); +#ifndef CONFIG_TEGRA186 + i2c_bus->periph_id, +#else + -1, +#endif + i2c_bus->speed); return 0; } |