diff options
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 4 | ||||
| -rw-r--r-- | drivers/i2c/rcar_i2c.c | 513 | ||||
| -rw-r--r-- | drivers/i2c/sh_sh7734_i2c.c | 376 | ||||
| -rw-r--r-- | drivers/i2c/tsi108_i2c.c | 275 |
5 files changed, 294 insertions, 880 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 7fb201d8e6..5eceab9ea8 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -339,6 +339,12 @@ config SYS_OMAP24_I2C_SPEED OMAP24xx Slave speed channel 0 endif +config SYS_I2C_RCAR_I2C + bool "Renesas RCar I2C driver" + depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C + help + Support for Renesas RCar I2C controller. + config SYS_I2C_RCAR_IIC bool "Renesas RCar Gen3 IIC driver" depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index e8bb6327fb..da368cc02a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -9,8 +9,6 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o obj-$(CONFIG_I2C_MV) += mv_i2c.o -obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o -obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o @@ -28,7 +26,7 @@ obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o -obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index a2627dca5f..8d87c73713 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -1,292 +1,353 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /* * drivers/i2c/rcar_i2c.c * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. + * Clock configuration based on Linux i2c-rcar.c: + * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> + * Copyright (C) 2011-2015 Renesas Electronics Corporation + * Copyright (C) 2012-14 Renesas Solutions Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> */ #include <common.h> +#include <clk.h> +#include <dm.h> #include <i2c.h> #include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct rcar_i2c { - u32 icscr; - u32 icmcr; - u32 icssr; - u32 icmsr; - u32 icsier; - u32 icmier; - u32 icccr; - u32 icsar; - u32 icmar; - u32 icrxdtxd; - u32 icccr2; - u32 icmpr; - u32 ichpr; - u32 iclpr; -}; - -#define MCR_MDBS 0x80 /* non-fifo mode switch */ -#define MCR_FSCL 0x40 /* override SCL pin */ -#define MCR_FSDA 0x20 /* override SDA pin */ -#define MCR_OBPC 0x10 /* override pins */ -#define MCR_MIE 0x08 /* master if enable */ -#define MCR_TSBE 0x04 -#define MCR_FSB 0x02 /* force stop bit */ -#define MCR_ESG 0x01 /* en startbit gen. */ - -#define MSR_MASK 0x7f -#define MSR_MNR 0x40 /* nack received */ -#define MSR_MAL 0x20 /* arbitration lost */ -#define MSR_MST 0x10 /* sent a stop */ -#define MSR_MDE 0x08 -#define MSR_MDT 0x04 -#define MSR_MDR 0x02 -#define MSR_MAT 0x01 /* slave addr xfer done */ - -static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = { - (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE, - (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE, - (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE, - (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE, +#include <wait_bit.h> + +#define RCAR_I2C_ICSCR 0x00 +#define RCAR_I2C_ICMCR 0x04 +#define RCAR_I2C_ICMCR_MDBS BIT(7) +#define RCAR_I2C_ICMCR_FSCL BIT(6) +#define RCAR_I2C_ICMCR_FSDA BIT(5) +#define RCAR_I2C_ICMCR_OBPC BIT(4) +#define RCAR_I2C_ICMCR_MIE BIT(3) +#define RCAR_I2C_ICMCR_TSBE BIT(2) +#define RCAR_I2C_ICMCR_FSB BIT(1) +#define RCAR_I2C_ICMCR_ESG BIT(0) +#define RCAR_I2C_ICSSR 0x08 +#define RCAR_I2C_ICMSR 0x0c +#define RCAR_I2C_ICMSR_MASK 0x7f +#define RCAR_I2C_ICMSR_MNR BIT(6) +#define RCAR_I2C_ICMSR_MAL BIT(5) +#define RCAR_I2C_ICMSR_MST BIT(4) +#define RCAR_I2C_ICMSR_MDE BIT(3) +#define RCAR_I2C_ICMSR_MDT BIT(2) +#define RCAR_I2C_ICMSR_MDR BIT(1) +#define RCAR_I2C_ICMSR_MAT BIT(0) +#define RCAR_I2C_ICSIER 0x10 +#define RCAR_I2C_ICMIER 0x14 +#define RCAR_I2C_ICCCR 0x18 +#define RCAR_I2C_ICCCR_SCGD_OFF 3 +#define RCAR_I2C_ICSAR 0x1c +#define RCAR_I2C_ICMAR 0x20 +#define RCAR_I2C_ICRXD_ICTXD 0x24 + +struct rcar_i2c_priv { + void __iomem *base; + struct clk clk; + u32 intdelay; + u32 icccr; }; -static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr) +static int rcar_i2c_finish(struct udevice *dev) { - /* set slave address */ - writel(chip << 1, &dev->icmar); - /* set register address */ - writel(addr, &dev->icrxdtxd); - /* clear status */ - writel(0, &dev->icmsr); - /* start master send */ - writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); - - while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE)) - != (MSR_MAT | MSR_MDE)) - udelay(10); - - /* clear ESG */ - writel(MCR_MDBS | MCR_MIE, &dev->icmcr); - /* start SCLclk */ - writel(~(MSR_MAT | MSR_MDE), &dev->icmsr); - - while (!(readl(&dev->icmsr) & MSR_MDE)) - udelay(10); + struct rcar_i2c_priv *priv = dev_get_priv(dev); + int ret; + + ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST, + true, 10, true); + + writel(0, priv->base + RCAR_I2C_ICSSR); + writel(0, priv->base + RCAR_I2C_ICMSR); + writel(0, priv->base + RCAR_I2C_ICMCR); + + return ret; } -static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev) +static void rcar_i2c_recover(struct udevice *dev) { - while (!(readl(&dev->icmsr) & MSR_MST)) - udelay(10); + struct rcar_i2c_priv *priv = dev_get_priv(dev); + u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC; + u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA; + int i; - writel(0, &dev->icmcr); + /* Send 9 SCL pulses */ + for (i = 0; i < 9; i++) { + writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR); + udelay(5); + writel(mcra, priv->base + RCAR_I2C_ICMCR); + udelay(5); + } + + /* Send stop condition */ + udelay(5); + writel(mcra, priv->base + RCAR_I2C_ICMCR); + udelay(5); + writel(mcr, priv->base + RCAR_I2C_ICMCR); + udelay(5); + writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR); + udelay(5); + writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR); + udelay(5); } -static int -rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size) +static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read) { - rcar_i2c_raw_rw_common(dev, chip, addr); - - /* set send date */ - writel(*val, &dev->icrxdtxd); - /* start SCLclk */ - writel(~MSR_MDE, &dev->icmsr); + struct rcar_i2c_priv *priv = dev_get_priv(dev); + u32 mask = RCAR_I2C_ICMSR_MAT | + (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE); + u32 val; + int ret; + + writel(0, priv->base + RCAR_I2C_ICMIER); + writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR); + writel(0, priv->base + RCAR_I2C_ICMSR); + writel(priv->icccr, priv->base + RCAR_I2C_ICCCR); + + ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR, + RCAR_I2C_ICMCR_FSDA, false, 2, true); + if (ret) { + rcar_i2c_recover(dev); + val = readl(priv->base + RCAR_I2C_ICMSR); + if (val & RCAR_I2C_ICMCR_FSDA) { + dev_err(dev, "Bus busy, aborting\n"); + return ret; + } + } - while (!(readl(&dev->icmsr) & MSR_MDE)) - udelay(10); + writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR); + writel(0, priv->base + RCAR_I2C_ICMSR); + writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG, + priv->base + RCAR_I2C_ICMCR); - /* set stop condition */ - writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); - /* start SCLclk */ - writel(~MSR_MDE, &dev->icmsr); + ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask, + true, 100, true); + if (ret) + return ret; - rcar_i2c_raw_rw_finish(dev); + /* Check NAK */ + if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR) + return -EREMOTEIO; return 0; } -static u8 -rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) +static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg) { - u8 ret; + struct rcar_i2c_priv *priv = dev_get_priv(dev); + u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE; + int i, ret = -EREMOTEIO; - rcar_i2c_raw_rw_common(dev, chip, addr); + ret = rcar_i2c_set_addr(dev, msg->addr, 1); + if (ret) + return ret; - /* set slave address, receive */ - writel((chip << 1) | 1, &dev->icmar); - /* start master receive */ - writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); - /* clear status */ - writel(0, &dev->icmsr); + for (i = 0; i < msg->len; i++) { + if (msg->len - 1 == i) + icmcr |= RCAR_I2C_ICMCR_FSB; - while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) - != (MSR_MAT | MSR_MDR)) - udelay(10); + writel(icmcr, priv->base + RCAR_I2C_ICMCR); + writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR); - /* clear ESG */ - writel(MCR_MDBS | MCR_MIE, &dev->icmcr); - /* prepare stop condition */ - writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); - /* start SCLclk */ - writel(~(MSR_MAT | MSR_MDR), &dev->icmsr); + ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, + RCAR_I2C_ICMSR_MDR, true, 100, true); + if (ret) + return ret; - while (!(readl(&dev->icmsr) & MSR_MDR)) - udelay(10); - - /* get receive data */ - ret = (u8)readl(&dev->icrxdtxd); - /* start SCLclk */ - writel(~MSR_MDR, &dev->icmsr); + msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff; + } - rcar_i2c_raw_rw_finish(dev); + writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR); - return ret; + return rcar_i2c_finish(dev); } -/* - * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck]) - * iicck : I2C internal clock < 20 MHz - * ticf : I2C SCL falling time: 35 ns - * tr : I2C SCL rising time: 200 ns - * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5 - * F[n] : n rounded up to an integer - */ -static u32 rcar_clock_gen(int i2c_no, u32 bus_speed) +static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg) { - u32 iicck, f, scl, scgd; - u32 intd = 5; - - int bit = 0, cdf_width = 3; - for (bit = 0; bit < (1 << cdf_width); bit++) { - iicck = CONFIG_HP_CLK_FREQ / (1 + bit); - if (iicck < 20000000) - break; + struct rcar_i2c_priv *priv = dev_get_priv(dev); + u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE; + int i, ret = -EREMOTEIO; + + ret = rcar_i2c_set_addr(dev, msg->addr, 0); + if (ret) + return ret; + + for (i = 0; i < msg->len; i++) { + writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD); + writel(icmcr, priv->base + RCAR_I2C_ICMCR); + writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR); + + ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, + RCAR_I2C_ICMSR_MDE, true, 100, true); + if (ret) + return ret; } - if (bit > (1 << cdf_width)) { - puts("rcar-i2c: Can not get CDF\n"); - return 0; - } + writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR); + icmcr |= RCAR_I2C_ICMCR_FSB; + writel(icmcr, priv->base + RCAR_I2C_ICMCR); - if (i2c_no == 0) - intd = 50; + return rcar_i2c_finish(dev); +} - f = (35 + 200 + intd) * (iicck / 1000000000); +static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + int ret; - for (scgd = 0; scgd < 0x40; scgd++) { - scl = iicck / (20 + (scgd * 8) + f); - if (scl <= bus_speed) - break; - } + for (; nmsgs > 0; nmsgs--, msg++) { + if (msg->flags & I2C_M_RD) + ret = rcar_i2c_read_common(dev, msg); + else + ret = rcar_i2c_write_common(dev, msg); - if (scgd > 0x40) { - puts("rcar-i2c: Can not get SDGB\n"); - return 0; + if (ret) + return -EREMOTEIO; } - debug("%s: scl: %d\n", __func__, scl); - debug("%s: bit %x\n", __func__, bit); - debug("%s: scgd %x\n", __func__, scgd); - debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit)); + return ret; +} + +static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags) +{ + struct rcar_i2c_priv *priv = dev_get_priv(dev); + int ret; - return scgd << (cdf_width) | bit; + /* Ignore address 0, slave address */ + if (addr == 0) + return -EINVAL; + + ret = rcar_i2c_set_addr(dev, addr, 1); + writel(0, priv->base + RCAR_I2C_ICMSR); + return ret; } -static void -rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz) { - struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; - u32 icccr = 0; + struct rcar_i2c_priv *priv = dev_get_priv(dev); + u32 scgd, cdf, round, ick, sum, scl; + unsigned long rate; - /* No i2c support prior to relocation */ - if (!(gd->flags & GD_FLG_RELOC)) - return; + /* + * calculate SCL clock + * see + * ICCCR + * + * ick = clkp / (1 + CDF) + * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) + * + * ick : I2C internal clock < 20 MHz + * ticf : I2C SCL falling time + * tr : I2C SCL rising time + * intd : LSI internal delay + * clkp : peripheral_clk + * F[] : integer up-valuation + */ + rate = clk_get_rate(&priv->clk); + cdf = rate / 20000000; + if (cdf >= 8) { + dev_err(dev, "Input clock %lu too high\n", rate); + return -EIO; + } + ick = rate / (cdf + 1); /* - * reset slave mode. - * slave mode is not used on this driver + * it is impossible to calculate large scale + * number on u32. separate it + * + * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) + * = F[sum * ick / 1000000000] + * = F[(ick / 1000000) * sum / 1000] */ - writel(0, &dev->icsier); - writel(0, &dev->icsar); - writel(0, &dev->icscr); - writel(0, &dev->icssr); + sum = 35 + 200 + priv->intdelay; + round = (ick + 500000) / 1000000 * sum; + round = (round + 500) / 1000; - /* reset master mode */ - writel(0, &dev->icmier); - writel(0, &dev->icmcr); - writel(0, &dev->icmsr); - writel(0, &dev->icmar); - - icccr = rcar_clock_gen(adap->hwadapnr, adap->speed); - if (icccr == 0) - puts("I2C: Init failed\n"); - else - writel(icccr, &dev->icccr); -} + /* + * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) + * + * Calculation result (= SCL) should be less than + * bus_speed for hardware safety + * + * We could use something along the lines of + * div = ick / (bus_speed + 1) + 1; + * scgd = (div - 20 - round + 7) / 8; + * scl = ick / (20 + (scgd * 8) + round); + * (not fully verified) but that would get pretty involved + */ + for (scgd = 0; scgd < 0x40; scgd++) { + scl = ick / (20 + (scgd * 8) + round); + if (scl <= bus_freq_hz) + goto scgd_find; + } + dev_err(dev, "it is impossible to calculate best SCL\n"); + return -EIO; -static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip, - uint addr, int alen, u8 *data, int len) -{ - struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; - int i; +scgd_find: + dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", + scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd); - for (i = 0; i < len; i++) - data[i] = rcar_i2c_raw_read(dev, chip, addr + i); + priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf; + writel(priv->icccr, priv->base + RCAR_I2C_ICCCR); return 0; } -static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, - int alen, u8 *data, int len) +static int rcar_i2c_probe(struct udevice *dev) { - struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; - return rcar_i2c_raw_write(dev, chip, addr, data, len); -} + struct rcar_i2c_priv *priv = dev_get_priv(dev); + int ret; -static int -rcar_i2c_probe(struct i2c_adapter *adap, u8 dev) -{ - return rcar_i2c_read(adap, dev, 0, 0, NULL, 0); -} + priv->base = dev_read_addr_ptr(dev); + priv->intdelay = dev_read_u32_default(dev, + "i2c-scl-internal-delay-ns", 5); + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + /* reset slave mode */ + writel(0, priv->base + RCAR_I2C_ICSIER); + writel(0, priv->base + RCAR_I2C_ICSAR); + writel(0, priv->base + RCAR_I2C_ICSCR); + writel(0, priv->base + RCAR_I2C_ICSSR); + + /* reset master mode */ + writel(0, priv->base + RCAR_I2C_ICMIER); + writel(0, priv->base + RCAR_I2C_ICMCR); + writel(0, priv->base + RCAR_I2C_ICMSR); + writel(0, priv->base + RCAR_I2C_ICMAR); + + ret = rcar_i2c_set_speed(dev, 100000); + if (ret) + clk_disable(&priv->clk); -static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; - u32 icccr; - int ret = 0; - - rcar_i2c_raw_rw_finish(dev); - - icccr = rcar_clock_gen(adap->hwadapnr, speed); - if (icccr == 0) { - puts("I2C: Init failed\n"); - ret = -1; - } else { - writel(icccr, &dev->icccr); - } return ret; } -/* - * Register RCAR i2c adapters - */ -U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, - rcar_i2c_write, rcar_i2c_set_bus_speed, - CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0) -U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, - rcar_i2c_write, rcar_i2c_set_bus_speed, - CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1) -U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, - rcar_i2c_write, rcar_i2c_set_bus_speed, - CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2) -U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, - rcar_i2c_write, rcar_i2c_set_bus_speed, - CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3) +static const struct dm_i2c_ops rcar_i2c_ops = { + .xfer = rcar_i2c_xfer, + .probe_chip = rcar_i2c_probe_chip, + .set_bus_speed = rcar_i2c_set_speed, +}; + +static const struct udevice_id rcar_i2c_ids[] = { + { .compatible = "renesas,rcar-gen2-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_rcar) = { + .name = "i2c_rcar", + .id = UCLASS_I2C, + .of_match = rcar_i2c_ids, + .probe = rcar_i2c_probe, + .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv), + .ops = &rcar_i2c_ops, +}; diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c deleted file mode 100644 index 6fe356baca..0000000000 --- a/drivers/i2c/sh_sh7734_i2c.c +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2012 Renesas Solutions Corp. - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include <common.h> -#include <i2c.h> -#include <asm/io.h> - -struct sh_i2c { - u8 iccr1; - u8 iccr2; - u8 icmr; - u8 icier; - u8 icsr; - u8 sar; - u8 icdrt; - u8 icdrr; - u8 nf2cyc; - u8 __pad0; - u8 __pad1; -}; - -static struct sh_i2c *base; -static u8 iccr1_cks, nf2cyc; - -/* ICCR1 */ -#define SH_I2C_ICCR1_ICE (1 << 7) -#define SH_I2C_ICCR1_RCVD (1 << 6) -#define SH_I2C_ICCR1_MST (1 << 5) -#define SH_I2C_ICCR1_TRS (1 << 4) -#define SH_I2C_ICCR1_MTRS \ - (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS) - -/* ICCR1 */ -#define SH_I2C_ICCR2_BBSY (1 << 7) -#define SH_I2C_ICCR2_SCP (1 << 6) -#define SH_I2C_ICCR2_SDAO (1 << 5) -#define SH_I2C_ICCR2_SDAOP (1 << 4) -#define SH_I2C_ICCR2_SCLO (1 << 3) -#define SH_I2C_ICCR2_IICRST (1 << 1) - -#define SH_I2C_ICIER_TIE (1 << 7) -#define SH_I2C_ICIER_TEIE (1 << 6) -#define SH_I2C_ICIER_RIE (1 << 5) -#define SH_I2C_ICIER_NAKIE (1 << 4) -#define SH_I2C_ICIER_STIE (1 << 3) -#define SH_I2C_ICIER_ACKE (1 << 2) -#define SH_I2C_ICIER_ACKBR (1 << 1) -#define SH_I2C_ICIER_ACKBT (1 << 0) - -#define SH_I2C_ICSR_TDRE (1 << 7) -#define SH_I2C_ICSR_TEND (1 << 6) -#define SH_I2C_ICSR_RDRF (1 << 5) -#define SH_I2C_ICSR_NACKF (1 << 4) -#define SH_I2C_ICSR_STOP (1 << 3) -#define SH_I2C_ICSR_ALOVE (1 << 2) -#define SH_I2C_ICSR_AAS (1 << 1) -#define SH_I2C_ICSR_ADZ (1 << 0) - -#define IRQ_WAIT 1000 - -static void sh_i2c_send_stop(struct sh_i2c *base) -{ - clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP); -} - -static int check_icsr_bits(struct sh_i2c *base, u8 bits) -{ - int i; - - for (i = 0; i < IRQ_WAIT; i++) { - if (bits & readb(&base->icsr)) - return 0; - udelay(10); - } - - return 1; -} - -static int check_stop(struct sh_i2c *base) -{ - int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP); - clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); - - return ret; -} - -static int check_tend(struct sh_i2c *base, int stop) -{ - int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND); - - if (stop) { - clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); - sh_i2c_send_stop(base); - } - - clrbits_8(&base->icsr, SH_I2C_ICSR_TEND); - return ret; -} - -static int check_tdre(struct sh_i2c *base) -{ - return check_icsr_bits(base, SH_I2C_ICSR_TDRE); -} - -static int check_rdrf(struct sh_i2c *base) -{ - return check_icsr_bits(base, SH_I2C_ICSR_RDRF); -} - -static int check_bbsy(struct sh_i2c *base) -{ - int i; - - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2))) - return 0; - udelay(10); - } - return 1; -} - -static int check_ackbr(struct sh_i2c *base) -{ - int i; - - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier))) - return 0; - udelay(10); - } - - return 1; -} - -static void sh_i2c_reset(struct sh_i2c *base) -{ - setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); - - udelay(100); - - clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); -} - -static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg) -{ - if (check_bbsy(base)) { - puts("i2c bus busy\n"); - goto fail; - } - - setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); - clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); - - writeb((id << 1), &base->icdrt); - - if (check_tend(base, 0)) { - puts("TEND check fail...\n"); - goto fail; - } - - if (check_ackbr(base)) { - check_tend(base, 0); - sh_i2c_send_stop(base); - goto fail; - } - - writeb(reg, &base->icdrt); - - if (check_tdre(base)) { - puts("TDRE check fail...\n"); - goto fail; - } - - if (check_tend(base, 0)) { - puts("TEND check fail...\n"); - goto fail; - } - - return 0; -fail: - - return 1; -} - -static int -i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size) -{ - int i; - - if (i2c_set_addr(base, id, reg)) { - puts("Fail set slave address\n"); - return 1; - } - - for (i = 0; i < size; i++) { - writeb(val[i], &base->icdrt); - check_tdre(base); - } - - check_tend(base, 1); - check_stop(base); - - udelay(100); - - clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); - clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); - sh_i2c_reset(base); - - return 0; -} - -static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) -{ - u8 ret = 0; - - if (i2c_set_addr(base, id, reg)) { - puts("Fail set slave address\n"); - goto fail; - } - - clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); - writeb((id << 1) | 1, &base->icdrt); - - if (check_tend(base, 0)) - puts("TDRE check fail...\n"); - - clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST); - clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); - setbits_8(&base->icier, SH_I2C_ICIER_ACKBT); - setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); - - /* read data (dummy) */ - ret = readb(&base->icdrr); - - if (check_rdrf(base)) { - puts("check RDRF error\n"); - goto fail; - } - - clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); - udelay(1000); - - sh_i2c_send_stop(base); - - if (check_stop(base)) { - puts("check STOP error\n"); - goto fail; - } - - clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); - clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); - - /* data read */ - ret = readb(&base->icdrr); - -fail: - clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); - - return ret; -} - -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned int current_bus; - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - switch (bus) { - case 0: - base = (void *)CONFIG_SH_I2C_BASE0; - break; - case 1: - base = (void *)CONFIG_SH_I2C_BASE1; - break; - default: - printf("Bad bus: %d\n", bus); - return -1; - } - - current_bus = bus; - - return 0; -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - return current_bus; -} -#endif - -void i2c_init(int speed, int slaveaddr) -{ -#ifdef CONFIG_I2C_MULTI_BUS - current_bus = 0; -#endif - base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; - - if (speed == 400000) - iccr1_cks = 0x07; - else - iccr1_cks = 0x0F; - - nf2cyc = 1; - - /* Reset */ - sh_i2c_reset(base); - - /* ICE enable and set clock */ - writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1); - writeb(nf2cyc, &base->nf2cyc); -} - -/* - * i2c_read: - Read multiple bytes from an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be read - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to write the data - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) -{ - int i = 0; - for (i = 0; i < len; i++) - buffer[i] = i2c_raw_read(base, chip, addr + i); - - return 0; -} - -/* - * i2c_write: - Write multiple bytes to an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be written - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to find the data to be written - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) -{ - return i2c_raw_write(base, chip, addr, buffer, len); -} - -/* - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ -int i2c_probe(u8 chip) -{ - u8 byte; - return i2c_read(chip, 0, 0, &byte, 1); -} diff --git a/drivers/i2c/tsi108_i2c.c b/drivers/i2c/tsi108_i2c.c deleted file mode 100644 index 208c0900ef..0000000000 --- a/drivers/i2c/tsi108_i2c.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 Tundra Semiconductor Corp. - * Author: Alex Bounine - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include <config.h> -#include <common.h> - -#include <tsi108.h> - -#if defined(CONFIG_CMD_I2C) - -#define I2C_DELAY 100000 -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DPRINT(x) printf (x) -#else -#define DPRINT(x) -#endif - -/* All functions assume that Tsi108 I2C block is the only master on the bus */ -/* I2C read helper function */ - -void i2c_init(int speed, int slaveaddr) -{ - /* - * The TSI108 has a fixed I2C clock rate and doesn't support slave - * operation. This function only exists as a stub to fit into the - * U-Boot I2C API. - */ -} - -static int i2c_read_byte ( - uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ - uchar chip_addr,/* I2C device address on the bus */ - uint byte_addr, /* Byte address within I2C device */ - uchar * buffer /* pointer to data buffer */ - ) -{ - u32 temp; - u32 to_count = I2C_DELAY; - u32 op_status = TSI108_I2C_TIMEOUT_ERR; - u32 chan_offset = TSI108_I2C_OFFSET; - - DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", - i2c_chan, chip_addr, byte_addr)); - - if (0 != i2c_chan) - chan_offset = TSI108_I2C_SDRAM_OFFSET; - - /* Check if I2C operation is in progress */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | - I2C_CNTRL2_START))) { - /* Set device address and operation (read = 0) */ - temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | - ((chip_addr >> 3) & 0x0F); - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = - temp; - - /* Issue the read command - * (at this moment all other parameters are 0 - * (size = 1 byte, lane = 0) - */ - - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = - (I2C_CNTRL2_START); - - /* Wait until operation completed */ - do { - /* Read I2C operation status */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) { - if (0 == (temp & - (I2C_CNTRL2_I2C_CFGERR | - I2C_CNTRL2_I2C_TO_ERR)) - ) { - op_status = TSI108_I2C_SUCCESS; - - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + - chan_offset + - I2C_RD_DATA); - - *buffer = (u8) (temp & 0xFF); - } else { - /* report HW error */ - op_status = TSI108_I2C_IF_ERROR; - - DPRINT (("I2C HW error reported: 0x%02x\n", temp)); - } - - break; - } - } while (to_count--); - } else { - op_status = TSI108_I2C_IF_BUSY; - - DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); - } - - DPRINT (("I2C read_byte() status: 0x%02x\n", op_status)); - return op_status; -} - -/* - * I2C Read interface as defined in "include/i2c.h" : - * chip_addr: I2C chip address, range 0..127 - * (to read from SPD channel EEPROM use (0xD0 ... 0xD7) - * NOTE: The bit 7 in the chip_addr serves as a channel select. - * This hack is for enabling "i2c sdram" command on Tsi108 boards - * without changes to common code. Used for I2C reads only. - * byte_addr: Memory or register address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Pointer to destination buffer for data to be read - * len: How many bytes to read - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_read (uchar chip_addr, uint byte_addr, int alen, - uchar * buffer, int len) -{ - u32 op_status = TSI108_I2C_PARAM_ERR; - u32 i2c_if = 0; - - /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/ - if (0xD0 == (chip_addr & ~0x07)) { - i2c_if = 1; - chip_addr &= 0x7F; - } - /* Check for valid I2C address */ - if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { - while (len--) { - op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++); - - if (TSI108_I2C_SUCCESS != op_status) { - DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); - - break; - } - } - } - - DPRINT (("I2C read() status: 0x%02x\n", op_status)); - return op_status; -} - -/* I2C write helper function */ - -static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ - uint byte_addr, /* Byte address within I2C device */ - uchar * buffer /* pointer to data buffer */ - ) -{ - u32 temp; - u32 to_count = I2C_DELAY; - u32 op_status = TSI108_I2C_TIMEOUT_ERR; - - /* Check if I2C operation is in progress */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { - /* Place data into the I2C Tx Register */ - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + - I2C_TX_DATA) = (u32) * buffer; - - /* Set device address and operation */ - temp = - I2C_CNTRL1_I2CWRITE | (byte_addr << 16) | - ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + - I2C_CNTRL1) = temp; - - /* Issue the write command (at this moment all other parameters - * are 0 (size = 1 byte, lane = 0) - */ - - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + - I2C_CNTRL2) = (I2C_CNTRL2_START); - - op_status = TSI108_I2C_TIMEOUT_ERR; - - /* Wait until operation completed */ - do { - /* Read I2C operation status */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { - if (0 == (temp & - (I2C_CNTRL2_I2C_CFGERR | - I2C_CNTRL2_I2C_TO_ERR))) { - op_status = TSI108_I2C_SUCCESS; - } else { - /* report detected HW error */ - op_status = TSI108_I2C_IF_ERROR; - - DPRINT (("I2C HW error reported: 0x%02x\n", temp)); - } - - break; - } - - } while (to_count--); - } else { - op_status = TSI108_I2C_IF_BUSY; - - DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); - } - - return op_status; -} - -/* - * I2C Write interface as defined in "include/i2c.h" : - * chip_addr: I2C chip address, range 0..127 - * byte_addr: Memory or register address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Pointer to data to be written - * len: How many bytes to write - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, - int len) -{ - u32 op_status = TSI108_I2C_PARAM_ERR; - - /* Check for valid I2C address */ - if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { - while (len--) { - op_status = - i2c_write_byte (chip_addr, byte_addr++, buffer++); - - if (TSI108_I2C_SUCCESS != op_status) { - DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); - - break; - } - } - } - - return op_status; -} - -/* - * I2C interface function as defined in "include/i2c.h". - * Probe the given I2C chip address by reading single byte from offset 0. - * Returns 0 if a chip responded, not 0 on failure. - */ - -int i2c_probe (uchar chip) -{ - u32 tmp; - - /* - * Try to read the first location of the chip. - * The Tsi108 HW doesn't support sending just the chip address - * and checkong for an <ACK> back. - */ - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -#endif |