5 files changed, 33 insertions, 11 deletions
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 4a8f8dea1c..8ef5fa4c48 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -671,7 +671,7 @@ static int of_sdram_firewall_setup(const void *blob)
 
 int ddr_calibration_sequence(void)
 {
-	WATCHDOG_RESET();
+	schedule();
 
 	/* Check to see if SDRAM cal was success */
 	if (sdram_startup()) {
@@ -681,7 +681,7 @@ int ddr_calibration_sequence(void)
 
 	puts("DDRCAL: Success\n");
 
-	WATCHDOG_RESET();
+	schedule();
 
 	/* initialize the MMR register */
 	sdram_mmr_init();
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
index 737a4e2ff1..d9039443b9 100644
--- a/drivers/ddr/altera/sdram_n5x.c
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -517,7 +517,7 @@ static int ensure_retry_procedure_complete(phys_addr_t umctl2_base)
 			      DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW;
 
 		udelay(1);
-		WATCHDOG_RESET();
+		schedule();
 	}
 
 	return 0;
@@ -1349,7 +1349,7 @@ static int ddr_post_handoff_config(phys_addr_t umctl2_base,
 		}
 
 		udelay(1);
-		WATCHDOG_RESET();
+		schedule();
 
 		/* Polling until SDRAM entered normal operating mode */
 		value = readl(umctl2_base + DDR4_STAT_OFFSET) &
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 9b1710c135..4716abfc9a 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -161,7 +161,7 @@ void sdram_init_ecc_bits(struct bd_info *bd)
 			sdram_clear_mem(start_addr, size_init);
 			size -= size_init;
 			start_addr += size_init;
-			WATCHDOG_RESET();
+			schedule();
 		}
 
 		bank++;
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index d738ae3a7c..5e4ad56f07 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -422,6 +422,9 @@ compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
 					dimm_params[i].mpart);
 #endif
 			}
+#ifndef CONFIG_SPL_BUILD
+			puts("       ");
+#endif
 		}
 	}
 
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 1903562ac4..ed3313a531 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -857,17 +857,32 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 	debug("total_memory by %s = %llu\n", __func__, total_memory);
 
 #if !defined(CONFIG_PHYS_64BIT)
-	/* Check for 4G or more.  Bad. */
-	if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
+	/*
+	 * Show warning about big DDR moodules. But avoid warning for 4 GB DDR
+	 * modules when U-Boot supports RAM of maximal size 4 GB - 1 byte.
+	 */
+	if ((first_ctrl == 0) && (total_memory - 1 > (phys_size_t)~0ULL)) {
 		puts("Detected ");
 		print_size(total_memory, " of memory\n");
-		printf("       This U-Boot only supports < 4G of DDR\n");
-		printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
-		printf("       "); /* re-align to match init_dram print */
-		total_memory = CONFIG_MAX_MEM_MAPPED;
+#ifndef CONFIG_SPL_BUILD
+		puts("       "); /* re-align to match init_dram print */
+#endif
+		puts("This U-Boot only supports <= ");
+		print_size((unsigned long long)((phys_size_t)~0ULL)+1, " of DDR\n");
+#ifndef CONFIG_SPL_BUILD
+		puts("       "); /* re-align to match init_dram print */
+#endif
+		puts("You could rebuild it with CONFIG_PHYS_64BIT\n");
+#ifndef CONFIG_SPL_BUILD
+		puts("       "); /* re-align to match init_dram print */
+#endif
 	}
 #endif
 
+	/* Ensure that total_memory does not overflow on return */
+	if (total_memory > (phys_size_t)~0ULL)
+		total_memory = (phys_size_t)~0ULL;
+
 	return total_memory;
 }
 
@@ -941,5 +956,9 @@ fsl_ddr_sdram_size(void)
 	/* Compute it once normally. */
 	total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 
+	/* Ensure that total_memory does not overflow on return */
+	if (total_memory > (phys_size_t)~0ULL)
+		total_memory = (phys_size_t)~0ULL;
+
 	return total_memory;
 }