diff options
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/Kconfig | 5 | ||||
| -rw-r--r-- | drivers/ddr/fsl/Kconfig | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index eec9d480b0..738b788401 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -30,5 +30,10 @@ config DDR_SPD For memory controllers that can utilize it, add enable support for using the JEDEC SDP standard. +config SYS_SPD_BUS_NUM + int "I2C bus number for DDR SPD" + depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY + default 0 + source "drivers/ddr/altera/Kconfig" source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index fe69bef3d3..d93ed8d2fe 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -10,6 +10,12 @@ config SYS_FSL_MMDC help Select Freescale Multi Mode DDR controller (MMDC). +config SYS_FSL_DDR_EMU + bool + help + Specify emulator support for DDR. Some DDR features such as deskew + training are not available. + if SYS_FSL_DDR || SYS_FSL_MMDC config SYS_FSL_DDR_BE @@ -169,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER Use the DDR controller to auto initialize memory. If not enabled, the DMA controller is responsible for doing this. +config SYS_DDR_RAW_TIMING + bool "Get DDR timing information from something other than SPD" + help + This is common with soldered DDR chips onboard without SPD. DDR raw + timing parameters are extracted from datasheet and hard-coded into + header files or board specific files. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" |