4 files changed, 59 insertions, 6 deletions

diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
index d4b393d25e..eec9d480b0 100644
--- a/drivers/ddr/Kconfig
+++ b/drivers/ddr/Kconfig
@@ -1,2 +1,34 @@
+choice
+	prompt "Method to determine DDR clock frequency"
+	default STATIC_DDR_CLK_FREQ
+	depends on ARCH_P1010 || ARCH_P1020 || ARCH_P2020 || ARCH_T1024 \
+		|| ARCH_T1042 || ARCH_T2080 || ARCH_T4240 || ARCH_LS1021A \
+		|| FSL_LSCH2 || FSL_LSCH3 || TARGET_KMCENT2
+	help
+	  The DDR clock frequency can either be defined statically now at
+	  build time, or can be determined at run-time via the
+	  get_board_ddr_clk function.
+
+config DYNAMIC_DDR_CLK_FREQ
+	bool "Run-time DDR clock frequency"
+
+config STATIC_DDR_CLK_FREQ
+	bool "Build-time static DDR clock frequency"
+
+endchoice
+
+config DDR_CLK_FREQ
+	int "DDR clock frequency in Hz"
+	depends on STATIC_DDR_CLK_FREQ
+	default 100000000
+	help
+	  The DDR clock frequency, specified in Hz.
+
+config DDR_SPD
+	bool "JEDEC Serial Presence Detect (SPD) support"
+	help
+	  For memory controllers that can utilize it, add enable support for
+	  using the JEDEC SDP standard.
+
 source "drivers/ddr/altera/Kconfig"
 source "drivers/ddr/imx/Kconfig"
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 8246f62798..fe3d6fc970 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -10,6 +10,8 @@ config SYS_FSL_MMDC
 	help
 	  Select Freescale Multi Mode DDR controller (MMDC).
 
+if SYS_FSL_DDR || SYS_FSL_MMDC
+
 config SYS_FSL_DDR_BE
 	bool
 	help
@@ -116,28 +118,51 @@ choice
 config SYS_FSL_DDR4
 	bool "Freescale DDR4 controller"
 	depends on SYS_FSL_HAS_DDR4
+	imply DDR_SPD
 	select SYS_FSL_DDRC_GEN4
 
 config SYS_FSL_DDR3
 	bool "Freescale DDR3 controller"
 	depends on SYS_FSL_HAS_DDR3
+	imply DDR_SPD
 	select SYS_FSL_DDRC_GEN3 if PPC
 	select SYS_FSL_DDRC_ARM_GEN3 if ARM
 
 config SYS_FSL_DDR2
 	bool "Freescale DDR2 controller"
 	depends on SYS_FSL_HAS_DDR2
+	imply DDR_SPD
 	select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
 
 config SYS_FSL_DDR1
 	bool "Freescale DDR1 controller"
 	depends on SYS_FSL_HAS_DDR1
+	imply DDR_SPD
 	select SYS_FSL_DDRC_GEN1
 
 endchoice
 
 endmenu
 
+config FSL_DMA
+	def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
+
+config DDR_ECC
+	bool "ECC DDR memory support"
+
+config DDR_ECC_CMD
+	bool "Access the ECC features of the memory controller"
+	depends on DDR_ECC && MPC83xx
+	default y
+
+config ECC_INIT_VIA_DDRCONTROLLER
+	bool "DDR Memory controller initializes memory."
+	help
+	  Use the DDR controller to auto initialize memory.  If not enabled,
+	  the DMA controller is responsible for doing this.
+
+endif
+
 config SYS_FSL_ERRATUM_A008378
 	bool
 
diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
index 270691e9bc..970651f870 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp.h
@@ -19,10 +19,10 @@
 #define FAR_END_DIMM_ADDR		0x50
 #define MAX_DIMM_ADDR			0x60
 
-#ifndef CONFIG_DDR_FIXED_SIZE
+#ifndef CONFIG_SYS_SDRAM_SIZE
 #define SDRAM_CS_SIZE			0xFFFFFFF
 #else
-#define SDRAM_CS_SIZE			(CONFIG_DDR_FIXED_SIZE - 1)
+#define SDRAM_CS_SIZE			((CONFIG_SYS_SDRAM_SIZE >> 10) - 1)
 #endif
 #define SDRAM_CS_BASE			0x0
 #define SDRAM_DIMM_SIZE			0x80000000
diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h
index 10d064d0a3..437a02efba 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp_config.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h
@@ -16,11 +16,7 @@
  * Level 3: Provides the windows margin of each DQ as a results of DQS
  *          centeralization
  */
-#ifdef CONFIG_DDR_LOG_LEVEL
 #define	DDR3_LOG_LEVEL	CONFIG_DDR_LOG_LEVEL
-#else
-#define	DDR3_LOG_LEVEL	0
-#endif
 
 #define DDR3_PBS        1