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-rw-r--r--drivers/clk/renesas/Kconfig18
-rw-r--r--drivers/clk/renesas/Makefile2
-rw-r--r--drivers/clk/renesas/clk-rcar-gen3.c109
-rw-r--r--drivers/clk/renesas/r8a779a0-cpg-mssr.c20
-rw-r--r--drivers/clk/renesas/r8a779f0-cpg-mssr.c250
-rw-r--r--drivers/clk/renesas/r8a779g0-cpg-mssr.c312
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h28
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h28
9 files changed, 714 insertions, 55 deletions
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d58e897ca1..45671c6925 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -45,13 +45,13 @@ config CLK_R8A7794
Enable this to support the clocks on Renesas R8A7794 SoC.
config CLK_RCAR_GEN3
- bool "Renesas RCar Gen3 clock driver"
- def_bool y if RCAR_GEN3
+ bool "Renesas RCar Gen3 and Gen4 clock driver"
+ def_bool y if RCAR_64
depends on CLK_RENESAS
select CLK_RCAR_CPG_LIB
select DM_RESET
help
- Enable this to support the clocks on Renesas RCar Gen3 SoC.
+ Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs.
config CLK_R8A774A1
bool "Renesas R8A774A1 clock driver"
@@ -131,3 +131,15 @@ config CLK_R8A779A0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779A0 SoC.
+
+config CLK_R8A779F0
+ bool "Renesas R8A779F0 clock driver"
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A779F0 SoC.
+
+config CLK_R8A779G0
+ bool "Renesas R8A779G0 clock driver"
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A779G0 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 8f82a7aa3e..fe0391e520 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -20,3 +20,5 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 1697867ff0..c8a5512b65 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -35,10 +35,16 @@
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
-static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+#define SD0CKCR1 0x08a4
+
+static const struct clk_div_table gen3_cpg_rpcsrc_div_table[] = {
{ 2, 5 }, { 3, 6 }, { 0, 0 },
};
+static const struct clk_div_table gen4_cpg_rpcsrc_div_table[] = {
+ { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
+};
+
static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
@@ -181,8 +187,10 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
struct cpg_mssr_info *info = priv->info;
struct clk parent;
const struct cpg_core_clk *core;
- const struct rcar_gen3_cpg_pll_config *pll_config =
- priv->cpg_pll_config;
+ const struct rcar_gen3_cpg_pll_config *gen3_pll_config =
+ priv->gen3_cpg_pll_config;
+ const struct rcar_gen4_cpg_pll_config *gen4_pll_config =
+ priv->gen4_cpg_pll_config;
u32 value, div;
u64 rate = 0;
u8 shift;
@@ -227,7 +235,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_MAIN:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
- 0, 1, pll_config->extal_div,
+ 0, 1, gen3_pll_config->extal_div,
"MAIN");
case CLK_TYPE_GEN3_PLL0:
@@ -236,8 +244,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL1:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
- 0, pll_config->pll1_mult,
- pll_config->pll1_div, "PLL1");
+ 0, gen3_pll_config->pll1_mult,
+ gen3_pll_config->pll1_div,
+ "PLL1");
case CLK_TYPE_GEN3_PLL2:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@@ -245,8 +254,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL3:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
- 0, pll_config->pll3_mult,
- pll_config->pll3_div, "PLL3");
+ 0, gen3_pll_config->pll3_mult,
+ gen3_pll_config->pll3_div,
+ "PLL3");
case CLK_TYPE_GEN3_PLL4:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@@ -254,25 +264,48 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN4_MAIN:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
- 0, 1, pll_config->extal_div,
- "V3U_MAIN");
+ 0, 1, gen4_pll_config->extal_div,
+ "MAIN");
case CLK_TYPE_GEN4_PLL1:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
- 0, pll_config->pll1_mult,
- pll_config->pll1_div,
- "V3U_PLL1");
+ 0, gen4_pll_config->pll1_mult,
+ gen4_pll_config->pll1_div,
+ "PLL1");
+
+ case CLK_TYPE_GEN4_PLL2:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+ 0, gen4_pll_config->pll2_mult,
+ gen4_pll_config->pll2_div,
+ "PLL2");
case CLK_TYPE_GEN4_PLL2X_3X:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
- core->offset, 0, 0,
- "V3U_PLL2X_3X");
+ core->offset, 0, 0, "PLL2X_3X");
+
+ case CLK_TYPE_GEN4_PLL3:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+ 0, gen4_pll_config->pll3_mult,
+ gen4_pll_config->pll3_div,
+ "PLL3");
+
+ case CLK_TYPE_GEN4_PLL4:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+ 0, gen4_pll_config->pll4_mult,
+ gen4_pll_config->pll4_div,
+ "PLL4");
case CLK_TYPE_GEN4_PLL5:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
- 0, pll_config->pll5_mult,
- pll_config->pll5_div,
- "V3U_PLL5");
+ 0, gen4_pll_config->pll5_mult,
+ gen4_pll_config->pll5_div,
+ "PLL5");
+
+ case CLK_TYPE_GEN4_PLL6:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+ 0, gen4_pll_config->pll6_mult,
+ gen4_pll_config->pll6_div,
+ "PLL6");
case CLK_TYPE_FF:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@@ -288,6 +321,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
div, rate);
return rate;
+ case CLK_TYPE_GEN4_SDSRC:
+ div = ((readl(priv->base + SD0CKCR1) >> 29) & 0x03) + 4;
+ rate = gen3_clk_get_rate64(&parent) / div;
+ debug("%s[%i] SDSRC clk: parent=%i div=%u => rate=%llu\n",
+ __func__, __LINE__, core->parent, div, rate);
+ return rate;
+
case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
fallthrough;
case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
@@ -321,7 +361,16 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
gen3_clk_get_rate64(&parent),
priv->base + CPG_RPCCKCR,
CPG_RPCCKCR_DIV_POST_MASK,
- cpg_rpcsrc_div_table, "RPCSRC");
+ gen3_cpg_rpcsrc_div_table,
+ "RPCSRC");
+
+ case CLK_TYPE_GEN4_RPCSRC:
+ return rcar_clk_get_rate64_div_table(core->parent,
+ gen3_clk_get_rate64(&parent),
+ priv->base + CPG_RPCCKCR,
+ CPG_RPCCKCR_DIV_POST_MASK,
+ gen4_cpg_rpcsrc_div_table,
+ "RPCSRC");
case CLK_TYPE_GEN3_D3_RPCSRC:
case CLK_TYPE_GEN3_E3_RPCSRC:
@@ -409,6 +458,7 @@ static int gen3_clk_probe(struct udevice *dev)
struct gen3_clk_priv *priv = dev_get_priv(dev);
struct cpg_mssr_info *info =
(struct cpg_mssr_info *)dev_get_driver_data(dev);
+ const void *pll_config;
fdt_addr_t rst_base;
int ret;
@@ -427,21 +477,24 @@ static int gen3_clk_probe(struct udevice *dev)
priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
- priv->cpg_pll_config =
- (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
- if (!priv->cpg_pll_config->extal_div)
- return -EINVAL;
+ pll_config = info->get_pll_config(priv->cpg_mode);
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
priv->info->status_regs = mstpsr;
priv->info->control_regs = smstpcr;
priv->info->reset_regs = srcr;
priv->info->reset_clear_regs = srstclr;
- } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
- priv->info->status_regs = mstpsr_for_v3u;
- priv->info->control_regs = mstpcr_for_v3u;
- priv->info->reset_regs = srcr_for_v3u;
- priv->info->reset_clear_regs = srstclr_for_v3u;
+ priv->gen3_cpg_pll_config = pll_config;
+ if (!priv->gen3_cpg_pll_config->extal_div)
+ return -EINVAL;
+ } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
+ priv->info->status_regs = mstpsr_for_gen4;
+ priv->info->control_regs = mstpcr_for_gen4;
+ priv->info->reset_regs = srcr_for_gen4;
+ priv->info->reset_clear_regs = srstclr_for_gen4;
+ priv->gen4_cpg_pll_config = pll_config;
+ if (!priv->gen4_cpg_pll_config->extal_div)
+ return -EINVAL;
} else {
return -EINVAL;
}
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index a9c941b6db..6b7ec36ab0 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -232,11 +232,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
/*
* CPG Clock Data
*/
-
/*
* MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
* 14 13 (MHz) 21 31
- * --------------------------------------------------------
+ * ----------------------------------------------------------------
* 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
* 0 1 20 x 1 x106 x180 x106 x120 x160 /19
* 1 0 Prohibited setting
@@ -244,13 +243,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
-
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
- /* EXTAL div PLL1 mult/div Not used OSC prediv PLL5 mult/div */
- { 1, 128, 1, 128, 1, 16, 192, 1, },
- { 1, 106, 1, 106, 1, 19, 160, 1, },
- { 0, 0, 0, 0, 0, 0, 0, 0, },
- { 2, 128, 1, 128, 1, 32, 192, 1, },
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
+ { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
+ { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
+ { 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
};
/*
@@ -292,13 +290,13 @@ static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = {
.mstp_table = r8a779a0_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a779a0_mstp_table),
.reset_node = "renesas,r8a779a0-rst",
- .reset_modemr_offset = 0x00,
+ .reset_modemr_offset = CPG_RST_MODEMR0,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = CLK_EXTALR,
.get_pll_config = r8a779a0_get_pll_config,
- .reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
+ .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
};
static const struct udevice_id r8a779a0_cpg_ids[] = {
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
new file mode 100644
index 0000000000..7aac28ed49
--- /dev/null
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ * Based on r8a779a0-cpg-mssr.c
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A779F0_CLK_R,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL5,
+ CLK_PLL6,
+ CLK_PLL1_DIV2,
+ CLK_PLL2_DIV2,
+ CLK_PLL3_DIV2,
+ CLK_PLL5_DIV2,
+ CLK_PLL5_DIV4,
+ CLK_PLL6_DIV2,
+ CLK_S0,
+ CLK_SASYNCPER,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_OCO,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779f0_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+ DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
+ DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
+ DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
+ DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+
+ DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
+ DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
+ DEF_RATE(".oco", CLK_OCO, 32768),
+
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+
+ /* Core Clock Outputs */
+ DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
+ DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8),
+ DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1),
+ DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1),
+ DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1),
+ DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1),
+ DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1),
+ DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1),
+ DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1),
+ DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5_DIV2, 5, 1),
+ DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
+
+ DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
+ DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+ DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+ DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
+
+ DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
+ DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870),
+
+ DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
+
+ DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
+
+ DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779f0_mod_clks[] = {
+ DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1),
+ DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
+ DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
+ DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
+ DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
+ DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
+ DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
+ DEF_MOD("msiof0", 618, R8A779F0_CLK_MSO),
+ DEF_MOD("msiof1", 619, R8A779F0_CLK_MSO),
+ DEF_MOD("msiof2", 620, R8A779F0_CLK_MSO),
+ DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO),
+ DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
+ DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
+ DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4),
+ DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4),
+ DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4),
+ DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4),
+ DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
+ DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
+ DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
+ DEF_MOD("tmu0", 713, R8A779F0_CLK_SASYNCRT),
+ DEF_MOD("tmu1", 714, R8A779F0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu2", 715, R8A779F0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu3", 716, R8A779F0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu4", 717, R8A779F0_CLK_SASYNCPERD2),
+ DEF_MOD("wdt", 907, R8A779F0_CLK_R),
+ DEF_MOD("cmt0", 910, R8A779F0_CLK_R),
+ DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
+ DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
+ DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
+ DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
+ DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
+ DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
+ DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
+ DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
+};
+
+/*
+ * CPG Clock Data
+ */
+/*
+ * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
+ * 14 13 (MHz)
+ * ------------------------------------------------------------------------
+ * 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15
+ * 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19
+ * 1 0 Prohibited setting
+ * 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
+ { 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, },
+ { 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
+ { 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, },
+};
+
+/*
+ * Note that the only clock left running before booting Linux are now
+ * MFIS, INTC-AP, INTC-EX and HSCIF0/SCIF3 on S4
+ */
+#define MSTPCR5_HSCIF0 BIT(14)
+#define MSTPCR7_SCIF3 BIT(4) /* No information: MFIS, INTC-AP, INTC-EX */
+static const struct mstp_stop_table r8a779f0_mstp_table[] = {
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00800000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x0003c000, MSTPCR5_HSCIF0, 0x0, 0x0 },
+ { 0x03000000, 0x0, 0x0, 0x0 },
+ { 0x1ffbe040, MSTPCR7_SCIF3, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00003c78, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x9e800000, 0x0, 0x0, 0x0 },
+ { 0x00000027, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00005800, 0x0, 0x0, 0x0 },
+};
+
+static const void *r8a779f0_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a779f0_cpg_mssr_info = {
+ .core_clk = r8a779f0_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a779f0_core_clks),
+ .mod_clk = r8a779f0_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a779f0_mod_clks),
+ .mstp_table = r8a779f0_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a779f0_mstp_table),
+ .reset_node = "renesas,r8a779f0-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR0,
+ .extalr_node = "extalr",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = CLK_EXTALR,
+ .get_pll_config = r8a779f0_get_pll_config,
+ .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
+};
+
+static const struct udevice_id r8a779f0_cpg_ids[] = {
+ {
+ .compatible = "renesas,r8a779f0-cpg-mssr",
+ .data = (ulong)&r8a779f0_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(cpg_r8a779f0) = {
+ .name = "cpg_r8a779f0",
+ .id = UCLASS_NOP,
+ .of_match = r8a779f0_cpg_ids,
+ .bind = gen3_cpg_bind,
+};
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
new file mode 100644
index 0000000000..8625e8a2d3
--- /dev/null
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on r8a779f0-cpg-mssr.c
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL5,
+ CLK_PLL6,
+ CLK_PLL1_DIV2,
+ CLK_PLL2_DIV2,
+ CLK_PLL3_DIV2,
+ CLK_PLL4_DIV2,
+ CLK_PLL5_DIV2,
+ CLK_PLL5_DIV4,
+ CLK_PLL6_DIV2,
+ CLK_S0,
+ CLK_S0_VIO,
+ CLK_S0_VC,
+ CLK_S0_HSC,
+ CLK_SASYNCPER,
+ CLK_SV_VIP,
+ CLK_SV_IR,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_VIO,
+ CLK_VC,
+ CLK_OCO,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779g0_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+ DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
+ DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
+ DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
+ DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
+ DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
+ DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
+ DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
+ DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
+ DEF_RATE(".oco", CLK_OCO, 32768),
+
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+ DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
+ DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
+
+ /* Core Clock Outputs */
+ DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
+ DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
+ DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
+ DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
+ DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
+ DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
+ DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
+ DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
+ DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
+ DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
+ DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
+ DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
+ DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
+ DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
+ DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
+ DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4_per", R8A779G0_CLK_S0D4_PER, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
+ DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
+ DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
+ DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
+ DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
+ DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
+ DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
+ DEF_FIXED("sasyncrt", R8A779G0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
+ DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+ DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+ DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
+ DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
+ DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
+ DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
+ DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
+ DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
+ DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
+ DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
+ DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
+ DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
+ DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
+ DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
+ DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
+
+ DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
+ DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
+ DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
+
+ DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
+
+ DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
+ DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
+ DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
+ DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
+ DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
+ DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
+ DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
+ DEF_MOD("fcpvd0", 508, R8A779G0_CLK_VIOBUSD2),
+ DEF_MOD("fcpvd1", 509, R8A779G0_CLK_VIOBUSD2),
+ DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1),
+ DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("i2c3", 521, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
+ DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
+ DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
+ DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
+ DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
+ DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
+ DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
+ DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
+ DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0),
+ DEF_MOD("sys-dmac0", 709, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("sys-dmac1", 710, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT),
+ DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
+ DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
+ DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
+ DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
+ DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
+ DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
+ DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
+ DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
+ DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
+ DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
+ DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
+};
+
+/*
+ * CPG Clock Data
+ */
+/*
+ * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
+ * 14 13 (MHz)
+ * ------------------------------------------------------------------------
+ * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
+ * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
+ * 1 0 Prohibited setting
+ * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
+ { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, },
+ { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
+ { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, },
+};
+
+/*
+ * Note that the only clock left running before booting Linux are now
+ * MFIS, INTC-AP, INTC-EX, SCIF0, HSCIF0 on V4H
+ */
+#define MSTPCR5_HSCIF0 BIT(14) /* No information: MFIS, INTC-AP */
+#define MSTPCR6_INTCEX BIT(11) /* No information: MFIS, INTC-AP */
+#define MSTPCR7_SCIF0 BIT(2) /* No information: MFIS, INTC-AP */
+static const struct mstp_stop_table r8a779g0_mstp_table[] = {
+ { 0x0FC302A1, 0x0, 0x0, 0x0 },
+ { 0x00D50038, 0x0, 0x0, 0x0 },
+ { 0x00003800, 0x0, 0x0, 0x0 },
+ { 0xF0000000, 0x0, 0x0, 0x0 },
+ { 0x0001CE01, 0x0, 0x0, 0x0 },
+ { 0xEEFFE380, MSTPCR5_HSCIF0, 0x0, 0x0 },
+ { 0xF3FD3901, MSTPCR6_INTCEX, 0x0, 0x0 },
+ { 0xE007E6FF, MSTPCR7_SCIF0, 0x0, 0x0 },
+ { 0xC0003FFF, 0x0, 0x0, 0x0 },
+ { 0x001FBCF8, 0x0, 0x0, 0x0 },
+ { 0x30000000, 0x0, 0x0, 0x0 },
+ { 0x000000C3, 0x0, 0x0, 0x0 },
+ { 0xDE800000, 0x0, 0x0, 0x0 },
+ { 0x00000017, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x00000000, 0x0, 0x0, 0x0 },
+ { 0x000033C0, 0x0, 0x0, 0x0 },
+ { 0x402A001E, 0x0, 0x0, 0x0 },
+ { 0x0C010080, 0x0, 0x0, 0x0 },
+};
+
+static const void *r8a779g0_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a779g0_cpg_mssr_info = {
+ .core_clk = r8a779g0_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a779g0_core_clks),
+ .mod_clk = r8a779g0_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a779g0_mod_clks),
+ .mstp_table = r8a779g0_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a779g0_mstp_table),
+ .reset_node = "renesas,r8a779g0-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR0,
+ .extalr_node = "extalr",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = CLK_EXTALR,
+ .get_pll_config = r8a779g0_get_pll_config,
+ .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
+};
+
+static const struct udevice_id r8a779g0_cpg_ids[] = {
+ {
+ .compatible = "renesas,r8a779g0-cpg-mssr",
+ .data = (ulong)&r8a779g0_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(cpg_r8a779g0) = {
+ .name = "cpg_r8a779g0",
+ .id = UCLASS_NOP,
+ .of_match = r8a779g0_cpg_ids,
+ .bind = gen3_cpg_bind,
+};
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 894e376549..06318c81ac 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -34,8 +34,13 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN4_MAIN,
CLK_TYPE_GEN4_PLL1,
- CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */
+ CLK_TYPE_GEN4_PLL2,
+ CLK_TYPE_GEN4_PLL2X_3X, /* R8A779A0 only */
+ CLK_TYPE_GEN4_PLL3,
CLK_TYPE_GEN4_PLL5,
+ CLK_TYPE_GEN4_PLL4,
+ CLK_TYPE_GEN4_PLL6,
+ CLK_TYPE_GEN4_SDSRC,
CLK_TYPE_GEN4_SDH,
CLK_TYPE_GEN4_SD,
CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
@@ -107,11 +112,27 @@ struct rcar_gen3_cpg_pll_config {
u8 pll3_mult;
u8 pll3_div;
u8 osc_prediv;
+};
+
+struct rcar_gen4_cpg_pll_config {
+ u8 extal_div;
+ u8 pll1_mult;
+ u8 pll1_div;
+ u8 pll2_mult;
+ u8 pll2_div;
+ u8 pll3_mult;
+ u8 pll3_div;
+ u8 pll4_mult;
+ u8 pll4_div;
u8 pll5_mult;
u8 pll5_div;
+ u8 pll6_mult;
+ u8 pll6_div;
+ u8 osc_prediv;
};
#define CPG_RST_MODEMR 0x060
+#define CPG_RST_MODEMR0 0x000
#define CPG_SDCKCR_STPnHCK BIT(9)
#define CPG_SDCKCR_STPnCK BIT(8)
@@ -133,7 +154,10 @@ struct gen3_clk_priv {
struct clk clk_extal;
struct clk clk_extalr;
u32 cpg_mode;
- const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+ union {
+ const struct rcar_gen3_cpg_pll_config *gen3_cpg_pll_config;
+ const struct rcar_gen4_cpg_pll_config *gen4_cpg_pll_config;
+ };
};
int gen3_cpg_bind(struct udevice *parent);
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index e0895d2c2f..10bd54d600 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -128,7 +128,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
info->mstp_table[i].sdis,
info->mstp_table[i].sen);
- if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U)
+ if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
continue;
clrsetbits_le32(base + RMSTPCR(i),
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 519f88548f..71e409f3eb 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -17,7 +17,7 @@
enum clk_reg_layout {
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
- CLK_REG_LAYOUT_RCAR_V3U,
+ CLK_REG_LAYOUT_RCAR_GEN4,
};
struct cpg_mssr_info {
@@ -134,7 +134,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
* Module Standby and Software Reset register offets.
*
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
- * R-Car Gen2, R-Car Gen3, and RZ/G1.
+ * R-Car Gen2, R-Car Gen3, R-Car Gen4 and RZ/G1.
* These are NOT valid for R-Car Gen1 and RZ/A1!
*/
@@ -147,9 +147,11 @@ static const u16 mstpsr[] = {
0x9A0, 0x9A4, 0x9A8, 0x9AC,
};
-static const u16 mstpsr_for_v3u[] = {
+static const u16 mstpsr_for_gen4[] = {
0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
- 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
+ 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
+ 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
+ 0x2E60, 0x2E64, 0x2E68, 0x2E6C,
};
/*
@@ -161,9 +163,11 @@ static const u16 smstpcr[] = {
0x990, 0x994, 0x998, 0x99C,
};
-static const u16 mstpcr_for_v3u[] = {
+static const u16 mstpcr_for_gen4[] = {
0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
- 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
+ 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
+ 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
+ 0x2D60, 0x2D64, 0x2D68, 0x2D6C,
};
/*
@@ -175,9 +179,11 @@ static const u16 srcr[] = {
0x920, 0x924, 0x928, 0x92C,
};
-static const u16 srcr_for_v3u[] = {
+static const u16 srcr_for_gen4[] = {
0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
- 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
+ 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
+ 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
+ 0x2C60, 0x2C64, 0x2C68, 0x2C6C,
};
/* Realtime Module Stop Control Register offsets */
@@ -193,9 +199,11 @@ static const u16 srstclr[] = {
0x960, 0x964, 0x968, 0x96C,
};
-static const u16 srstclr_for_v3u[] = {
+static const u16 srstclr_for_gen4[] = {
0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
- 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
+ 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
+ 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
+ 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
};
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-20 07:28:50 +0000