4 files changed, 22 insertions, 7 deletions
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 5ae4781d11..bd0d3e4f47 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -115,7 +115,7 @@ static int imx6q_clk_probe(struct udevice *dev)
 
 	/* CCM clocks */
 	base = dev_read_addr_ptr(dev);
-	if (base == (void *)FDT_ADDR_T_NONE)
+	if (!base)
 		return -EINVAL;
 
 	clk_dm(IMX6QDL_CLK_USDHC1_SEL,
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index a05dac7c7a..fc41a028f6 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -323,7 +323,7 @@ static int imx8mm_clk_probe(struct udevice *dev)
 	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	base = dev_read_addr_ptr(dev);
-	if (base == (void *)FDT_ADDR_T_NONE)
+	if (!base)
 		return -EINVAL;
 
 	clk_dm(IMX8MM_CLK_A53_SRC,
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 4048cc63cc..eb43971ae6 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -293,7 +293,7 @@ static int imx8mn_clk_probe(struct udevice *dev)
 	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	base = dev_read_addr_ptr(dev);
-	if (base == (void *)FDT_ADDR_T_NONE)
+	if (!base)
 		return -EINVAL;
 
 	clk_dm(IMX8MN_CLK_A53_SRC,
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index fc16416d5f..0cdb9df45d 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -121,10 +121,16 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
 {
 	struct clk_pllv3 *pll = to_clk_pllv3(clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
-	unsigned long min_rate = parent_rate * 54 / 2;
-	unsigned long max_rate = parent_rate * 108 / 2;
+	unsigned long min_rate;
+	unsigned long max_rate;
 	u32 val, div;
 
+	if (parent_rate == 0)
+		return -EINVAL;
+
+	min_rate = parent_rate * 54 / 2;
+	max_rate = parent_rate * 108 / 2;
+
 	if (rate < min_rate || rate > max_rate)
 		return -EINVAL;
 
@@ -157,6 +163,9 @@ static ulong clk_pllv3_av_get_rate(struct clk *clk)
 	u32 div = readl(pll->base) & pll->div_mask;
 	u64 temp64 = (u64)parent_rate;
 
+	if (mfd == 0)
+		return -EIO;
+
 	temp64 *= mfn;
 	do_div(temp64, mfd);
 
@@ -167,13 +176,19 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
 {
 	struct clk_pllv3 *pll = to_clk_pllv3(clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
-	unsigned long min_rate = parent_rate * 27;
-	unsigned long max_rate = parent_rate * 54;
+	unsigned long min_rate;
+	unsigned long max_rate;
 	u32 val, div;
 	u32 mfn, mfd = 1000000;
 	u32 max_mfd = 0x3FFFFFFF;
 	u64 temp64;
 
+	if (parent_rate == 0)
+		return -EINVAL;
+
+	min_rate = parent_rate * 27;
+	max_rate = parent_rate * 54;
+
 	if (rate < min_rate || rate > max_rate)
 		return -EINVAL;