diff options
Diffstat (limited to 'doc/device-tree-bindings')
| -rw-r--r-- | doc/device-tree-bindings/arm/arm,scmi.txt | 15 | ||||
| -rw-r--r-- | doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt | 32 | ||||
| -rw-r--r-- | doc/device-tree-bindings/mmc/sandbox,mmc.txt | 18 | ||||
| -rw-r--r-- | doc/device-tree-bindings/pinctrl/apple,pinctrl.yaml | 106 |
4 files changed, 133 insertions, 38 deletions
diff --git a/doc/device-tree-bindings/arm/arm,scmi.txt b/doc/device-tree-bindings/arm/arm,scmi.txt index a76124f4a3..92572eabb5 100644 --- a/doc/device-tree-bindings/arm/arm,scmi.txt +++ b/doc/device-tree-bindings/arm/arm,scmi.txt @@ -14,7 +14,8 @@ Required properties: The scmi node with the following properties shall be under the /firmware/ node. -- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports +- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports, + or "linaro,scmi-optee" for OP-TEE transport. - mboxes: List of phandle and mailbox channel specifiers. It should contain exactly one or two mailboxes, one for transmitting messages("tx") and another optional for receiving the notifications("rx") if @@ -26,6 +27,8 @@ The scmi node with the following properties shall be under the /firmware/ node. - #size-cells : should be '0' as 'reg' property doesn't have any size associated with it. - arm,smc-id : SMC id required when using smc or hvc transports +- linaro,optee-channel-id : Channel specifier required when using OP-TEE + transport. Optional properties: @@ -33,16 +36,16 @@ Optional properties: See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details about the generic mailbox controller and client driver bindings. - -The mailbox is the only permitted method of calling the SCMI firmware. Mailbox doorbell is used as a mechanism to alert the presence of a messages and/or notification. Each protocol supported shall have a sub-node with corresponding compatible as described in the following sections. If the platform supports dedicated -communication channel for a particular protocol, the 3 properties namely: -mboxes, mbox-names and shmem shall be present in the sub-node corresponding -to that protocol. +communication channel for a particular protocol, properties shall be present +in the sub-node corresponding to that protocol. These properties are: +- mboxes, mbox-names and shmem for mailbox transport +- arm,smc-id and shmem for smc/hvc transport +- linaro,optee-channel-id and possibly shmem for OP-TEE transport Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol ------------------------------------------------------------ diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt index ac6a7df432..926e3e83b3 100644 --- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt +++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt @@ -128,23 +128,6 @@ phyc attributes: MR2 MR3 -- st,phy-cal : phy cal depending of calibration or tuning of DDR - This parameter is optional; when it is absent the built-in PHY - calibration is done. - for STM32MP15x: 12 values are requested in this order - DX0DLLCR - DX0DQTR - DX0DQSTR - DX1DLLCR - DX1DQTR - DX1DQSTR - DX2DLLCR - DX2DQTR - DX2DQSTR - DX3DLLCR - DX3DQTR - DX3DQSTR - Example: / { @@ -280,21 +263,6 @@ Example: 0x00000000 /*MR3*/ >; - st,phy-cal = < - 0x40000000 /*DX0DLLCR*/ - 0xFFFFFFFF /*DX0DQTR*/ - 0x3DB02000 /*DX0DQSTR*/ - 0x40000000 /*DX1DLLCR*/ - 0xFFFFFFFF /*DX1DQTR*/ - 0x3DB02000 /*DX1DQSTR*/ - 0x40000000 /*DX2DLLCR*/ - 0xFFFFFFFF /*DX2DQTR*/ - 0x3DB02000 /*DX2DQSTR*/ - 0x40000000 /*DX3DLLCR*/ - 0xFFFFFFFF /*DX3DQTR*/ - 0x3DB02000 /*DX3DQSTR*/ - >; - status = "okay"; }; }; diff --git a/doc/device-tree-bindings/mmc/sandbox,mmc.txt b/doc/device-tree-bindings/mmc/sandbox,mmc.txt new file mode 100644 index 0000000000..1170bcd6a0 --- /dev/null +++ b/doc/device-tree-bindings/mmc/sandbox,mmc.txt @@ -0,0 +1,18 @@ +Sandbox MMC +=========== + +Required properties: +- compatible : "sandbox,mmc" + +Optional properties: +- filename : Name of backing file, if any. This is mapped into the MMC device + so can be used to provide a filesystem or other test data + + +Example +------- + +mmc2 { + compatible = "sandbox,mmc"; + non-removable; +}; diff --git a/doc/device-tree-bindings/pinctrl/apple,pinctrl.yaml b/doc/device-tree-bindings/pinctrl/apple,pinctrl.yaml new file mode 100644 index 0000000000..d50571affd --- /dev/null +++ b/doc/device-tree-bindings/pinctrl/apple,pinctrl.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple GPIO controller + +maintainers: + - Mark Kettenis <kettenis@openbsd.org> + +description: | + The Apple GPIO controller is a simple combined pin and GPIO + controller present on Apple ARM SoC platforms, including various + iPhone and iPad devices and the "Apple Silicon" Macs. + +properties: + compatible: + items: + - const: apple,t8103-pinctrl + - const: apple,pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupts: + description: One interrupt for each of the (up to 7) interrupt + groups supported by the controller sorted by interrupt group + number in ascending order. + minItems: 1 + maxItems: 7 + + interrupt-controller: true + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + Values are constructed from pin number and alternate function + configuration number using the APPLE_PINMUX() helper macro + defined in include/dt-bindings/pinctrl/apple.h. + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/apple-aic.h> + #include <dt-bindings/pinctrl/apple.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@23c100000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3c100000 0x0 0x100000>; + clocks = <&gpio_clk>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 212>; + + interrupt-controller; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 16 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 17 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 18 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 19 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 20 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 21 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 22 IRQ_TYPE_LEVEL_HIGH>; + + pcie_pins: pcie-pins { + pinmux = <APPLE_PINMUX(150, 1)>, + <APPLE_PINMUX(151, 1)>, + <APPLE_PINMUX(32, 1)>; + }; + }; + }; |