diff options
Diffstat (limited to 'cpu')
34 files changed, 381 insertions, 1265 deletions
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 641f270490..9cbd477677 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -29,9 +29,7 @@ */ /* * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices + * 1 - this driver is intended for use with USB Mass Storage Devices * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! */ diff --git a/cpu/blackfin/Makefile b/cpu/blackfin/Makefile index 8fed4b422b..b4049ff874 100644 --- a/cpu/blackfin/Makefile +++ b/cpu/blackfin/Makefile @@ -17,14 +17,15 @@ EXTRA := CEXTRA := initcode.o SEXTRA := start.o SOBJS := interrupt.o cache.o -COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o +COBJS-y := cpu.o traps.o interrupts.o reset.o serial.o watchdog.o +COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) -COBJS += initcode.o +COBJS-y += initcode.o endif -SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) EXTRA := $(addprefix $(obj),$(EXTRA)) CEXTRA := $(addprefix $(obj),$(CEXTRA)) SEXTRA := $(addprefix $(obj),$(SEXTRA)) diff --git a/cpu/blackfin/cache.S b/cpu/blackfin/cache.S index 51bdb30e32..9facadfd17 100644 --- a/cpu/blackfin/cache.S +++ b/cpu/blackfin/cache.S @@ -39,7 +39,7 @@ ENTRY(_blackfin_dcache_flush_range) RTS; ENDPROC(_blackfin_dcache_flush_range) -ENTRY(_blackfin_dcache_invalidate_range) +ENTRY(_blackfin_dcache_flush_invalidate_range) R2 = -32; R2 = R0 & R2; P0 = R2; @@ -58,4 +58,4 @@ ENTRY(_blackfin_dcache_invalidate_range) FLUSHINV[P0]; SSYNC; RTS; -ENDPROC(_blackfin_dcache_invalidate_range) +ENDPROC(_blackfin_dcache_flush_invalidate_range) diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c index 9efd88e7ec..30c214be7b 100644 --- a/cpu/blackfin/cpu.c +++ b/cpu/blackfin/cpu.c @@ -14,11 +14,14 @@ #include <asm/blackfin.h> #include <asm/cplb.h> #include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/ebiu.h> #include <asm/mach-common/bits/trace.h> #include "cpu.h" #include "serial.h" +ulong bfin_poweron_retx; + __attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { @@ -48,6 +51,9 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); #endif + /* Save RETX so we can pass it while booting Linux */ + bfin_poweron_retx = bootflag; + #ifdef CONFIG_DEBUG_DUMP /* Turn on hardware trace buffer */ bfin_write_TBUFCTL(TBUFPWR | TBUFEN); diff --git a/cpu/blackfin/i2c.c b/cpu/blackfin/i2c.c deleted file mode 100644 index 2a3e2238c3..0000000000 --- a/cpu/blackfin/i2c.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * i2c.c - driver for Blackfin on-chip TWI/I2C - * - * Copyright (c) 2006-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> - -#ifdef CONFIG_HARD_I2C - -#include <asm/blackfin.h> -#include <i2c.h> -#include <asm/io.h> -#include <asm/mach-common/bits/twi.h> - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#ifdef TWI0_CLKDIV -#define bfin_read_TWI_CLKDIV() bfin_read_TWI0_CLKDIV() -#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) -#define bfin_read_TWI_CONTROL() bfin_read_TWI0_CONTROL() -#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read_TWI0_SLAVE_CTL() -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write_TWI0_SLAVE_CTL(val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read_TWI0_SLAVE_STAT() -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write_TWI0_SLAVE_STAT(val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read_TWI0_SLAVE_ADDR() -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write_TWI0_SLAVE_ADDR(val) -#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL() -#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val) -#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT() -#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read_TWI0_MASTER_ADDR() -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) -#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT() -#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val) -#define bfin_read_TWI_INT_MASK() bfin_read_TWI0_INT_MASK() -#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val) -#define bfin_read_TWI_FIFO_CTL() bfin_read_TWI0_FIFO_CTL() -#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val) -#define bfin_read_TWI_FIFO_STAT() bfin_read_TWI0_FIFO_STAT() -#define bfin_write_TWI_FIFO_STAT(val) bfin_write_TWI0_FIFO_STAT(val) -#define bfin_read_TWI_XMT_DATA8() bfin_read_TWI0_XMT_DATA8() -#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val) -#define bfin_read_TWI_XMT_DATA_16() bfin_read_TWI0_XMT_DATA16() -#define bfin_write_TWI_XMT_DATA16(val) bfin_write_TWI0_XMT_DATA16(val) -#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8() -#define bfin_write_TWI_RCV_DATA8(val) bfin_write_TWI0_RCV_DATA8(val) -#define bfin_read_TWI_RCV_DATA16() bfin_read_TWI0_RCV_DATA16() -#define bfin_write_TWI_RCV_DATA16(val) bfin_write_TWI0_RCV_DATA16(val) -#endif - -#ifdef DEBUG_I2C -#define PRINTD(fmt,args...) do { \ - DECLARE_GLOBAL_DATA_PTR; \ - if (gd->have_console) \ - printf(fmt ,##args); \ - } while (0) -#else -#define PRINTD(fmt,args...) -#endif - -#ifndef CONFIG_TWICLK_KHZ -#define CONFIG_TWICLK_KHZ 50 -#endif - -/* All transfers are described by this data structure */ -struct i2c_msg { - u16 addr; /* slave address */ - u16 flags; -#define I2C_M_STOP 0x2 -#define I2C_M_RD 0x1 - u16 len; /* msg length */ - u8 *buf; /* pointer to msg data */ -}; - -/** - * i2c_reset: - reset the host controller - */ -static void i2c_reset(void) -{ - /* Disable TWI */ - bfin_write_TWI_CONTROL(0); - SSYNC(); - - /* Set TWI internal clock as 10MHz */ - bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F); - - /* Set Twi interface clock as specified */ - if (CONFIG_TWICLK_KHZ > 400) - bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 / - 400) & 0xFF)); - else - bfin_write_TWI_CLKDIV(((5 * 1024 / - CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 / - CONFIG_TWICLK_KHZ) - & 0xFF)); - - /* Enable TWI */ - bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); - SSYNC(); -} - -int wait_for_completion(struct i2c_msg *msg, int timeout_count) -{ - unsigned short twi_int_stat; - unsigned short mast_stat; - int i; - - for (i = 0; i < timeout_count; i++) { - twi_int_stat = bfin_read_TWI_INT_STAT(); - mast_stat = bfin_read_TWI_MASTER_STAT(); - - if (XMTSERV & twi_int_stat) { - /* Transmit next data */ - if (msg->len > 0) { - bfin_write_TWI_XMT_DATA8(*(msg->buf++)); - msg->len--; - } else if (msg->flags & I2C_M_STOP) - bfin_write_TWI_MASTER_CTL - (bfin_read_TWI_MASTER_CTL() | STOP); - SSYNC(); - /* Clear status */ - bfin_write_TWI_INT_STAT(XMTSERV); - SSYNC(); - i = 0; - } - if (RCVSERV & twi_int_stat) { - if (msg->len > 0) { - /* Receive next data */ - *(msg->buf++) = bfin_read_TWI_RCV_DATA8(); - msg->len--; - } else if (msg->flags & I2C_M_STOP) { - bfin_write_TWI_MASTER_CTL - (bfin_read_TWI_MASTER_CTL() | STOP); - SSYNC(); - } - /* Clear interrupt source */ - bfin_write_TWI_INT_STAT(RCVSERV); - SSYNC(); - i = 0; - } - if (MERR & twi_int_stat) { - bfin_write_TWI_INT_STAT(MERR); - bfin_write_TWI_INT_MASK(0); - bfin_write_TWI_MASTER_STAT(0x3e); - bfin_write_TWI_MASTER_CTL(0); - SSYNC(); - /* - * if both err and complete int stats are set, - * return proper results. - */ - if (MCOMP & twi_int_stat) { - bfin_write_TWI_INT_STAT(MCOMP); - bfin_write_TWI_INT_MASK(0); - bfin_write_TWI_MASTER_CTL(0); - SSYNC(); - /* - * If it is a quick transfer, - * only address bug no data, not an err. - */ - if (msg->len == 0 && mast_stat & BUFRDERR) - return 0; - /* - * If address not acknowledged return -3, - * else return 0. - */ - else if (!(mast_stat & ANAK)) - return 0; - else - return -3; - } - return -1; - } - if (MCOMP & twi_int_stat) { - bfin_write_TWI_INT_STAT(MCOMP); - SSYNC(); - bfin_write_TWI_INT_MASK(0); - bfin_write_TWI_MASTER_CTL(0); - SSYNC(); - return 0; - } - } - if (msg->flags & I2C_M_RD) - return -4; - else - return -2; -} - -/** - * i2c_transfer: - Transfer one byte over the i2c bus - * - * This function can tranfer a byte over the i2c bus in both directions. - * It is used by the public API functions. - * - * @return: 0: transfer successful - * -1: transfer fail - * -2: transmit timeout - * -3: ACK missing - * -4: receive timeout - * -5: controller not ready - */ -int i2c_transfer(struct i2c_msg *msg) -{ - int ret = 0; - int timeout_count = 10000; - int len = msg->len; - - if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) { - ret = -5; - goto transfer_error; - } - - while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) - continue; - - /* Set Transmit device address */ - bfin_write_TWI_MASTER_ADDR(msg->addr); - - /* - * FIFO Initiation. - * Data in FIFO should be discarded before start a new operation. - */ - bfin_write_TWI_FIFO_CTL(0x3); - SSYNC(); - bfin_write_TWI_FIFO_CTL(0); - SSYNC(); - - if (!(msg->flags & I2C_M_RD)) { - /* Transmit first data */ - if (msg->len > 0) { - PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf, - len); - bfin_write_TWI_XMT_DATA8(*(msg->buf++)); - msg->len--; - SSYNC(); - } - } - - /* clear int stat */ - bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV); - - /* Interrupt mask . Enable XMT, RCV interrupt */ - bfin_write_TWI_INT_MASK(MCOMP | MERR | - ((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV)); - SSYNC(); - - if (len > 0 && len <= 255) - bfin_write_TWI_MASTER_CTL((len << 6)); - else if (msg->len > 255) { - bfin_write_TWI_MASTER_CTL((0xff << 6)); - msg->flags &= I2C_M_STOP; - } else - bfin_write_TWI_MASTER_CTL(0); - - /* Master enable */ - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | - ((msg->flags & I2C_M_RD) - ? MDIR : 0) | ((CONFIG_TWICLK_KHZ > - 100) ? FAST : 0)); - SSYNC(); - - ret = wait_for_completion(msg, timeout_count); - PRINTD("3 in i2c_transfer: ret=%d\n", ret); - - transfer_error: - switch (ret) { - case 1: - PRINTD(("i2c_transfer: error: transfer fail\n")); - break; - case 2: - PRINTD(("i2c_transfer: error: transmit timeout\n")); - break; - case 3: - PRINTD(("i2c_transfer: error: ACK missing\n")); - break; - case 4: - PRINTD(("i2c_transfer: error: receive timeout\n")); - break; - case 5: - PRINTD(("i2c_transfer: error: controller not ready\n")); - i2c_reset(); - break; - default: - break; - } - return ret; - -} - -/* ---------------------------------------------------------------------*/ -/* API Functions */ -/* ---------------------------------------------------------------------*/ - -void i2c_init(int speed, int slaveaddr) -{ - i2c_reset(); -} - -/** - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ - -int i2c_probe(uchar chip) -{ - struct i2c_msg msg; - u8 probebuf; - - i2c_reset(); - - probebuf = 0; - msg.addr = chip; - msg.flags = 0; - msg.len = 1; - msg.buf = &probebuf; - if (i2c_transfer(&msg)) - return -1; - - msg.addr = chip; - msg.flags = I2C_M_RD; - msg.len = 1; - msg.buf = &probebuf; - if (i2c_transfer(&msg)) - return -1; - - return 0; -} - -/** - * i2c_read: - Read multiple bytes from an i2c device - * - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - - PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip, - addr, alen, len); - - if (alen > 0) { - addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF); - msg.addr = chip; - msg.flags = 0; - msg.len = alen; - msg.buf = addr_bytes; - if (i2c_transfer(&msg)) - return -1; - } - - /* start read sequence */ - PRINTD(("i2c_read: start read sequence\n")); - msg.addr = chip; - msg.flags = I2C_M_RD; - msg.len = len; - msg.buf = buffer; - if (i2c_transfer(&msg)) - return -1; - - return 0; -} - -/** - * i2c_write: - Write multiple bytes to an i2c device - * - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - - PRINTD - ("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n", - chip, addr, alen, len, buffer[0]); - - /* chip address write */ - if (alen > 0) { - addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF); - msg.addr = chip; - msg.flags = 0; - msg.len = alen; - msg.buf = addr_bytes; - if (i2c_transfer(&msg)) - return -1; - } - - /* start read sequence */ - PRINTD(("i2c_write: start write sequence\n")); - msg.addr = chip; - msg.flags = 0; - msg.len = len; - msg.buf = buffer; - if (i2c_transfer(&msg)) - return -1; - - return 0; - -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index ffc8420f1a..e733dd20fd 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -158,7 +158,7 @@ static inline void serial_putc(char c) #endif #ifndef CONFIG_PLL_CTL_VAL -# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9)) +# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF) #endif #ifndef CONFIG_EBIU_RSTCTL_VAL diff --git a/cpu/blackfin/jtag-console.c b/cpu/blackfin/jtag-console.c new file mode 100644 index 0000000000..44c0a839ec --- /dev/null +++ b/cpu/blackfin/jtag-console.c @@ -0,0 +1,125 @@ +/* + * jtag-console.c - console driver over Blackfin JTAG + * + * Copyright (c) 2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <devices.h> +#include <asm/blackfin.h> + +#ifndef CONFIG_JTAG_CONSOLE_TIMEOUT +# define CONFIG_JTAG_CONSOLE_TIMEOUT 100 +#endif + +/* The Blackfin tends to be much much faster than the JTAG hardware. */ +static void jtag_write_emudat(uint32_t emudat) +{ + static bool overflowed = false; + ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT; + while (bfin_read_DBGSTAT() & 0x1) { + if (overflowed) + return; + if (timeout < get_timer(0)) + overflowed = true; + } + overflowed = false; + __asm__ __volatile__("emudat = %0;" : : "d"(emudat)); +} +/* Transmit a buffer. The format is: + * [32bit length][actual data] + */ +static void jtag_send(const char *c, uint32_t len) +{ + uint32_t i; + + if (len == 0) + return; + + /* First send the length */ + jtag_write_emudat(len); + + /* Then send the data */ + for (i = 0; i < len; i += 4) + jtag_write_emudat((c[i] << 0) | (c[i+1] << 8) | (c[i+2] << 16) | (c[i+3] << 24)); +} +static void jtag_putc(const char c) +{ + jtag_send(&c, 1); +} +static void jtag_puts(const char *s) +{ + jtag_send(s, strlen(s)); +} + +static int jtag_tstc(void) +{ + return (bfin_read_DBGSTAT() & 0x2); +} + +/* Receive a buffer. The format is: + * [32bit length][actual data] + */ +static size_t inbound_len; +static int leftovers_len; +static uint32_t leftovers; +static int jtag_getc(void) +{ + int ret; + uint32_t emudat; + + /* see if any data is left over */ + if (leftovers_len) { + --leftovers_len; + ret = leftovers & 0xff; + leftovers >>= 8; + return ret; + } + + /* wait for new data ! */ + while (!jtag_tstc()) + continue; + __asm__("%0 = emudat;" : "=d"(emudat)); + + if (inbound_len == 0) { + /* grab the length */ + inbound_len = emudat; + } else { + /* store the bytes */ + leftovers_len = min(4, inbound_len); + inbound_len -= leftovers_len; + leftovers = emudat; + } + + return jtag_getc(); +} + +int drv_jtag_console_init(void) +{ + device_t dev; + int ret; + + memset(&dev, 0x00, sizeof(dev)); + strcpy(dev.name, "jtag"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.putc = jtag_putc; + dev.puts = jtag_puts; + dev.tstc = jtag_tstc; + dev.getc = jtag_getc; + + ret = device_register(&dev); + return (ret == 0 ? 1 : ret); +} + +#ifdef CONFIG_UART_CONSOLE_IS_JTAG +/* Since the JTAG is always available (at power on), allow it to fake a UART */ +void serial_set_baud(uint32_t baud) {} +void serial_setbrg(void) {} +int serial_init(void) { return 0; } +void serial_putc(const char c) __attribute__((alias("jtag_putc"))); +void serial_puts(const char *s) __attribute__((alias("jtag_puts"))); +int serial_tstc(void) __attribute__((alias("jtag_tstc"))); +int serial_getc(void) __attribute__((alias("jtag_getc"))); +#endif diff --git a/cpu/blackfin/reset.c b/cpu/blackfin/reset.c index d1e34b3f94..284cea579d 100644 --- a/cpu/blackfin/reset.c +++ b/cpu/blackfin/reset.c @@ -29,26 +29,35 @@ void bfin_reset(void) */ __builtin_bfin_ssync(); - while (1) { + /* The bootrom checks to see how it was reset and will + * automatically perform a software reset for us when + * it starts executing after the core reset. + */ + if (ANOMALY_05000353 || ANOMALY_05000386) { /* Initiate System software reset. */ bfin_write_SWRST(0x7); /* Due to the way reset is handled in the hardware, we need - * to delay for 7 SCLKS. The only reliable way to do this is - * to calculate the CCLK/SCLK ratio and multiply 7. For now, + * to delay for 10 SCLKS. The only reliable way to do this is + * to calculate the CCLK/SCLK ratio and multiply 10. For now, * we'll assume worse case which is a 1:15 ratio. */ asm( "LSETUP (1f, 1f) LC0 = %0\n" "1: nop;" : - : "a" (15 * 7) + : "a" (15 * 10) : "LC0", "LB0", "LT0" ); /* Clear System software reset */ bfin_write_SWRST(0); + /* The BF526 ROM will crash during reset */ +#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) + bfin_read_SWRST(); +#endif + /* Wait for the SWRST write to complete. Cannot rely on SSYNC * though as the System state is all reset now. */ @@ -59,10 +68,11 @@ void bfin_reset(void) : "a" (15 * 1) : "LC1", "LB1", "LT1" ); + } + while (1) /* Issue core reset */ asm("raise 1"); - } } /* We need to trampoline ourselves up into L1 since our linker diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 0d6f377c05..42534bd9b9 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -29,6 +29,8 @@ #include <asm/blackfin.h> #include <asm/mach-common/bits/uart.h> +#ifdef CONFIG_UART_CONSOLE + #if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0) # error CONFIG_UART_CONSOLE must be 0 on parts with only one UART #endif @@ -170,3 +172,5 @@ void serial_puts(const char *s) while (*s) serial_putc(*s++); } + +#endif diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index ec40c266ac..f671096768 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -14,6 +14,10 @@ #include <asm/blackfin.h> #include <asm/mach-common/bits/uart.h> +#ifndef CONFIG_UART_CONSOLE +# define CONFIG_UART_CONSOLE 0 +#endif + #ifdef CONFIG_DEBUG_EARLY_SERIAL # define BFIN_DEBUG_EARLY_SERIAL 1 #else @@ -95,7 +99,16 @@ __attribute__((always_inline)) static inline void serial_do_portmux(void) { -#ifdef __ADSPBF52x__ +#if defined(__ADSPBF51x__) +# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ + bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + switch (CONFIG_UART_CONSOLE) { + case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */ + case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */ + } + SSYNC(); +#elif defined(__ADSPBF52x__) # define DO_MUX(port, mux, tx, rx) \ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S index 9975a0c62f..6c8def4816 100644 --- a/cpu/blackfin/start.S +++ b/cpu/blackfin/start.S @@ -125,8 +125,11 @@ ENTRY(_start) */ r6 = 1 (x); - /* Relocate from wherever are (FLASH/RAM/etc...) to the - * hardcoded monitor location in the end of RAM. + /* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded + * monitor location in the end of RAM. We know that memcpy() only + * uses registers, so it is safe to call here. Note that this only + * copies to external memory ... we do not start executing out of + * it yet (see "lower to 15" below). */ serial_early_puts("Relocate"); call _get_pc; @@ -135,27 +138,16 @@ ENTRY(_start) r2.h = .Loffset; r3.l = _start; r3.h = _start; - r1 = r2 - r3; - - r0 = r0 - r1; - - cc = r0 == r3; + r2 = r2 - r3; + r1 = r0 - r2; + cc = r1 == r3; if cc jump .Lnorelocate; - r6 = 0 (x); - p1 = r0; - - p2.l = LO(CONFIG_SYS_MONITOR_BASE); - p2.h = HI(CONFIG_SYS_MONITOR_BASE); - p3 = 0x04; - p4.l = LO(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN); - p4.h = HI(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN); -.Lloop1: - r1 = [p1 ++ p3]; - [p2 ++ p3] = r1; - cc=p2==p4; - if !cc jump .Lloop1; + r0 = r3; + r2.l = LO(CONFIG_SYS_MONITOR_LEN); + r2.h = HI(CONFIG_SYS_MONITOR_LEN); + call _memcpy_ASM; /* Initialize BSS section ... we know that memset() does not * use the BSS, so it is safe to call here. The bootrom LDR @@ -173,9 +165,8 @@ ENTRY(_start) .Lnorelocate: /* Setup the actual stack in external memory */ - r0.h = HI(CONFIG_STACKBASE); - r0.l = LO(CONFIG_STACKBASE); - sp = r0; + sp.h = HI(CONFIG_STACKBASE); + sp.l = LO(CONFIG_STACKBASE); fp = sp; /* Now lower ourselves from the highest interrupt level to @@ -183,7 +174,9 @@ ENTRY(_start) * setting the 15 handler to ".Lenable_nested", raising the 15 * interrupt, and then returning from the highest interrupt * level to the dummy "jump" until the interrupt controller - * services the pending 15 interrupt. + * services the pending 15 interrupt. If executing out of + * flash, these steps also changes the code flow from flash + * to external memory. */ serial_early_puts("Lower to 15"); r0 = r7; diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c index d17c0a195d..a2c6f1eceb 100644 --- a/cpu/blackfin/traps.c +++ b/cpu/blackfin/traps.c @@ -111,23 +111,12 @@ void trap_c(struct pt_regs *regs) } if (i == ARRAY_SIZE(bfin_memory_map)) { printf("%cCPLB exception outside of memory map at 0x%p\n", - (data ? 'D' : 'I'), new_cplb_addr); + (data ? 'D' : 'I'), (void *)new_cplb_addr); bfin_panic(regs); } else debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end); new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags); - /* Turn the cache off */ - SSYNC(); - if (data) { - asm(" .align 8; "); - *pDMEM_CONTROL &= ~ENDCPLB; - } else { - asm(" .align 8; "); - *pIMEM_CONTROL &= ~ENICPLB; - } - SSYNC(); - if (data) { CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0; CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0; @@ -149,8 +138,17 @@ void trap_c(struct pt_regs *regs) debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA); last_evicted = i + 1; + + /* need to turn off cplbs whenever we muck with the cplb table */ +#if ENDCPLB != ENICPLB +# error cplb enable bit violates my sanity +#endif + uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL); + bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB); *CPLB_ADDR = new_cplb_addr; *CPLB_DATA = new_cplb_data; + bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB); + SSYNC(); /* dump current table for debugging purposes */ CPLB_ADDR = CPLB_ADDR_BASE; @@ -158,17 +156,6 @@ void trap_c(struct pt_regs *regs) for (i = 0; i < 16; ++i) debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++); - /* Turn the cache back on */ - SSYNC(); - if (data) { - asm(" .align 8; "); - *pDMEM_CONTROL |= ENDCPLB; - } else { - asm(" .align 8; "); - *pIMEM_CONTROL |= ENICPLB; - } - SSYNC(); - break; } @@ -220,20 +207,21 @@ static const char *symbol_lookup(unsigned long addr, unsigned long *caddr) static void decode_address(char *buf, unsigned long address) { unsigned long sym_addr; + void *paddr = (void *)address; const char *sym = symbol_lookup(address, &sym_addr); if (sym) { - sprintf(buf, "<0x%p> { %s + 0x%x }", address, sym, address - sym_addr); + sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr); return; } if (!address) - sprintf(buf, "<0x%p> /* Maybe null pointer? */", address); + sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr); else if (address >= CONFIG_SYS_MONITOR_BASE && address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - sprintf(buf, "<0x%p> /* somewhere in u-boot */", address); + sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr); else - sprintf(buf, "<0x%p> /* unknown address */", address); + sprintf(buf, "<0x%p> /* unknown address */", paddr); } static char *strhwerrcause(uint16_t hwerrcause) @@ -273,7 +261,7 @@ static char *strexcause(uint16_t excause) void dump(struct pt_regs *fp) { char buf[150]; - size_t i; + int i; uint16_t hwerrcause, excause; if (!ENABLE_DUMP) @@ -288,8 +276,8 @@ void dump(struct pt_regs *fp) printf("SEQUENCER STATUS:\n"); printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", fp->seqstat, fp->ipend, fp->syscfg); - printf(" HWERRCAUSE: 0x%lx: %s\n", hwerrcause, strhwerrcause(hwerrcause)); - printf(" EXCAUSE : 0x%lx: %s\n", excause, strexcause(excause)); + printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause)); + printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause)); for (i = 6; i <= 15; ++i) { if (fp->ipend & (1 << i)) { decode_address(buf, bfin_read32(EVT0 + 4*i)); @@ -323,7 +311,7 @@ void dump(struct pt_regs *fp) printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", fp->p0, fp->p1, fp->p2, fp->p3); printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", - fp->p4, fp->p5, fp->fp, fp); + fp->p4, fp->p5, fp->fp, (unsigned long)fp); printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0, fp->lc0); printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n", @@ -349,7 +337,7 @@ void dump_bfin_trace_buffer(void) { char buf[150]; unsigned long tflags; - size_t i = 0; + int i = 0; if (!ENABLE_DUMP) return; diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile index e1fb327bb4..7e98d87026 100644 --- a/cpu/ixp/Makefile +++ b/cpu/ixp/Makefile @@ -26,10 +26,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o timer.o pci.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +COBJS-y += cpu.o +COBJS-y += interrupts.o +ifndef CONFIG_USE_IRQ +COBJS-y += timer.o +endif + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index 27872fb784..fd545b5a25 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -86,9 +86,6 @@ int cpu_init (void) FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif -#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) - pci_init(); -#endif return 0; } diff --git a/cpu/ixp/npe/IxNpeDlImageMgr.c b/cpu/ixp/npe/IxNpeDlImageMgr.c index ccc0da7ebd..9bcdc9c0d8 100644 --- a/cpu/ixp/npe/IxNpeDlImageMgr.c +++ b/cpu/ixp/npe/IxNpeDlImageMgr.c @@ -133,20 +133,14 @@ typedef struct */ static IxNpeDlImageMgrStats ixNpeDlImageMgrStats; -/* default image */ -#ifdef CONFIG_IXP4XX_NPE_EXT_UCODE_BASE -static UINT32 *IxNpeMicroCodeImageLibrary = (UINT32 *)CONFIG_IXP4XX_NPE_EXT_UCODE_BASE; -#else -static UINT32 *IxNpeMicroCodeImageLibrary = (UINT32 *)IxNpeMicrocode_array; -#endif - static UINT32* getIxNpeMicroCodeImageLibrary(void) { char *s; + if ((s = getenv("npe_ucode")) != NULL) return (UINT32*) simple_strtoul(s, NULL, 16); else - return IxNpeMicroCodeImageLibrary; + return NULL; } /* @@ -422,7 +416,7 @@ ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary) (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary; BOOL result = TRUE; - if (header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) + if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) { result = FALSE; ixNpeDlImageMgrStats.invalidSignature++; @@ -643,6 +637,11 @@ ixNpeDlImageMgrImageFind ( } #else imageLibrary = getIxNpeMicroCodeImageLibrary(); + if (imageLibrary == NULL) + { + printf ("npe: ERROR, no Microcode found in memory\n"); + return IX_FAIL; + } #endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */ } diff --git a/cpu/ixp/npe/Makefile b/cpu/ixp/npe/Makefile index 25117d787f..f4f97bd0d3 100644 --- a/cpu/ixp/npe/Makefile +++ b/cpu/ixp/npe/Makefile @@ -25,11 +25,11 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnpe.a -LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB +LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux CFLAGS += $(LOCAL_CFLAGS) HOST_CFLAGS += $(LOCAL_CFLAGS) -COBJS := npe.o \ +COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \ miiphy.o \ IxOsalBufferMgt.o \ IxOsalIoMem.o \ @@ -79,17 +79,13 @@ COBJS := npe.o \ IxNpeMhSolicitedCbMgr.o \ IxNpeMhUnsolicitedCbMgr.o -ifndef CONFIG_IXP4XX_NPE_EXT_UCODE_BASE -COBJS += IxNpeMicrocode.o -endif - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) all: $(LIB) -$(LIB): $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index bd77fed377..03e3bf7c16 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -44,8 +44,6 @@ #include <npe.h> -#ifdef CONFIG_IXP4XX_NPE - static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL; static int npe_exists[NPE_NUM_PORTS]; static int npe_used[NPE_NUM_PORTS]; @@ -690,5 +688,3 @@ int npe_initialize(bd_t * bis) return 1; } - -#endif /* CONFIG_IXP4XX_NPE */ diff --git a/cpu/ixp/pci.c b/cpu/ixp/pci.c deleted file mode 100644 index 8c6b0b21b4..0000000000 --- a/cpu/ixp/pci.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * IXP PCI Init - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> - -#ifdef CONFIG_PCI - -#include <asm/processor.h> -#include <asm/io.h> -#include <pci.h> -#include <asm/arch/ixp425.h> -#include <asm/arch/ixp425pci.h> - -static void non_prefetch_read (unsigned int addr, unsigned int cmd, - unsigned int *data); -static void non_prefetch_write (unsigned int addr, unsigned int cmd, - unsigned int data); -static void configure_pins (void); -static void sys_pci_gpio_clock_config (void); -static void pci_bus_scan (void); -static int pci_device_exists (unsigned int deviceNo); -static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus, - unsigned int dev, unsigned int func); -static void sys_pci_device_bars_write (void); -static void calc_bars (PciBar * Bars[], unsigned int nBars, - unsigned int startAddr); - -#define PCI_MEMORY_BUS 0x00000000 -#define PCI_MEMORY_PHY 0x48000000 -#define PCI_MEMORY_SIZE 0x04000000 - -#define PCI_MEM_BUS 0x40000000 -#define PCI_MEM_PHY 0x00000000 -#define PCI_MEM_SIZE 0x04000000 - -#define PCI_IO_BUS 0x40000000 -#define PCI_IO_PHY 0x50000000 -#define PCI_IO_SIZE 0x10000000 - -struct pci_controller hose; - -unsigned int nDevices; -unsigned int nMBars; -unsigned int nIOBars; -PciBar *memBars[IXP425_PCI_MAX_BAR]; -PciBar *ioBars[IXP425_PCI_MAX_BAR]; -PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS]; - -int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val) -{ - unsigned int retval; - unsigned int addr; - - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval); - - *val = retval; - - return (OK); -} - -int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val) -{ - unsigned int n; - unsigned int retval; - unsigned int addr; - unsigned int byteEnables; - - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - - /*Pick out the word we are interested in */ - *val = (retval >> (8 * n)); - - return (OK); -} - -int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val) -{ - unsigned int retval; - unsigned int n; - unsigned int byteEnables; - unsigned int addr; - - n = where % 4; - /*byte enables are 4 bits, active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - - /*address bits 31:28 specify the device, 10:8 specify the function */ - /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - /*Pick out the byte we are interested in */ - *val = (retval >> (8 * n)); - - return (OK); -} - -int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be written */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - return (OK); -} - -int pci_write_config_word (pci_dev_t dev, int where, unsigned short val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - return (OK); -} - -int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val) -{ - unsigned int addr; - - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val); - - return (OK); -} - -void non_prefetch_read (unsigned int addr, - unsigned int cmd, unsigned int *data) -{ - REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); - - /*set up and execute the read */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); - - /*The result of the read is now in np_rdata */ - REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data); - - return; -} - -void non_prefetch_write (unsigned int addr, - unsigned int cmd, unsigned int data) -{ - - REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); - /*set up the write */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); - /*Execute the write by writing to NP_WDATA */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data); - - return; -} - -/* - * PCI controller config registers are accessed through these functions - * i.e. these allow us to set up our own BARs etc. - */ -void crp_read (unsigned int offset, unsigned int *data) -{ - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset); - REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data); -} - -void crp_write (unsigned int offset, unsigned int data) -{ - /*The CRP address register bit 16 indicates that we want to do a write */ - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, - PCI_CRP_WRITE | offset); - REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data); -} - -/*struct pci_controller *hose*/ -void pci_ixp_init (struct pci_controller *hose) -{ - unsigned int regval; - - hose->first_busno = 0; - hose->last_busno = 0x00; - - /* System memory space */ - pci_set_region (hose->regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region (hose->regions + 1, - PCI_MEM_BUS, - PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose (hose); - -/* - ========================================================== - Init IXP PCI - ========================================================== -*/ - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= 1 << 2; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - - configure_pins (); - - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13))); - udelay (533); - sys_pci_gpio_clock_config (); - REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0); - udelay (100); - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13)); - udelay (533); - crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT); - /*Setup PCI-AHB and AHB-PCI address mappings */ - REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET, - IXP425_PCI_AHBMEMBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET, - IXP425_PCI_AHBIOBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET, - IXP425_PCI_PCIMEMBASE_DEFAULT); - - crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); - udelay (1000); - - pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD); - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("Device bus dev func deviceID vendorID \n"); -#endif - pci_bus_scan (); -} - -void configure_pins (void) -{ - unsigned int regval; - - /* Disable clock on GPIO PIN 14 */ - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8))); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOER, - (((~(3 << 13)) & regval) | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPIT2R, - (regval & - ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1))); - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); -} - -void sys_pci_gpio_clock_config (void) -{ - unsigned int regval; - - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 4; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 8; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); -} - -void pci_bus_scan (void) -{ - unsigned int bus = 0, dev, func = 0; - unsigned short data16; - unsigned int data32; - unsigned char intPin; - - /* Assign first device to ourselves */ - devices[0].bus = 0; - devices[0].device = 0; - devices[0].func = 0; - - crp_read (PCI_CFG_VENDOR_ID, &data32); - - devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK; - devices[0].device_id = data32 >> 16; - devices[0].error = FALSE; - devices[0].bar[NO_BAR].size = 0; /*dummy - required */ - - nDevices = 1; - - nMBars = 0; - nIOBars = 0; - - for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) { - - /*Check whether a device is present */ - if (pci_device_exists (dev) != TRUE) { - - /*Clear error bits in ISR, write 1 to clear */ - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | - PCI_ISR_AHBE); - continue; - } - - /*A device is present, add an entry to the array */ - devices[nDevices].bus = bus; - devices[nDevices].device = dev; - devices[nDevices].func = func; - - pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16); - - devices[nDevices].vendor_id = data16; - - pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16); - devices[nDevices].device_id = data16; - - /*The device is functioning correctly, set error to FALSE */ - devices[nDevices].error = FALSE; - - /*Figure out what BARs are on this device */ - sys_pci_bar_info_get (nDevices, bus, dev, func); - /*Figure out what INTX# line the card uses */ - pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin); - - /*assign the appropriate irq line */ - if (intPin > PCI_IRQ_LINES) { - devices[nDevices].error = TRUE; - } else if (intPin != 0) { - /*This device uses an interrupt line */ - /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */ - devices[nDevices].irq = intPin; - } -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("%06d %03d %03d %04d %08d %08x\n", nDevices, - devices[nDevices].vendor_id); -#endif - nDevices++; - - } - - calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE); - sys_pci_device_bars_write (); - - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -} - -void sys_pci_bar_info_get (unsigned int devnum, - unsigned int bus, - unsigned int dev, unsigned int func) -{ - unsigned int data32; - unsigned int tmp; - unsigned int size; - - pci_write_config_dword (devnum, - PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY); - pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32); - - devices[devnum].bar[0].address = (data32 & 1); - - if (data32 & 1) { - /* IO space */ - tmp = data32 & ~0x3; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nIOBars < IXP425_PCI_MAX_BAR) { - ioBars[nIOBars++] = &devices[devnum].bar[0]; - } - } else { - /* Mem space */ - tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nMBars < IXP425_PCI_MAX_BAR) { - memBars[nMBars++] = &devices[devnum].bar[0]; - } else { - devices[devnum].error = TRUE; - } - - } - - devices[devnum].bar[1].size = 0; -} - -void sortBars (PciBar * Bars[], unsigned int nBars) -{ - unsigned int i, j; - PciBar *tmp; - - if (nBars == 0) { - return; - } - - /* Sort biggest to smallest */ - for (i = 0; i < nBars - 1; i++) { - for (j = i + 1; j < nBars; j++) { - if (Bars[j]->size > Bars[i]->size) { - /* swap them */ - tmp = Bars[i]; - Bars[i] = Bars[j]; - Bars[j] = tmp; - } - } - } -} - -void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr) -{ - unsigned int i; - - if (nBars == 0) { - return; - } - - for (i = 0; i < nBars; i++) { - Bars[i]->address |= startAddr; - startAddr += Bars[i]->size; - } -} - -void sys_pci_device_bars_write (void) -{ - unsigned int i; - int addr; - - for (i = 1; i < nDevices; i++) { - if (devices[i].error) { - continue; - } - - pci_write_config_dword (devices[i].device, - PCI_CFG_BASE_ADDRESS_0, - devices[i].bar[0].address); - addr = BIT (31 - devices[i].device) | - (0 << PCI_NP_AD_FUNCSL) | - (PCI_CFG_BASE_ADDRESS_0 & ~3); - pci_write_config_dword (devices[i].device, - PCI_CFG_DEV_INT_LINE, devices[i].irq); - - pci_write_config_word (devices[i].device, - PCI_CFG_COMMAND, INITIAL_PCI_CMD); - - } -} - - -int pci_device_exists (unsigned int deviceNo) -{ - unsigned int vendorId; - unsigned int regval; - - pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId); - - /* There are two ways to find out an empty device. - * 1. check Master Abort bit after the access. - * 2. check whether the vendor id read back is 0x0. - */ - REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval); - if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) { - return TRUE; - } - /*no device present, make sure that the master abort bit is reset */ - - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE); - return FALSE; -} - -pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo) -{ - unsigned int i; - unsigned int devdidvid; - unsigned int didvid; - unsigned int vendorId, deviceId; - - vendorId = ids->vendor; - deviceId = ids->device; - didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) | - (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK); - - for (i = devNo + 1; i < nDevices; i++) { - - pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID, - &devdidvid); - - if (devdidvid == didvid) { - return devices[i].device; - } - } - return -1; -} -#endif /* CONFIG_PCI */ diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c deleted file mode 100644 index dd26af49b5..0000000000 --- a/cpu/ixp/serial.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/arch/ixp425.h> - -/* - * 14.7456 MHz - * Baud Rate = -------------- - * 16 x Divisor - */ -#define SERIAL_CLOCK 921600 - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg (void) -{ - unsigned int quot = 0; - int uart = CONFIG_SYS_IXP425_CONSOLE; - - if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0)) - quot = SERIAL_CLOCK / gd->baudrate; - else - hang (); - - IER(uart) = 0; /* Disable for now */ - FCR(uart) = 0; /* No fifos enabled */ - - /* set baud rate */ - LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - DLL(uart) = quot & 0xff; - DLH(uart) = quot >> 8; - LCR(uart) = LCR_WLS0 | LCR_WLS1; -#ifdef CONFIG_SERIAL_RTS_ACTIVE - MCR(uart) = MCR_RTS; /* set RTS active */ -#else - MCR(uart) = 0; /* set RTS inactive */ -#endif - IER(uart) = IER_UUE; -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - /* wait for room in the tx FIFO on UART */ - while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0); - - THR(CONFIG_SYS_IXP425_CONSOLE) = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ - return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)); - - return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c index 09d8ad5602..deb227a1a6 100644 --- a/cpu/ixp/timer.c +++ b/cpu/ixp/timer.c @@ -32,7 +32,6 @@ #include <common.h> #include <asm/arch/ixp425.h> -#ifndef CONFIG_USE_IRQ ulong get_timer (ulong base) { return get_timer_masked () - base; @@ -80,4 +79,3 @@ ulong get_timer_masked (void) } return (reload_constant - current); } -#endif /* #ifndef CONFIG_USE_IRQ */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index 17489da8d4..ea02efbb0d 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -27,9 +27,7 @@ */ /* * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices + * 1 - this driver is intended for use with USB Mass Storage Devices * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! */ @@ -56,7 +54,7 @@ #define USBH_ENABLE_CE (1<<3) #define USBH_ENABLE_RD (1<<4) -#ifdef LITTLEENDIAN +#ifdef __LITTLE_ENDIAN #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) #else #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index b7180b0c6c..d5a16047de 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -65,6 +65,34 @@ void flush_cache(ulong start_addr, ulong size) } } +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Invalidate_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { write_c0_entrylo0(low0); diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 542bf21c77..5992111c1d 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -137,7 +137,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(clocks, 1, 0, do_clocks, - "clocks - print clock configuration\n", + "print clock configuration", " clocks\n" ); diff --git a/cpu/mpc8260/Makefile b/cpu/mpc8260/Makefile index 80d785229c..9f0c2dd50c 100644 --- a/cpu/mpc8260/Makefile +++ b/cpu/mpc8260/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -27,9 +27,13 @@ LIB = $(obj)lib$(CPU).a START = start.o kgdb.o COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ - interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \ + interrupts.o ether_fcc.o i2c.o commproc.o \ bedbug_603e.o pci.o spi.o +COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o + +COBJS += $(COBJS-y) + SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c index f1be485e8e..c969ff65e6 100644 --- a/cpu/mpc8260/bedbug_603e.c +++ b/cpu/mpc8260/bedbug_603e.c @@ -72,7 +72,7 @@ void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } @@ -119,7 +119,7 @@ void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) || (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' )))) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index b9e748ab8b..f4beca55be 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -326,5 +326,8 @@ int cpu_eth_init(bd_t *bis) #if defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); #endif +#if defined(CONFIG_ETHER_ON_SCC) + mpc82xx_scc_enet_initialize(bd); +#endif return 0; } diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index c65f0e068f..3671ef1dfb 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -10,6 +10,12 @@ * Advent Networks, Inc. <http://www.adventnetworks.com> * Jay Monkman <jtm@smoothsmoothie.com> * + * Modified so that it plays nicely when more than one ETHERNET interface + * is in use a la ether_fcc.c. + * (C) Copyright 2008 + * DENX Software Engineerin GmbH + * Gary Jennejohn <garyj@denx.de> + * * See file CREDITS for list of people who contributed to this * project. * @@ -32,11 +38,14 @@ #include <common.h> #include <asm/cpm_8260.h> #include <mpc8260.h> +#include <malloc.h> #include <net.h> #include <command.h> #include <config.h> -#if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_CMD_NET) +#ifndef CONFIG_NET_MULTI +#error "CONFIG_NET_MULTI must be defined." +#endif #if (CONFIG_ETHER_INDEX == 1) # define PROFF_ENET PROFF_SCC1 @@ -100,7 +109,7 @@ typedef volatile struct CommonBufferDescriptor { static RTXBD *rtx; -int eth_send(volatile void *packet, int length) +static int sec_send(struct eth_device *dev, volatile void *packet, int length) { int i; int result = 0; @@ -137,7 +146,7 @@ int eth_send(volatile void *packet, int length) } -int eth_rx(void) +static int sec_rx(struct eth_device *dev) { int length; @@ -184,7 +193,7 @@ int eth_rx(void) * *************************************************************/ -int eth_init(bd_t *bis) +static int sec_init(struct eth_device *dev, bd_t *bis) { int i; volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; @@ -194,9 +203,14 @@ int eth_init(bd_t *bis) rxIdx = 0; txIdx = 0; - /* assign static pointer to BD area */ - dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); - rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; + /* + * Assign static pointer to BD area. + * Avoid exhausting DPRAM, which would cause a panic. + */ + if (rtx == NULL) { + dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); + rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; + } /* 24.21 - (1-3): ioports have been set up already */ @@ -338,7 +352,7 @@ int eth_init(bd_t *bis) } -void eth_halt(void) +static void sec_halt(struct eth_device *dev) { volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | @@ -346,7 +360,7 @@ void eth_halt(void) } #if 0 -void restart(void) +static void sec_restart(void) { volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | @@ -354,4 +368,20 @@ void restart(void) } #endif -#endif +int mpc82xx_scc_enet_initialize(bd_t *bis) +{ + struct eth_device *dev; + + dev = (struct eth_device *) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "SCC ETHERNET"); + dev->init = sec_init; + dev->halt = sec_halt; + dev->send = sec_send; + dev->recv = sec_rx; + + eth_register(dev); + + return 1; +} diff --git a/cpu/mpc83xx/ecc.c b/cpu/mpc83xx/ecc.c index 5ab169fe3e..f3942b411f 100644 --- a/cpu/mpc83xx/ecc.c +++ b/cpu/mpc83xx/ecc.c @@ -119,7 +119,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) writeback[1] = 0x89abcdefUL; if (argc > 4) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -350,12 +350,12 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } } - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD(ecc, 4, 0, do_ecc, - "ecc - support for DDR ECC features\n", + "support for DDR ECC features", "status - print out status info\n" "ecc captureclear - clear capture regs data\n" "ecc sbecnt <val> - set Single-Bit Error counter\n" diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 4230099c0c..9b7e7b576e 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -544,6 +544,6 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(clocks, 1, 0, do_clocks, - "clocks - print clock configuration\n", + "print clock configuration", " clocks\n" ); diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c index 5d52366392..0308bbbf7a 100644 --- a/cpu/mpc8xx/bedbug_860.c +++ b/cpu/mpc8xx/bedbug_860.c @@ -71,7 +71,7 @@ void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } @@ -122,7 +122,7 @@ void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, if( !isdigit( argv[ 1 ][ 0 ])) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c index afd5d83d95..251204beb7 100644 --- a/cpu/nios2/sysid.c +++ b/cpu/nios2/sysid.c @@ -52,7 +52,7 @@ int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sysid, 1, 1, do_sysid, - "sysid - display Nios-II system id\n\n", + "display Nios-II system id", "\n - display Nios-II system id\n" ); #endif /* CONFIG_SYS_NIOS_SYSID_BASE */ diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c index 5ef5607918..ef11cb65e4 100644 --- a/cpu/ppc4xx/bedbug_405.c +++ b/cpu/ppc4xx/bedbug_405.c @@ -71,7 +71,7 @@ void bedbug405_do_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* -------------------------------------------------- */ if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } @@ -125,7 +125,7 @@ void bedbug405_do_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* Set a breakpoint at the address */ if (!isdigit (argv[1][0])) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 6d5f8d65da..4365df9879 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -259,6 +259,7 @@ phys_size_t initdram(int board_type) #ifndef CONFIG_SYS_SDRAM_TABLE sdram_conf_t mb0cf[] = { {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */ + {(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */ {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */ }; #else @@ -269,6 +270,18 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #define CONFIG_SYS_SDRAM0_TR0 0x41094012 #endif +#ifndef CONFIG_SYS_SDRAM0_WDDCTR +#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_RTR +#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_CFG0 +#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */ +#endif + #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) #define NUM_TRIES 64 @@ -378,7 +391,7 @@ phys_size_t initdram(int board_type) mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* @@ -387,31 +400,63 @@ phys_size_t initdram(int board_type) mtsdram(mem_b0cr, mb0cf[i].reg); mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0); mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ - mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ + mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR); mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */ + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { + phys_size_t size = mb0cf[i].size; /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(mem_tr1, (tr1_bank1 | 0x80800800)); + + /* + * OK, size detected. Enable second bank if + * defined (assumes same type as bank 0) + */ +#ifdef CONFIG_SDRAM_BANK1 + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + + /* + * Check if 2nd bank is really available. + * If the size not equal to the size of the first + * bank, then disable the 2nd bank completely. + */ + if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) + != mb0cf[i].size) { + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, 0); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + } else { + /* + * We have two identical banks, so the size + * is twice the bank size + */ + size = 2 * size; + } +#endif + #ifdef CONFIG_SDRAM_ECC - ecc_init(0, mb0cf[i].size); + ecc_init(0, size); #endif /* * OK, size detected -> all done */ - return mb0cf[i].size; + return size; } } diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c index d94e139815..52b6cfd684 100644 --- a/cpu/sh4/cpu.c +++ b/cpu/sh4/cpu.c @@ -82,3 +82,11 @@ int dcache_status (void) { return 0; } + +int cpu_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + sh_eth_initialize(bis); +#endif + return 0; +} |