diff options
Diffstat (limited to 'cmd')
| -rw-r--r-- | cmd/Kconfig | 13 | ||||
| -rw-r--r-- | cmd/Makefile | 2 | ||||
| -rw-r--r-- | cmd/bdinfo.c | 15 | ||||
| -rw-r--r-- | cmd/bootefi.c | 17 | ||||
| -rw-r--r-- | cmd/mmc.c | 21 | ||||
| -rw-r--r-- | cmd/mvebu/bubt.c | 2 | ||||
| -rw-r--r-- | cmd/pmic.c | 2 | ||||
| -rw-r--r-- | cmd/rockusb.c | 74 | ||||
| -rw-r--r-- | cmd/ti/Kconfig | 10 | ||||
| -rw-r--r-- | cmd/ti/Makefile | 10 | ||||
| -rw-r--r-- | cmd/ti/ddr3.c | 338 |
11 files changed, 494 insertions, 10 deletions
diff --git a/cmd/Kconfig b/cmd/Kconfig index c033223526..35fe9d5001 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -914,6 +914,14 @@ config CMD_USB_SDP help Enables the command "sdp" which is used to have U-Boot emulating the Serial Download Protocol (SDP) via USB. +config CMD_ROCKUSB + bool "rockusb" + depends on USB_FUNCTION_ROCKUSB + help + Rockusb protocol is widely used by Rockchip SoC based devices. It can + read/write info, image to/from devices. This enable rockusb command + support to communication with rockusb device. for more detail about + this command, please read doc/README.rockusb. config CMD_USB_MASS_STORAGE bool "UMS usb mass storage" @@ -1176,6 +1184,8 @@ config CMD_UUID endmenu +source "cmd/ti/Kconfig" + config CMD_BOOTSTAGE bool "Enable the 'bootstage' command" depends on BOOTSTAGE @@ -1357,17 +1367,20 @@ config CMD_CRAMFS config CMD_EXT2 bool "ext2 command support" + select FS_EXT4 help Enables EXT2 FS command config CMD_EXT4 bool "ext4 command support" + select FS_EXT4 help Enables EXT4 FS command config CMD_EXT4_WRITE depends on CMD_EXT4 bool "ext4 write command support" + select EXT4_WRITE help Enables EXT4 FS write command diff --git a/cmd/Makefile b/cmd/Makefile index ab45bf434a..5ab47cbbf1 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -105,6 +105,7 @@ obj-$(CONFIG_CMD_READ) += read.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o obj-$(CONFIG_CMD_REISER) += reiser.o obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o +obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o obj-$(CONFIG_SANDBOX) += host.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_CMD_NVME) += nvme.o @@ -158,6 +159,7 @@ endif # !CONFIG_SPL_BUILD obj-y += nvedit.o obj-$(CONFIG_ARCH_MVEBU) += mvebu/ +obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/ filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";") diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 27ffcd55bc..c7ebad17d1 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -417,6 +417,21 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#elif defined(CONFIG_RISCV) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + + print_num("arch_number", bd->bi_arch_number); + print_bi_boot_params(bd); + print_bi_dram(bd); + print_eth_ip_addr(); + print_baudrate(); + + return 0; +} + #elif defined(CONFIG_ARC) int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 78ff109835..51213c0293 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -32,6 +32,9 @@ static void efi_init_obj_list(void) { efi_obj_list_initalized = 1; + /* Initialize EFI driver uclass */ + efi_driver_init(); + efi_console_register(); #ifdef CONFIG_PARTITIONS efi_disk_register(); @@ -103,11 +106,11 @@ static void *copy_fdt(void *fdt) /* Safe fdt location is at 128MB */ new_fdt_addr = fdt_ram_start + (128 * 1024 * 1024) + fdt_size; - if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages, + if (efi_allocate_pages(1, EFI_RUNTIME_SERVICES_DATA, fdt_pages, &new_fdt_addr) != EFI_SUCCESS) { /* If we can't put it there, put it somewhere */ new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size); - if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages, + if (efi_allocate_pages(1, EFI_RUNTIME_SERVICES_DATA, fdt_pages, &new_fdt_addr) != EFI_SUCCESS) { printf("ERROR: Failed to reserve space for FDT\n"); return NULL; @@ -122,8 +125,8 @@ static void *copy_fdt(void *fdt) } static efi_status_t efi_do_enter( - void *image_handle, struct efi_system_table *st, - asmlinkage ulong (*entry)(void *image_handle, + efi_handle_t image_handle, struct efi_system_table *st, + asmlinkage ulong (*entry)(efi_handle_t image_handle, struct efi_system_table *st)) { efi_status_t ret = EFI_LOAD_ERROR; @@ -136,8 +139,8 @@ static efi_status_t efi_do_enter( #ifdef CONFIG_ARM64 static efi_status_t efi_run_in_el2(asmlinkage ulong (*entry)( - void *image_handle, struct efi_system_table *st), - void *image_handle, struct efi_system_table *st) + efi_handle_t image_handle, struct efi_system_table *st), + efi_handle_t image_handle, struct efi_system_table *st) { /* Enable caches again */ dcache_enable(); @@ -159,7 +162,7 @@ static efi_status_t do_bootefi_exec(void *efi, void *fdt, struct efi_device_path *memdp = NULL; ulong ret; - ulong (*entry)(void *image_handle, struct efi_system_table *st) + ulong (*entry)(efi_handle_t image_handle, struct efi_system_table *st) asmlinkage; ulong fdt_pages, fdt_size, fdt_start, fdt_end; const efi_guid_t fdt_guid = EFI_FDT_GUID; @@ -23,7 +23,12 @@ static void print_mmcinfo(struct mmc *mmc) (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); - printf("Tran Speed: %d\n", mmc->tran_speed); + printf("Bus Speed: %d\n", mmc->clock); +#if CONFIG_IS_ENABLED(MMC_VERBOSE) + printf("Mode : %s\n", mmc_mode_name(mmc->selected_mode)); + mmc_dump_capabilities("card capabilities", mmc->card_caps); + mmc_dump_capabilities("host capabilities", mmc->host_caps); +#endif printf("Rd Block Len: %d\n", mmc->read_bl_len); printf("%s version %d.%d", IS_SD(mmc) ? "SD" : "MMC", @@ -40,15 +45,19 @@ static void print_mmcinfo(struct mmc *mmc) printf("Bus Width: %d-bit%s\n", mmc->bus_width, mmc->ddr_mode ? " DDR" : ""); +#if CONFIG_IS_ENABLED(MMC_WRITE) puts("Erase Group Size: "); print_size(((u64)mmc->erase_grp_size) << 9, "\n"); +#endif if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) { bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0; bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR); +#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) puts("HC WP Group Size: "); print_size(((u64)mmc->hc_wp_grp_size) << 9, "\n"); +#endif puts("User Capacity: "); print_size(mmc->capacity_user, usr_enh ? " ENH" : ""); @@ -297,6 +306,8 @@ static int do_mmc_read(cmd_tbl_t *cmdtp, int flag, return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; } + +#if CONFIG_IS_ENABLED(MMC_WRITE) static int do_mmc_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -355,6 +366,8 @@ static int do_mmc_erase(cmd_tbl_t *cmdtp, int flag, return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; } +#endif + static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -433,6 +446,7 @@ static int do_mmc_list(cmd_tbl_t *cmdtp, int flag, return CMD_RET_SUCCESS; } +#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) static int parse_hwpart_user(struct mmc_hwpart_conf *pconf, int argc, char * const argv[]) { @@ -582,6 +596,7 @@ static int do_mmc_hwpartition(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; } } +#endif #ifdef CONFIG_SUPPORT_EMMC_BOOT static int do_mmc_bootbus(cmd_tbl_t *cmdtp, int flag, @@ -785,13 +800,17 @@ static int do_mmc_bkops_enable(cmd_tbl_t *cmdtp, int flag, static cmd_tbl_t cmd_mmc[] = { U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""), U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""), +#if CONFIG_IS_ENABLED(MMC_WRITE) U_BOOT_CMD_MKENT(write, 4, 0, do_mmc_write, "", ""), U_BOOT_CMD_MKENT(erase, 3, 0, do_mmc_erase, "", ""), +#endif U_BOOT_CMD_MKENT(rescan, 1, 1, do_mmc_rescan, "", ""), U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""), U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""), U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""), +#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""), +#endif #ifdef CONFIG_SUPPORT_EMMC_BOOT U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""), U_BOOT_CMD_MKENT(bootpart-resize, 4, 0, do_mmc_boot_resize, "", ""), diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index a1997ac0d3..23fb8cd807 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -110,7 +110,7 @@ static ulong get_load_addr(void) /******************************************************************** * eMMC services ********************************************************************/ -#ifdef CONFIG_DM_MMC +#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(MMC_WRITE) static int mmc_burn_image(size_t image_size) { struct mmc *mmc; diff --git a/cmd/pmic.c b/cmd/pmic.c index 970767cdfa..7bf23fb2a9 100644 --- a/cmd/pmic.c +++ b/cmd/pmic.c @@ -201,7 +201,7 @@ static int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, } U_BOOT_CMD(pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, - " operations", + "PMIC sub-system", "list - list pmic devices\n" "pmic dev [name] - show or [set] operating PMIC device\n" "pmic dump - dump registers\n" diff --git a/cmd/rockusb.c b/cmd/rockusb.c new file mode 100644 index 0000000000..af81cdcd02 --- /dev/null +++ b/cmd/rockusb.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2017 Eddie Cai <eddie.cai.linux@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <console.h> +#include <g_dnl.h> +#include <usb.h> +#include <asm/arch/f_rockusb.h> + +static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int controller_index, dev_index; + char *usb_controller; + char *devtype; + char *devnum; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + + usb_controller = argv[1]; + controller_index = simple_strtoul(usb_controller, NULL, 0); + + if (argc >= 4) { + devtype = argv[2]; + devnum = argv[3]; + } else { + return CMD_RET_USAGE; + } + dev_index = simple_strtoul(devnum, NULL, 0); + rockusb_dev_init(devtype, dev_index); + + ret = board_usb_init(controller_index, USB_INIT_DEVICE); + if (ret) { + printf("USB init failed: %d\n", ret); + return CMD_RET_FAILURE; + } + + g_dnl_clear_detach(); + ret = g_dnl_register("usb_dnl_rockusb"); + if (ret) + return CMD_RET_FAILURE; + + if (!g_dnl_board_usb_cable_connected()) { + puts("\rUSB cable not detected, Command exit.\n"); + ret = CMD_RET_FAILURE; + goto exit; + } + + while (1) { + if (g_dnl_detach()) + break; + if (ctrlc()) + break; + usb_gadget_handle_interrupts(controller_index); + } + ret = CMD_RET_SUCCESS; + +exit: + g_dnl_unregister(); + g_dnl_clear_detach(); + board_usb_cleanup(controller_index, USB_INIT_DEVICE); + + return ret; +} + +U_BOOT_CMD(rockusb, 4, 1, do_rockusb, + "use the rockusb protocol", + "<USB_controller> <devtype> <dev[:part]> e.g. rockusb 0 mmc 0\n" +); diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig new file mode 100644 index 0000000000..efeff0d482 --- /dev/null +++ b/cmd/ti/Kconfig @@ -0,0 +1,10 @@ +menu "TI specific command line interface" + +config CMD_DDR3 + bool "command for verifying DDR features" + help + Support for testing ddr3 on TI platforms. This command + supports memory verification, memory comapre and ecc + verification if supported. + +endmenu diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile new file mode 100644 index 0000000000..7dba66f4e7 --- /dev/null +++ b/cmd/ti/Makefile @@ -0,0 +1,10 @@ +# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj- += dummy.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_DDR3) += ddr3.o +endif diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c new file mode 100644 index 0000000000..664bb5ff55 --- /dev/null +++ b/cmd/ti/ddr3.c @@ -0,0 +1,338 @@ +/* + * EMIF: DDR3 test commands + * + * Copyright (C) 2012-2017 Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/hardware.h> +#include <asm/cache.h> +#include <asm/emif.h> +#include <common.h> +#include <command.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ARCH_KEYSTONE +#include <asm/arch/ddr3.h> +#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE +#define STACKSIZE (512 << 10) /* 512 KiB */ + +#define DDR_REMAP_ADDR 0x80000000 +#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17) + +#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \ + STACKSIZE) >> 17) - 2) +#endif + +#define DDR_TEST_BURST_SIZE 1024 + +static int ddr_memory_test(u32 start_address, u32 end_address, int quick) +{ + u32 index_start, value, index; + + index_start = start_address; + + while (1) { + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) + __raw_writel(index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) { + value = __raw_readl(index); + if (value != index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readl(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + if (quick) + continue; + + /* Write a pattern for complementary values */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) + __raw_writel((u32)~index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) { + value = __raw_readl(index); + if (value != ~index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readl(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 2) + __raw_writew((u16)index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 2) { + value = __raw_readw(index); + if (value != (u16)index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readw(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 1) + __raw_writeb((u8)index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 1) { + value = __raw_readb(index); + if (value != (u8)index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readb(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + } + + puts("ddr memory test PASSED!\n"); + return 0; +} + +static int ddr_memory_compare(u32 address1, u32 address2, u32 size) +{ + u32 index, value, index2, value2; + + for (index = address1, index2 = address2; + index < address1 + size; + index += 4, index2 += 4) { + value = __raw_readl(index); + value2 = __raw_readl(index2); + + if (value != value2) { + printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n", + index, value, index2, value2); + + return -1; + } + } + + puts("ddr memory compare PASSED!\n"); + return 0; +} + +static void ddr_check_ecc_status(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt); + u32 int_status = readl(&emif->emif_irqstatus_raw_sys); + int ecc_test = 0; + char *env; + + env = env_get("ecc_test"); + if (env) + ecc_test = simple_strtol(env, NULL, 0); + + puts("ECC test Status:\n"); + if (int_status & EMIF_INT_WR_ECC_ERR_SYS_MASK) + puts("\tECC test: DDR ECC write error interrupted\n"); + + if (int_status & EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK) + if (!ecc_test) + panic("\tECC test: DDR ECC 2-bit error interrupted"); + + if (int_status & EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK) + puts("\tECC test: DDR ECC 1-bit error interrupted\n"); + + if (err_1b) + printf("\tECC test: 1-bit ECC err count: 0x%x\n", err_1b); +} + +static int ddr_memory_ecc_err(u32 addr, u32 ecc_err) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + u32 val1, val2, val3; + + debug("Disabling D-Cache before ECC test\n"); + dcache_disable(); + invalidate_dcache_all(); + + puts("Testing DDR ECC:\n"); + puts("\tECC test: Disabling DDR ECC ...\n"); + writel(0, &emif->emif_ecc_ctrl_reg); + + val1 = readl(addr); + val2 = val1 ^ ecc_err; + writel(val2, addr); + + val3 = readl(addr); + printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n", + addr, val1, val2, ecc_err, val3); + + puts("\tECC test: Enabling DDR ECC ...\n"); +#ifdef CONFIG_ARCH_KEYSTONE + ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16); + writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + ddr3_enable_ecc(EMIF1_BASE, 1); +#else + writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg); +#endif + + val1 = readl(addr); + printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1); + + ddr_check_ecc_status(); + + debug("Enabling D-cache back after ECC test\n"); + enable_caches(); + + return 0; +} + +static int is_addr_valid(u32 addr) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 start_addr, end_addr, range, ecc_ctrl; + +#ifdef CONFIG_ARCH_KEYSTONE + ecc_ctrl = EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK; + range = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16); +#else + ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + range = readl(&emif->emif_ecc_address_range_1); +#endif + + /* Check in ecc address range 1 */ + if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { + start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + + 0xFFFF; + if ((addr >= start_addr) && (addr <= end_addr)) + /* addr within ecc address range 1 */ + return 1; + } + + /* Check in ecc address range 2 */ + if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) { + range = readl(&emif->emif_ecc_address_range_2); + start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + + 0xFFFF; + if ((addr >= start_addr) && (addr <= end_addr)) + /* addr within ecc address range 2 */ + return 1; + } + + return 0; +} + +static int is_ecc_enabled(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + + return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) && + (ecc_ctrl & EMIF_ECC_REG_RMW_EN_MASK); +} + +static int do_ddr_test(cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + u32 start_addr, end_addr, size, ecc_err; + + if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) { + if (!is_ecc_enabled()) { + puts("ECC not enabled. Please Enable ECC any try again\n"); + return CMD_RET_FAILURE; + } + + start_addr = simple_strtoul(argv[2], NULL, 16); + ecc_err = simple_strtoul(argv[3], NULL, 16); + + if (!is_addr_valid(start_addr)) { + puts("Invalid address. Please enter ECC supported address!\n"); + return CMD_RET_FAILURE; + } + + ddr_memory_ecc_err(start_addr, ecc_err); + return 0; + } + + if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) || + ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0)))) + return cmd_usage(cmdtp); + + start_addr = simple_strtoul(argv[2], NULL, 16); + end_addr = simple_strtoul(argv[3], NULL, 16); + + if ((start_addr < CONFIG_SYS_SDRAM_BASE) || + (start_addr > (CONFIG_SYS_SDRAM_BASE + + get_effective_memsize() - 1)) || + (end_addr < CONFIG_SYS_SDRAM_BASE) || + (end_addr > (CONFIG_SYS_SDRAM_BASE + + get_effective_memsize() - 1)) || (start_addr >= end_addr)) { + puts("Invalid start or end address!\n"); + return cmd_usage(cmdtp); + } + + puts("Please wait ...\n"); + if (argc == 5) { + size = simple_strtoul(argv[4], NULL, 16); + ddr_memory_compare(start_addr, end_addr, size); + } else { + ddr_memory_test(start_addr, end_addr, 0); + } + + return 0; +} + +U_BOOT_CMD(ddr, 5, 1, do_ddr_test, + "DDR3 test", + "test <start_addr in hex> <end_addr in hex> - test DDR from start\n" + " address to end address\n" + "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n" + " compare DDR data of (size) bytes from start address to end\n" + " address\n" + "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n" + " in DDR data at <addr>, the command will read a 32-bit data\n" + " from <addr>, and write (data ^ bit_err) back to <addr>\n" +); |