diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/CZ.NIC/turris_omnia/turris_omnia.c | 65 | ||||
| -rw-r--r-- | board/beacon/beacon-rzg2m/MAINTAINERS | 10 | ||||
| -rw-r--r-- | board/microchip/mpfs_icicle/Kconfig | 5 | ||||
| -rw-r--r-- | board/microchip/mpfs_icicle/mpfs_icicle.c | 17 | ||||
| -rw-r--r-- | board/sifive/unmatched/Kconfig | 1 | ||||
| -rw-r--r-- | board/sifive/unmatched/spl.c | 3 | ||||
| -rw-r--r-- | board/sunxi/board.c | 8 |
7 files changed, 99 insertions, 10 deletions
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 36c596efc5..ae24d14b76 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -43,6 +43,23 @@ DECLARE_GLOBAL_DATA_PTR; #define OMNIA_I2C_EEPROM_CHIP_LEN 2 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 +#define SYS_RSTOUT_MASK MVEBU_REGISTER(0x18260) +#define SYS_RSTOUT_MASK_WD BIT(10) + +#define A385_WDT_GLOBAL_CTRL MVEBU_REGISTER(0x20300) +#define A385_WDT_GLOBAL_RATIO_MASK GENMASK(18, 16) +#define A385_WDT_GLOBAL_RATIO_SHIFT 16 +#define A385_WDT_GLOBAL_25MHZ BIT(10) +#define A385_WDT_GLOBAL_ENABLE BIT(8) + +#define A385_WDT_GLOBAL_STATUS MVEBU_REGISTER(0x20304) +#define A385_WDT_GLOBAL_EXPIRED BIT(31) + +#define A385_WDT_DURATION MVEBU_REGISTER(0x20334) + +#define A385_WD_RSTOUT_UNMASK MVEBU_REGISTER(0x20704) +#define A385_WD_RSTOUT_UNMASK_GLOBAL BIT(8) + enum mcu_commands { CMD_GET_STATUS_WORD = 0x01, CMD_GET_RESET = 0x09, @@ -141,6 +158,47 @@ static int omnia_mcu_write(u8 cmd, const void *buf, int len) return dm_i2c_write(chip, cmd, buf, len); } +static void enable_a385_watchdog(unsigned int timeout_minutes) +{ + struct sar_freq_modes sar_freq; + u32 watchdog_freq; + + printf("Enabling A385 watchdog with %u minutes timeout...\n", + timeout_minutes); + + /* + * Use NBCLK clock (a.k.a. L2 clock) as watchdog input clock with + * its maximal ratio 7 instead of default fixed 25 MHz clock. + * It allows to set watchdog duration up to the 22 minutes. + */ + clrsetbits_32(A385_WDT_GLOBAL_CTRL, + A385_WDT_GLOBAL_25MHZ | A385_WDT_GLOBAL_RATIO_MASK, + 7 << A385_WDT_GLOBAL_RATIO_SHIFT); + + /* + * Calculate watchdog clock frequency. It is defined by formula: + * freq = NBCLK / 2 / (2 ^ ratio) + * We set ratio to the maximal possible value 7. + */ + get_sar_freq(&sar_freq); + watchdog_freq = sar_freq.nb_clk * 1000000 / 2 / (1 << 7); + + /* Set watchdog duration */ + writel(timeout_minutes * 60 * watchdog_freq, A385_WDT_DURATION); + + /* Clear the watchdog expiration bit */ + clrbits_32(A385_WDT_GLOBAL_STATUS, A385_WDT_GLOBAL_EXPIRED); + + /* Enable watchdog timer */ + setbits_32(A385_WDT_GLOBAL_CTRL, A385_WDT_GLOBAL_ENABLE); + + /* Enable reset on watchdog */ + setbits_32(A385_WD_RSTOUT_UNMASK, A385_WD_RSTOUT_UNMASK_GLOBAL); + + /* Unmask reset for watchdog */ + clrbits_32(SYS_RSTOUT_MASK, SYS_RSTOUT_MASK_WD); +} + static bool disable_mcu_watchdog(void) { int ret; @@ -423,10 +481,13 @@ void spl_board_init(void) { /* * If booting from UART, disable MCU watchdog in SPL, since uploading - * U-Boot proper can take too much time and trigger it. + * U-Boot proper can take too much time and trigger it. Instead enable + * A385 watchdog with very high timeout (10 minutes) to prevent hangup. */ - if (get_boot_device() == BOOT_DEVICE_UART) + if (get_boot_device() == BOOT_DEVICE_UART) { + enable_a385_watchdog(10); disable_mcu_watchdog(); + } } int board_init(void) diff --git a/board/beacon/beacon-rzg2m/MAINTAINERS b/board/beacon/beacon-rzg2m/MAINTAINERS index 77c4057ab0..f8042bb2c4 100644 --- a/board/beacon/beacon-rzg2m/MAINTAINERS +++ b/board/beacon/beacon-rzg2m/MAINTAINERS @@ -4,3 +4,13 @@ S: Maintained F: board/beacon/beacon-rzg2m/ F: include/configs/beacon-rzg2m.h F: configs/rzg2_beacon_defconfig +F: arch/arm/dts/beacon-renesom-baseboard.dtsi +F: arch/arm/dts/beacon-renesom-som.dtsi +F: arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts +F: arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts +F: arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts +F: arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi +F: arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi +F: arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi +F: arch/arm/dts/rz-g2-beacon-u-boot.dtsi + diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 4678462378..092e411215 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -45,5 +45,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply MMC_WRITE imply MMC_SDHCI imply MMC_SDHCI_CADENCE + imply MMC_SDHCI_ADMA + imply MMC_HS200_SUPPORT + imply CMD_I2C + imply DM_I2C + imply SYS_I2C_MICROCHIP endif diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index afef719dff..e74c9fb03c 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -119,7 +119,22 @@ int board_late_init(void) if (icicle_mac_addr[idx] == ':') icicle_mac_addr[idx] = ' '; } - env_set("icicle_mac_addr", icicle_mac_addr); + env_set("icicle_mac_addr0", icicle_mac_addr); + + mac_addr[5] = device_serial_number[0] + 1; + + icicle_mac_addr[0] = '['; + + sprintf(&icicle_mac_addr[1], "%pM", mac_addr); + + icicle_mac_addr[18] = ']'; + icicle_mac_addr[19] = '\0'; + + for (idx = 0; idx < 20; idx++) { + if (icicle_mac_addr[idx] == ':') + icicle_mac_addr[idx] = ' '; + } + env_set("icicle_mac_addr1", icicle_mac_addr); return 0; } diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig index fb2c1fbb58..fe213fd504 100644 --- a/board/sifive/unmatched/Kconfig +++ b/board/sifive/unmatched/Kconfig @@ -26,6 +26,7 @@ config SPL_OPENSBI_LOAD_ADDR config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SIFIVE_FU740 + select ENV_IS_IN_SPI_FLASH select SUPPORT_SPL select RESET_SIFIVE select BINMAN diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c index d5663274cd..7c0beedc08 100644 --- a/board/sifive/unmatched/spl.c +++ b/board/sifive/unmatched/spl.c @@ -22,6 +22,7 @@ #define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12) #define MODE_SELECT_REG 0x1000 +#define MODE_SELECT_SPI 0x6 #define MODE_SELECT_SD 0xb #define MODE_SELECT_MASK GENMASK(3, 0) @@ -123,6 +124,8 @@ u32 spl_boot_device(void) u32 boot_device = mode_select & MODE_SELECT_MASK; switch (boot_device) { + case MODE_SELECT_SPI: + return BOOT_DEVICE_SPI; case MODE_SELECT_SD: return BOOT_DEVICE_MMC1; default: diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 4f5747c34a..fdbcd40269 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -698,13 +698,7 @@ int g_dnl_board_usb_cable_connected(void) return ret; } - ret = sun4i_usb_phy_vbus_detect(&phy); - if (ret == 1) { - pr_err("A charger is plugged into the OTG\n"); - return -ENODEV; - } - - return ret; + return sun4i_usb_phy_vbus_detect(&phy); } #endif |