diff options
Diffstat (limited to 'board')
60 files changed, 17 insertions, 5117 deletions
diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig deleted file mode 100644 index ac3fe3fbcb..0000000000 --- a/board/LaCie/edminiv2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EDMINIV2 - -config SYS_BOARD - default "edminiv2" - -config SYS_VENDOR - default "LaCie" - -config SYS_CONFIG_NAME - default "edminiv2" - -endif diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS deleted file mode 100644 index 055afd0e76..0000000000 --- a/board/LaCie/edminiv2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EDMINIV2 BOARD -M: Simon Guinot <simon.guinot@sequanux.org> -S: Maintained -F: board/LaCie/edminiv2/ -F: include/configs/edminiv2.h -F: configs/edminiv2_defconfig diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile deleted file mode 100644 index 5252c2b0e6..0000000000 --- a/board/LaCie/edminiv2/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> - -obj-y := edminiv2.o ../common/common.o diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c deleted file mode 100644 index 9c066a283c..0000000000 --- a/board/LaCie/edminiv2/edminiv2.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - */ - -#include <common.h> -#include <miiphy.h> -#include <net.h> -#include <asm/arch/orion5x.h> -#include <asm/global_data.h> -#include "../common/common.h" -#include <spl.h> -#include <ns16550.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of board */ - gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; - - /* boot parameter start at 256th byte of RAM base */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - mv_phy_88e1116_init("egiga0", 8); -} -#endif /* CONFIG_RESET_PHY_R */ - -/* - * SPL serial setup and NOR boot device selection - */ - -#ifdef CONFIG_SPL_BUILD - -void spl_board_init(void) -{ - preloader_console_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NOR; -} - -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/atmark-techno/armadillo-800eva/Kconfig b/board/atmark-techno/armadillo-800eva/Kconfig deleted file mode 100644 index cd37dd4861..0000000000 --- a/board/atmark-techno/armadillo-800eva/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ARMADILLO_800EVA - -config SYS_BOARD - default "armadillo-800eva" - -config SYS_VENDOR - default "atmark-techno" - -config SYS_CONFIG_NAME - default "armadillo-800eva" - -endif diff --git a/board/atmark-techno/armadillo-800eva/MAINTAINERS b/board/atmark-techno/armadillo-800eva/MAINTAINERS deleted file mode 100644 index 6f547d82ec..0000000000 --- a/board/atmark-techno/armadillo-800eva/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ARMADILLO-800EVA BOARD -M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -S: Maintained -F: board/atmark-techno/armadillo-800eva/ -F: include/configs/armadillo-800eva.h -F: configs/armadillo-800eva_defconfig diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile deleted file mode 100644 index 7e01cb6794..0000000000 --- a/board/atmark-techno/armadillo-800eva/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - -obj-y += armadillo-800eva.o diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c deleted file mode 100644 index c1c3dfd3de..0000000000 --- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <malloc.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/rmobile.h> - -#define s_init_wait(cnt) \ - ({ \ - volatile u32 i = 0x10000 * cnt; \ - while (i > 0) \ - i--; \ - }) - -#define USBCR1 0xE605810A - -void s_init(void) -{ - struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE; - struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE; - struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE; - struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE; - struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE; - struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE; - - /* Watchdog init */ - writew(0xA500, &rwdt0->rwtcsra0); - writew(0xA500, &rwdt1->rwtcsra0); - - /* CPG */ - writel(0xFF800080, &cpg->rmstpcr4); - writel(0xFF800080, &cpg->smstpcr4); - - /* USB clock */ - writel(0x00000080, &cpg->usbckcr); - s_init_wait(1); - - /* USBCR1 */ - writew(0x0710, USBCR1); - - /* FRQCR */ - writel(0x00000000, &cpg->frqcrb); - writel(0x62030533, &cpg->frqcra); - writel(0x208A354E, &cpg->frqcrc); - writel(0x80331050, &cpg->frqcrb); - s_init_wait(1); - - writel(0x00000000, &cpg->frqcrd); - s_init_wait(1); - - /* SUBClk */ - writel(0x0000010B, &cpg->subckcr); - - /* PLL */ - writel(0x00004004, &cpg->pllc01cr); - s_init_wait(1); - - writel(0xa0000000, &cpg->pllc2cr); - s_init_wait(2); - - /* BSC */ - writel(0x0000001B, &bsc->cmncr); - - writel(0x20000000, &dbsc->dbcmd); - writel(0x10009C40, &dbsc->dbcmd); - s_init_wait(1); - - writel(0x00000007, &dbsc->dbkind); - writel(0x0E030A02, &dbsc->dbconf0); - writel(0x00000001, &dbsc->dbphytype); - writel(0x00000000, &dbsc->dbbl); - writel(0x00000006, &dbsc->dbtr0); - writel(0x00000005, &dbsc->dbtr1); - writel(0x00000000, &dbsc->dbtr2); - writel(0x00000006, &dbsc->dbtr3); - writel(0x00080006, &dbsc->dbtr4); - writel(0x00000015, &dbsc->dbtr5); - writel(0x0000000f, &dbsc->dbtr6); - writel(0x00000004, &dbsc->dbtr7); - writel(0x00000018, &dbsc->dbtr8); - writel(0x00000006, &dbsc->dbtr9); - writel(0x00000006, &dbsc->dbtr10); - writel(0x0000000F, &dbsc->dbtr11); - writel(0x0000000D, &dbsc->dbtr12); - writel(0x000000A0, &dbsc->dbtr13); - writel(0x000A0003, &dbsc->dbtr14); - writel(0x00000003, &dbsc->dbtr15); - writel(0x40005005, &dbsc->dbtr16); - writel(0x0C0C0000, &dbsc->dbtr17); - writel(0x00000200, &dbsc->dbtr18); - writel(0x00000040, &dbsc->dbtr19); - writel(0x00000001, &dbsc->dbrnk0); - writel(0x00000110, &dbsc->dbdficnt); - writel(0x00000101, &ddrp->funcctrl); - writel(0x00000001, &ddrp->dllctrl); - writel(0x00000186, &ddrp->zqcalctrl); - writel(0xB3440051, &ddrp->zqodtctrl); - writel(0x94449443, &ddrp->rdctrl); - writel(0x000000C0, &ddrp->rdtmg); - writel(0x00000101, &ddrp->fifoinit); - writel(0x02060506, &ddrp->outctrl); - writel(0x00004646, &ddrp->dqcalofs1); - writel(0x00004646, &ddrp->dqcalofs2); - writel(0x800000aa, &ddrp->dqcalexp); - writel(0x00000000, &ddrp->dllctrl); - writel(0x00000000, DDRPNCNT); - - writel(0x0000000C, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000002, DDRPNCNT); - - writel(0x0000000C, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000187, &ddrp->zqcalctrl); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000010, &dbsc->dbdficnt); - writel(0x02060507, &ddrp->outctrl); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x21009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x11000044, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x2A000000, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x2B000000, &dbsc->dbcmd); - readl(&dbsc->dbwait); - - writel(0x29000004, &dbsc->dbcmd); - readl(&dbsc->dbwait); - - writel(0x28001520, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x03000200, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x000001FF, &dbsc->dbrfcnf0); - writel(0x00010C30, &dbsc->dbrfcnf1); - writel(0x00000000, &dbsc->dbrfcnf2); - - writel(0x00000001, &dbsc->dbrfen); - writel(0x00000001, &dbsc->dbacen); - - /* BSC */ - writel(0x00410400, &bsc->cs0bcr); - writel(0x00410400, &bsc->cs2bcr); - writel(0x00410400, &bsc->cs5bbcr); - writel(0x02CB0400, &bsc->cs6abcr); - - writel(0x00000440, &bsc->cs0wcr); - writel(0x00000440, &bsc->cs2wcr); - writel(0x00000240, &bsc->cs5bwcr); - writel(0x00000240, &bsc->cs6awcr); - - writel(0x00000005, &bsc->rbwtcnt); - writel(0x00000002, &bsc->cs0wcr2); - writel(0x00000002, &bsc->cs2wcr2); - writel(0x00000002, &bsc->cs4wcr2); -} - -#define GPIO_ICCR (0xE60581A0) -#define ICCR_15BIT (1 << 15) /* any time 1 */ -#define IIC0_CONTA (1 << 7) -#define IIC0_CONTB (1 << 6) -#define IIC1_CONTA (1 << 5) -#define IIC1_CONTB (1 << 4) -#define IIC0_PS33E (1 << 1) -#define IIC1_PS33E (1 << 0) -#define GPIO_ICCR_DATA \ - (ICCR_15BIT | \ - IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \ - IIC1_CONTB | IIC0_PS33E | IIC1_PS33E) - -#define MSTPCR1 0xE6150134 -#define TMU0_MSTP125 (1 << 25) -#define I2C0_MSTP116 (1 << 16) - -#define MSTPCR3 0xE615013C -#define I2C1_MSTP323 (1 << 23) -#define GETHER_MSTP309 (1 << 9) - -#define GPIO_SCIFA1_TXD (0xE60520C4) -#define GPIO_SCIFA1_RXD (0xE60520C3) - -int board_early_init_f(void) -{ - /* TMU */ - clrbits_le32(MSTPCR1, TMU0_MSTP125); - - /* GETHER */ - clrbits_le32(MSTPCR3, GETHER_MSTP309); - - /* I2C 0/1 */ - clrbits_le32(MSTPCR1, I2C0_MSTP116); - clrbits_le32(MSTPCR3, I2C1_MSTP323); - - /* SCIFA1 */ - writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */ - writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */ - - /* IICCR */ - writew(GPIO_ICCR_DATA, GPIO_ICCR); - - return 0; -} - -DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA; - /* adress of boot parameters */ - gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100; - - /* Init PFC controller */ - r8a7740_pinmux_init(); - - /* GETHER Enable */ - gpio_request(GPIO_FN_ET_CRS, NULL); - gpio_request(GPIO_FN_ET_MDC, NULL); - gpio_request(GPIO_FN_ET_MDIO, NULL); - gpio_request(GPIO_FN_ET_TX_ER, NULL); - gpio_request(GPIO_FN_ET_RX_ER, NULL); - gpio_request(GPIO_FN_ET_ERXD0, NULL); - gpio_request(GPIO_FN_ET_ERXD1, NULL); - gpio_request(GPIO_FN_ET_ERXD2, NULL); - gpio_request(GPIO_FN_ET_ERXD3, NULL); - gpio_request(GPIO_FN_ET_TX_CLK, NULL); - gpio_request(GPIO_FN_ET_TX_EN, NULL); - gpio_request(GPIO_FN_ET_ETXD0, NULL); - gpio_request(GPIO_FN_ET_ETXD1, NULL); - gpio_request(GPIO_FN_ET_ETXD2, NULL); - gpio_request(GPIO_FN_ET_ETXD3, NULL); - gpio_request(GPIO_FN_ET_PHY_INT, NULL); - gpio_request(GPIO_FN_ET_COL, NULL); - gpio_request(GPIO_FN_ET_RX_DV, NULL); - gpio_request(GPIO_FN_ET_RX_CLK, NULL); - - gpio_request(GPIO_PORT18, NULL); /* PHY_RST */ - gpio_direction_output(GPIO_PORT18, 1); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} - -int board_late_init(void) -{ - return 0; -} - -void reset_cpu(void) -{ -} diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 018fed9cc2..a337db4efc 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -135,30 +135,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -#ifdef CONFIG_KS8851_MLL -void at91sam9n12ek_ks8851_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[2].setup); - writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | - AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), - &smc->cs[2].pulse); - writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), - &smc->cs[2].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | - AT91_SMC_MODE_TDF_CYCLE(1), - &smc->cs[2].mode); - - /* Configure NCS2 PIN */ - at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); -} -#endif - #ifdef CONFIG_USB_ATMEL void at91sam9n12ek_usb_hw_init(void) { @@ -193,10 +169,6 @@ int board_init(void) at91_lcd_hw_init(); #endif -#ifdef CONFIG_KS8851_MLL - at91sam9n12ek_ks8851_hw_init(); -#endif - #ifdef CONFIG_USB_ATMEL at91sam9n12ek_usb_hw_init(); #endif @@ -204,13 +176,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_KS8851_MLL -int board_eth_init(struct bd_info *bis) -{ - return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); -} -#endif - int dram_init(void) { gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig deleted file mode 100644 index 683efde764..0000000000 --- a/board/compulab/cm_t335/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_CM_T335 - -config SYS_BOARD - default "cm_t335" - -config SYS_VENDOR - default "compulab" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "cm_t335" - -endif diff --git a/board/compulab/cm_t335/MAINTAINERS b/board/compulab/cm_t335/MAINTAINERS deleted file mode 100644 index 5fb922c68b..0000000000 --- a/board/compulab/cm_t335/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM_T335 BOARD -M: Igor Grinberg <grinberg@compulab.co.il> -S: Maintained -F: board/compulab/cm_t335/ -F: include/configs/cm_t335.h -F: configs/cm_t335_defconfig diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile deleted file mode 100644 index 34f6713118..0000000000 --- a/board/compulab/cm_t335/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/ -# -# Author: Ilya Ledvich <ilya@compulab.co.il> - -obj-y += cm_t335.o -obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c deleted file mode 100644 index 1d4a3aceef..0000000000 --- a/board/compulab/cm_t335/cm_t335.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Board functions for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich <ilya@compulab.co.il> - */ - -#include <common.h> -#include <env.h> -#include <errno.h> -#include <miiphy.h> -#include <net.h> -#include <status_led.h> -#include <cpsw.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware_am33xx.h> -#include <asm/io.h> -#include <asm/gpio.h> - -#include "../common/eeprom.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - gpmc_init(); - -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF); -#endif - return 0; -} - -#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - return; -} - -static struct cpsw_slave_data cpsw_slave = { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = &cpsw_slave, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -/* PHY reset GPIO */ -#define GPIO_PHY_RST GPIO_PIN(3, 7) - -static void board_phy_init(void) -{ - gpio_request(GPIO_PHY_RST, "phy_rst"); - gpio_direction_output(GPIO_PHY_RST, 0); - mdelay(2); - gpio_set_value(GPIO_PHY_RST, 1); - mdelay(2); -} - -static void get_efuse_mac_addr(uchar *enetaddr) -{ - uint32_t mac_hi, mac_lo; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - enetaddr[0] = mac_hi & 0xFF; - enetaddr[1] = (mac_hi & 0xFF00) >> 8; - enetaddr[2] = (mac_hi & 0xFF0000) >> 16; - enetaddr[3] = (mac_hi & 0xFF000000) >> 24; - enetaddr[4] = mac_lo & 0xFF; - enetaddr[5] = (mac_lo & 0xFF00) >> 8; -} - -/* - * Routine: handle_mac_address - * Description: prepare MAC address for on-board Ethernet. - */ -static int handle_mac_address(void) -{ - uchar enetaddr[6]; - int rv; - - rv = eth_env_get_enetaddr("ethaddr", enetaddr); - if (rv) - return 0; - - rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); - if (rv) - get_efuse_mac_addr(enetaddr); - - if (!is_valid_ethaddr(enetaddr)) - return -1; - - return eth_env_set_enetaddr("ethaddr", enetaddr); -} - -#define AR8051_PHY_DEBUG_ADDR_REG 0x1d -#define AR8051_PHY_DEBUG_DATA_REG 0x1e -#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 -#define AR8051_RGMII_TX_CLK_DLY 0x100 - -int board_eth_init(struct bd_info *bis) -{ - int rv, n = 0; - const char *devname; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - rv = handle_mac_address(); - if (rv) - printf("No MAC address found!\n"); - - writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); - - board_phy_init(); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; - - /* - * CPSW RGMII Internal Delay Mode is not supported in all PVT - * operating points. So we must set the TX clock delay feature - * in the AR8051 PHY. Since we only support a single ethernet - * device, we only do this for the first instance. - */ - devname = miiphy_get_current_dev(); - - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, - AR8051_DEBUG_RGMII_CLK_DLY_REG); - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, - AR8051_RGMII_TX_CLK_DLY); - return n; -} -#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c deleted file mode 100644 index 1c326bd1b6..0000000000 --- a/board/compulab/cm_t335/mux.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinmux configuration for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich <ilya@compulab.co.il> - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mux.h> -#include <asm/io.h> - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; - -static struct module_pin_mux uart1_pin_mux[] = { - {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, - {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)}, - {-1}, -}; - -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {-1}, -}; - -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux i2c1_pin_mux[] = { - /* I2C_DATA */ - {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - /* I2C_SCLK */ - {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux rgmii1_pin_mux[] = { - {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ - {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ - {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ - {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ - {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ - {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ - {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ - {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ - {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ - {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ - {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ - {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {-1}, -}; - -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; - -static struct module_pin_mux eth_phy_rst_pin_mux[] = { - {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */ - {-1}, -}; - -static struct module_pin_mux status_led_pin_mux[] = { - {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */ - {-1}, -}; - -void set_uart_mux_conf(void) -{ - configure_module_pin_mux(uart0_pin_mux); - configure_module_pin_mux(uart1_pin_mux); -} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(i2c1_pin_mux); - configure_module_pin_mux(rgmii1_pin_mux); - configure_module_pin_mux(eth_phy_rst_pin_mux); - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(nand_pin_mux); - configure_module_pin_mux(status_led_pin_mux); -} diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c deleted file mode 100644 index 33264dfa71..0000000000 --- a/board/compulab/cm_t335/spl.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL specific code for Compulab CM-T335 board - * - * Board functions for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich <ilya@compulab.co.il> - */ - -#include <common.h> -#include <cpu_func.h> -#include <errno.h> -#include <init.h> -#include <log.h> - -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/clocks_am33xx.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware_am33xx.h> -#include <linux/sizes.h> - -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, - .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, - .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, - .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, - .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41J128MJT125_RD_DQS, - .datawdsratio0 = MT41J128MJT125_WR_DQS, - .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, - .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41J128MJT125_RATIO, - .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, - - .cmd1csratio = MT41J128MJT125_RATIO, - .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, - - .cmd2csratio = MT41J128MJT125_RATIO, - .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41J128MJT125_EMIF_SDCFG, - .ref_ctrl = MT41J128MJT125_EMIF_SDREF, - .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, - .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, - .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, - .zq_config = MT41J128MJT125_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -const struct dpll_params dpll_ddr = { -/* M N M2 M3 M4 M5 M6 */ - 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -static void probe_sdram_size(long size) -{ - switch (size) { - case SZ_512M: - ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; - break; - case SZ_256M: - ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; - break; - case SZ_128M: - ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; - break; - default: - puts("Failed configuring DRAM, resetting...\n\n"); - reset_cpu(); - } - debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); - config_ddr(303, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} - -void sdram_init(void) -{ - long size = SZ_1G; - - do { - size = size / 2; - probe_sdram_size(size); - } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); - - return; -} diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds deleted file mode 100644 index 4993880461..0000000000 --- a/board/compulab/cm_t335/u-boot.lds +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - *(.vectors) - CPUDIR/start.o (.text*) - board/compulab/cm_t335/built-in.o (.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = .; - - . = ALIGN(4); - __u_boot_list : { - KEEP(*(SORT(__u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - .hash : { *(.hash*) } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - - /* - * Deprecated: this MMU section is used by pxa at present but - * should not be used by new boards/CPUs. - */ - . = ALIGN(4096); - .mmutable : { - *(.mmutable) - } - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 7c93d30e1d..377c6aa077 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -41,7 +41,6 @@ obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif -obj-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o ifndef CONFIG_RAMBOOT_PBL obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c deleted file mode 100644 index 2315793010..0000000000 --- a/board/freescale/common/sgmii_riser.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Freescale SGMII Riser Card - * - * This driver supports the SGMII Riser card found on the - * "DS" style of development board from Freescale. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <net.h> -#include <linux/libfdt.h> -#include <tsec.h> -#include <fdt_support.h> - -void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) -{ - int i; - - for (i = 0; i < num; i++) - if (tsec_info[i].flags & TSEC_SGMII) - tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET; -} - -void fsl_sgmii_riser_fdt_fixup(void *fdt) -{ - struct eth_device *dev; - int node; - int mdio_node; - int i = -1; - int etsec_num = 0; - - node = fdt_path_offset(fdt, "/aliases"); - if (node < 0) - return; - - while ((dev = eth_get_dev_by_index(++i)) != NULL) { - struct tsec_private *priv; - int phy_node; - int enet_node; - uint32_t ph; - char sgmii_phy[16]; - char enet[16]; - const u32 *phyh; - const char *model; - const char *path; - - if (!strstr(dev->name, "eTSEC")) - continue; - - priv = dev->priv; - if (!(priv->flags & TSEC_SGMII)) { - etsec_num++; - continue; - } - - mdio_node = fdt_node_offset_by_compatible(fdt, -1, - "fsl,gianfar-mdio"); - if (mdio_node < 0) - return; - - sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num); - phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy); - if (phy_node > 0) { - fdt_increase_size(fdt, 32); - ph = fdt_create_phandle(fdt, phy_node); - if (!ph) - continue; - } - - sprintf(enet, "ethernet%d", etsec_num++); - path = fdt_getprop(fdt, node, enet, NULL); - if (!path) { - debug("No alias for %s\n", enet); - continue; - } - - enet_node = fdt_path_offset(fdt, path); - if (enet_node < 0) - continue; - - model = fdt_getprop(fdt, enet_node, "model", NULL); - - /* - * We only want to do this to eTSECs. On some platforms - * there are more than one type of gianfar-style ethernet - * controller, and as we are creating an implicit connection - * between ethernet nodes and eTSEC devices, it is best to - * make the connection use as much explicit information - * as exists. - */ - if (!strstr(model, "TSEC")) - continue; - - if (phy_node < 0) { - /* - * This part is only for old device tree without - * sgmii_phy nodes. It's kept just for compatible - * reason. Soon to be deprecated if all device tree - * get updated. - */ - phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL); - if (!phyh) - continue; - - phy_node = fdt_node_offset_by_phandle(fdt, - fdt32_to_cpu(*phyh)); - - priv = dev->priv; - - if (priv->flags & TSEC_SGMII) - fdt_setprop_cell(fdt, phy_node, "reg", - priv->phyaddr); - } else { - fdt_setprop(fdt, enet_node, "phy-handle", &ph, - sizeof(ph)); - fdt_setprop_string(fdt, enet_node, - "phy-connection-type", - phy_string_for_interface( - PHY_INTERFACE_MODE_SGMII)); - } - } -} diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig deleted file mode 100644 index dbcd1afcba..0000000000 --- a/board/freescale/corenet_ds/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -if TARGET_P3041DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P3041DS" - -endif - -if TARGET_P4080DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P4080DS" - -endif - -if TARGET_P5040DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P5040DS" - -endif diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS deleted file mode 100644 index f0da86a34c..0000000000 --- a/board/freescale/corenet_ds/MAINTAINERS +++ /dev/null @@ -1,21 +0,0 @@ -CORENET_DS BOARD -#M: - -S: Maintained -F: board/freescale/corenet_ds/ -F: include/configs/P3041DS.h -F: configs/P3041DS_defconfig -F: configs/P3041DS_NAND_defconfig -F: configs/P3041DS_SDCARD_defconfig -F: configs/P3041DS_SPIFLASH_defconfig -F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P4080DS.h -F: configs/P4080DS_defconfig -F: configs/P4080DS_SDCARD_defconfig -F: configs/P4080DS_SPIFLASH_defconfig -F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P5040DS.h -F: configs/P5040DS_defconfig -F: configs/P5040DS_NAND_defconfig -F: configs/P5040DS_SDCARD_defconfig -F: configs/P5040DS_SPIFLASH_defconfig -F: configs/P5040DS_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile deleted file mode 100644 index 4d62fc9ce1..0000000000 --- a/board/freescale/corenet_ds/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += corenet_ds.o -obj-y += ddr.o -obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o -obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o -obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o -obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o -obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o -obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c deleted file mode 100644 index 3a83e65f2f..0000000000 --- a/board/freescale/corenet_ds/corenet_ds.c +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <fdt_support.h> -#include <image.h> -#include <init.h> -#include <netdev.h> -#include <asm/global_data.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> - -#include "../common/ngpixis.h" -#include "corenet_ds.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - unsigned int i; -#endif - static const char * const freq[] = {"100", "125", "156.25", "212.5" }; - - printf("Board: %sDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - - sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); - sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - - /* Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - - printf("Bank%u=%sMhz ", i+1, freq[clock]); - } -#ifdef CONFIG_TARGET_P5040DS - /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ - sw = in_8(&PIXIS_SW(9)); - printf("Bank4=%sMhz ", freq[sw & 3]); -#endif - puts("\n"); -#else - sw = in_8(&PIXIS_SW(3)); - /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ - /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ - /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ - printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); - printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); - printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); -#endif - - return 0; -} - -int board_early_init_f(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* - * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 - * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce - * the noise introduced by these unterminated and unused clock pairs. - */ - setbits_be32(&gur->ddrclkdr, 0x001B001B); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - - return 0; -} - -#define NUM_SRDS_BANKS 3 - -int misc_init_r(void) -{ - serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[NUM_SRDS_BANKS]; - unsigned int i; - u8 sw; - -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - default: - printf("Warning: SDREFCLK%u switch setting of '11' is " - "unsupported\n", i + 1); - break; - } - } -#else - /* Warn if the expected SERDES reference clocks don't match the - * actual reference clocks. This needs to be done after calling - * p4080_erratum_serdes8(), since that function may modify the clocks. - */ - sw = in_8(&PIXIS_SW(3)); - actual[0] = (sw & 0x40) ? - SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; - actual[1] = (sw & 0x20) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; - actual[2] = (sw & 0x10) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; -#endif - - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES bank %u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} diff --git a/board/freescale/corenet_ds/corenet_ds.h b/board/freescale/corenet_ds/corenet_ds.h deleted file mode 100644 index 84e5c4a2de..0000000000 --- a/board/freescale/corenet_ds/corenet_ds.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); - -#endif diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c deleted file mode 100644 index 2c440673e7..0000000000 --- a/board/freescale/corenet_ds/ddr.c +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <init.h> -#include <log.h> -#include <vsprintf.h> -#include <asm/global_data.h> -#include <asm/mmu.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/fsl_law.h> - -DECLARE_GLOBAL_DATA_PTR; - - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -extern fixed_ddr_parm_t fixed_ddr_parm_0[]; -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) -extern fixed_ddr_parm_t fixed_ddr_parm_1[]; -#endif - -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - unsigned int lawbar1_target_id; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_1[i].ddr_settings, - sizeof(ddr_cfg_regs)); - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); -#endif - - /* - * setup laws for DDR. If not interleaving, presuming half memory on - * DDR1 and the other half on DDR2 - */ - if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - LAW_TRGT_IF_DDR_INTRLV) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - } else { -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - /* We require both controllers have identical DIMMs */ - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - lawbar1_target_id = LAW_TRGT_IF_DDR_2; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#else - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#endif - } - return ddr_size; -} - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 5, 6, 0xff, 2, 0}, - {2, 1050, 5, 7, 0xff, 2, 0}, - {2, 1250, 4, 6, 0xff, 2, 0}, - {2, 1350, 5, 7, 0xff, 2, 0}, - {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 1250, 4, 6, 0xff, 2, 0}, - {1, 1335, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. The center values are good - * for both slots. We use identical speed tables for them. In future use, if - * DIMMs have fewer center values that require two separated tables, copy the - * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 4, 6, 0xff, 2, 0}, - {2, 1050, 4, 7, 0xff, 2, 0}, - {2, 1666, 4, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 60 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN; -} - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing...."); - - if (fsl_use_spd()) { - puts("using SPD\n"); - dram_size = fsl_ddr_sdram(); - } else { - puts("using fixed parameters\n"); - dram_size = fixed_sdram(); - } - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c deleted file mode 100644 index a27e905ace..0000000000 --- a/board/freescale/corenet_ds/eth_hydra.c +++ /dev/null @@ -1,526 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Timur Tabi <timur@freescale.com> - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHY is provided via the XAUI riser card. Since there is only one - * Fman device on a P3041 and P5020, we only support one SGMII card and one - * RGMII card. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fdt_support.h> -#include <fsl_dtsec.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x78 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -#define PHY_BASE_ADDR 0x00 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int hydra_mdio_reset(struct mii_dev *bus) -{ - struct hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = hydra_mdio_read; - bus->write = hydra_mdio_write; - bus->reset = hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given an alias or a path for a node, set the mux value of that node. - * - * If 'alias' is not a valid alias, then it is treated as a full path to the - * node. No error checking is performed. - * - * This function is normally called to set the fsl,hydra-mdio-muxval property - * of a virtual MDIO node. - */ -static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "reg", - &mux, sizeof(mux), 1); - do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", - &mux, sizeof(mux), 1); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - * Note that this code would be cleaner if had a function called - * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] - * array. That's because all we're doing is figuring out the PHY address for - * a given Fman MAC and writing it to the device tree. Well, we already did - * the hard work to figure that out in board_eth_init(), so it's silly to - * repeat that here. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; - char phy[16]; - - if (port == FM1_10GEC1) { - /* XAUI */ - int lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - return; - } - - if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) { - /* RGMII */ - /* The RGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - return; - } - - /* If it's not RGMII or XGMII, it must be SGMII */ - if (mux) { - /* The SGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 - -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - * - * For SGMII, we also need to set the mux value in the node. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - unsigned int i; - int lane; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - fdt_status_okay_by_alias(fdt, "emi1_sgmii"); - /* Also set the MUX value */ - fdt_set_mdio_mux(fdt, "emi1_sgmii", - mdio_mux[i].val); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "emi1_rgmii"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) - fdt_status_okay_by_alias(fdt, "emi2_xgmii"); -#endif -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - switch (slot) { - case 1: - /* Always DTSEC5 on Bank 3 */ - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - hydra_mdio_set_mux("HYDRA_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * If DTSEC4 is RGMII, then it's routed via via EC1 to - * the first on-board RGMII port. If DTSEC5 is RGMII, - * then it's routed via via EC2 to the second on-board - * RGMII port. The other DTSECs cannot be routed to - * RGMII. - */ - fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - hydra_mdio_set_mux("HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); - set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot == 1) { - /* XAUI card is in slot 1 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT1); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - } else { - /* XAUI card is in slot 2 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT2); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - } - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c deleted file mode 100644 index df5a69bcba..0000000000 --- a/board/freescale/corenet_ds/eth_p4080.c +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <linux/delay.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" -#include <fsl_dtsec.h> - -#define EMI_NONE 0xffffffff -#define EMI_MASK 0xf0000000 -#define EMI1_RGMII 0x0 -#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ -#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ -#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ -#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ -#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ -#define EMI1_MASK 0xc0000000 -#define EMI2_MASK 0x30000000 - -#define PHY_BASE_ADDR 0x00 -#define PHY_BASE_ADDR_SLOT5 0x10 - -static int mdio_mux[NUM_FM_PORTS]; - -static char *mdio_names[16] = { - "P4080DS_MDIO0", - "P4080DS_MDIO1", - NULL, - "P4080DS_MDIO3", - "P4080DS_MDIO4", - NULL, NULL, NULL, - "P4080DS_MDIO8", - NULL, NULL, NULL, - "P4080DS_MDIO12", - NULL, NULL, NULL, -}; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot. - */ -static u8 lane_to_slot[] = { - 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5 -}; - -static char *p4080ds_mdio_name_for_muxval(u32 muxval) -{ - return mdio_names[(muxval & EMI_MASK) >> 28]; -} - -struct mii_dev *mii_dev_for_muxval(u32 muxval) -{ - struct mii_dev *bus; - char *name = p4080ds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - if (phydev->drv->uid == PHY_UID_TN2020) { - unsigned long timeout = 1 * 1000; /* 1 seconds */ - enum srds_prtcl device; - - /* - * Wait for the XAUI to come out of reset. This is when it - * starts transmitting alignment signals. - */ - while (--timeout) { - int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); - if (reg < 0) { - printf("TN2020: Error reading from PHY at " - "address %u\n", phydev->addr); - break; - } - /* - * Note that we've never actually seen - * MDIO_CTRL1_RESET set to 1. - */ - if ((reg & MDIO_CTRL1_RESET) == 0) - break; - udelay(1000); - } - - if (!timeout) { - printf("TN2020: Timeout waiting for PHY at address %u " - " to reset.\n", phydev->addr); - } - - switch (phydev->addr) { - case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: - device = XAUI_FM1; - break; - case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: - device = XAUI_FM2; - break; - default: - device = NONE; - } - - serdes_reset_rx(device); - } - - return 0; -} -#endif - -struct p4080ds_mdio { - u32 muxval; - struct mii_dev *realbus; -}; - -static void p4080ds_mux_mdio(u32 muxval) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); - gpioval |= muxval; - - out_be32(&pgpio->gpdat, gpioval); -} - -static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int p4080ds_mdio_reset(struct mii_dev *bus) -{ - struct p4080ds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int p4080ds_mdio_init(char *realbusname, u32 muxval) -{ - struct p4080ds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate P4080DS MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate P4080DS private data\n"); - free(bus); - return -1; - } - - bus->read = p4080ds_mdio_read; - bus->write = p4080ds_mdio_write; - bus->reset = p4080ds_mdio_reset; - sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) -{ - if (mdio_mux[port] == EMI1_RGMII) - fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); - - if (mdio_mux[port] == EMI1_SLOT3) { - int idx = port - FM2_DTSEC1 + 5; - char phy[16]; - - sprintf(phy, "phy%d_slot3", idx); - - fdt_set_phy_handle(blob, prop, pa, phy); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - /* - * P4080DS can be configured in many different ways, supporting a number - * of combinations of ethernet devices and phy types. In order to - * have just one device tree for all of those configurations, we fix up - * the tree here. By default, the device tree configures FM1 and FM2 - * for SGMII, and configures XAUI on both 10G interfaces. So we have - * a number of different variables to track: - * - * 1) Whether the device is configured at all. Whichever devices are - * not enabled should be disabled by setting the "status" property - * to "disabled". - * 2) What the PHY interface is. If this is an RGMII connection, - * we should change the "phy-connection-type" property to - * "rgmii" - * 3) Which PHY is being used. Because the MDIO buses are muxed, - * we need to redirect the "phy-handle" property to point at the - * PHY on the right slot/bus. - */ - - /* We've got six MDIO nodes that may or may not need to exist */ - fdt_status_disabled_by_alias(fdt, "emi1_slot3"); - fdt_status_disabled_by_alias(fdt, "emi1_slot4"); - fdt_status_disabled_by_alias(fdt, "emi1_slot5"); - fdt_status_disabled_by_alias(fdt, "emi2_slot4"); - fdt_status_disabled_by_alias(fdt, "emi2_slot5"); - - for (i = 0; i < NUM_FM_PORTS; i++) { - switch (mdio_mux[i]) { - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); - break; - case EMI1_SLOT5: - fdt_status_okay_by_alias(fdt, "emi1_slot5"); - break; - case EMI2_SLOT4: - fdt_status_okay_by_alias(fdt, "emi2_slot4"); - break; - case EMI2_SLOT5: - fdt_status_okay_by_alias(fdt, "emi2_slot5"); - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - int i; - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - struct mii_dev *bus; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - /* The first 4 GPIOs are outputs to control MDIO bus muxing */ - out_be32(&pgpio->gpdir, EMI_MASK); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the 6 muxing front-ends to the MDIO buses */ - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5); - - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); -#endif - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - bus = mii_dev_for_muxval(EMI1_SLOT5); - set_sgmii_phy(bus, FM1_DTSEC1, - CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5); - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - int idx = i - FM1_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - bus = mii_dev_for_muxval(EMI1_SLOT3); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - bus = mii_dev_for_muxval(EMI1_SLOT4); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { - int idx = i - FM2_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM2 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } -#endif - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c deleted file mode 100644 index 55bac0f761..0000000000 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ /dev/null @@ -1,783 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans - * and 5 1G interfaces and 10G interface per FMan. Based on the options in - * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman's MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include <common.h> -#include <log.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fdt_support.h> -#include <fsl_dtsec.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x70 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_SLOT3 0x60 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -/* SGMII */ -#define PHY_BASE_ADDR 0x00 -#define REGNUM 0x00 -#define PORT_NUM_FM1 0x04 -#define PORT_NUM_FM2 0x02 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -static struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void super_hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct super_hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int super_hydra_mdio_reset(struct mii_dev *bus) -{ - struct super_hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct super_hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int super_hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct super_hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = super_hydra_mdio_read; - bus->write = super_hydra_mdio_write; - bus->reset = super_hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - enum srds_prtcl device; - int lane, slot, phy; - char alias[32]; - - /* RGMII and XGMII are already mapped correctly in the DTS */ - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - device = serdes_device_from_fm_port(port); - lane = serdes_get_first_lane(device); - slot = lane_to_slot[lane]; - phy = fm_info_get_phy_address(port); - - sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 -#define PIXIS_SW11_LANE_9_SEL 0x04 -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - /* SW11 appears in the programming model as SW9 */ - u8 sw11 = in_8(&PIXIS_SW(9)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - enum fm_port i; - int lane, slot; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } - -#if CONFIG_SYS_NUM_FMAN == 2 - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ -#endif /* CONFIG_FMAN_ENET */ -} - -/* - * Mapping of SerDes Protocol to MDIO MUX value and PHY address. - * - * Fman 1: - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 2 1c | 2 1d | 2 1e | 2 1f - * 0x01 | | 6 1c | - * 0x02 | | 3 1c | 3 1d - * 0x03 2 1c | 2 1d | 2 1e | 2 1f - * 0x04 2 1c | 2 1d | 2 1e | 2 1f - * 0x05 | | 3 1c | 3 1d - * 0x06 2 1c | 2 1d | 2 1e | 2 1f - * 0x07 | | 6 1c | - * 0x11 2 1c | 2 1d | 2 1e | 2 1f - * 0x2a 2 | | 2 1e | 2 1f - * 0x34 6 1c | 6 1d | 4 1e | 4 1f - * 0x35 | | 3 1c | 3 1d - * 0x36 6 1c | 6 1d | 4 1e | 4 1f - * | | | - * Fman 2: | | | - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * EMI1 | EMI1 | EMI1 | EMI1 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 | | 6 1c | 6 1d - * 0x01 | | | - * 0x02 | | 6 1c | 6 1d - * 0x03 3 1c | 3 1d | 6 1c | 6 1d - * 0x04 3 1c | 3 1d | 6 1c | 6 1d - * 0x05 | | 6 1c | 6 1d - * 0x06 | | 6 1c | 6 1d - * 0x07 | | | - * 0x11 | | | - * 0x2a | | | - * 0x34 | | | - * 0x35 | | | - * 0x36 | | | - */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - int qsgmii; - int phy_real_addr; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_RGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM1_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM2_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM3_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM1_TGEC_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM2_TGEC_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); -#endif - - switch (srds_prtcl) { - case 0: - case 3: - case 4: - case 6: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - case 1: - case 2: - case 5: - case 7: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - break; - default: - printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM1@DTSEC%u is RGMII at address %u\n", - idx + 1, 0); - fm_info_set_phy_address(i, 0); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); - qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); - - if (qsgmii) { - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { - if (fm_info_get_enet_if(i) == - PHY_INTERFACE_MODE_SGMII) { - phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; - fm_info_set_phy_address(i, phy_real_addr); - } - } - switch (srds_prtcl) { - case 0x00: - case 0x03: - case 0x04: - case 0x06: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); - break; - case 0x01: - case 0x02: - case 0x05: - case 0x07: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); - break; - default: - break; - } - } - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM2@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM3_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM3_SGMII_MDIO")); - } else { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM2_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM2_SGMII_MDIO")); - } - - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM2@DTSEC%u is RGMII at address %u\n", - idx + 1, 1); - fm_info_set_phy_address(i, 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman2: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM2_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); - -#endif - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c deleted file mode 100644 index c62d85ccc0..0000000000 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c deleted file mode 100644 index 9839eaceaf..0000000000 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 -#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 -#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 -#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 -#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 -#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 -#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 -#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF -#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 -#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 -#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 -#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce -#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 -#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 -#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 -#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 -#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {850, 950, &ddr_cfg_regs_900}, - {950, 1050, &ddr_cfg_regs_1000}, - {1050, 1250, &ddr_cfg_regs_1200}, - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {750, 850, &ddr_cfg_regs_800_2nd}, - {850, 950, &ddr_cfg_regs_900_2nd}, - {950, 1050, &ddr_cfg_regs_1000_2nd}, - {1050, 1250, &ddr_cfg_regs_1200_2nd}, - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c deleted file mode 100644 index 112733be78..0000000000 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg deleted file mode 100644 index 8813156219..0000000000 --- a/board/freescale/corenet_ds/rcw_p3041ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P3041DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -12600000 00000000 241C0000 00000000 -D8984A01 03002000 58000000 41000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg deleted file mode 100644 index 6a26339599..0000000000 --- a/board/freescale/corenet_ds/rcw_p4080ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P4080DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -105a0000 00000000 1e1e181e 0000cccc -58400000 3c3c2000 58000000 e1000000 -00000000 00000000 00000000 008b6000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg deleted file mode 100644 index 82fa7417d9..0000000000 --- a/board/freescale/corenet_ds/rcw_p5040ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P5040DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -0c580000 00000000 22121200 00000000 -089c4400 00283000 58000000 61000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 5ab03b3340..3ed6100b7c 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -109,44 +109,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_TSEC_ENET -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index 65030342be..8cbf33fa0c 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -6,5 +6,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o -obj-y += eth.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c deleted file mode 100644 index a9f162b974..0000000000 --- a/board/freescale/ls1021aqds/eth.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * This file handles the board muxing between the RGMII/SGMII PHYs on - * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb - * ports. The SGMII PHYs are provided by the standard Freescale four-port - * SGMII riser card. - * - * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends - * on which port is used. The value for SGMII depends on which slot the riser - * is inserted in. - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/arch/fsl_serdes.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <malloc.h> - -#include "../common/sgmii_riser.h" -#include "../common/qixis.h" - -#define EMI1_MASK 0x1f -#define EMI1_RGMII0 1 -#define EMI1_RGMII1 2 -#define EMI1_RGMII2 3 -#define EMI1_SGMII1 0x1c -#define EMI1_SGMII2 0x1d - -struct ls1021a_mdio { - struct mii_dev *realbus; -}; - -static void ls1021a_mux_mdio(int addr) -{ - u8 brdcfg4; - - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= EMI1_MASK; - - switch (addr) { - case EMI1_RGMII0: - brdcfg4 |= 0; - break; - case EMI1_RGMII1: - brdcfg4 |= 0x20; - break; - case EMI1_RGMII2: - brdcfg4 |= 0x40; - break; - case EMI1_SGMII1: - brdcfg4 |= 0x60; - break; - case EMI1_SGMII2: - brdcfg4 |= 0x80; - break; - default: - brdcfg4 |= 0xa0; - break; - } - - QIXIS_WRITE(brdcfg[4], brdcfg4); -} - -static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1021a_mdio *priv = bus->priv; - - ls1021a_mux_mdio(addr); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1021a_mdio *priv = bus->priv; - - ls1021a_mux_mdio(addr); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int ls1021a_mdio_reset(struct mii_dev *bus) -{ - struct ls1021a_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1021a_mdio_init(char *realbusname, char *fakebusname) -{ - struct ls1021a_mdio *lsmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate LS102xA MDIO bus\n"); - return -1; - } - - lsmdio = malloc(sizeof(*lsmdio)); - if (!lsmdio) { - printf("Failed to allocate LS102xA private data\n"); - free(bus); - return -1; - } - - bus->read = ls1021a_mdio_read; - bus->write = ls1021a_mdio_write; - bus->reset = ls1021a_mdio_reset; - strcpy(bus->name, fakebusname); - - lsmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!lsmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(lsmdio); - return -1; - } - - bus->priv = lsmdio; - - return mdio_register(bus); -} - -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[3]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; - } else { - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; - } else { - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_init(tsec_info, num); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - /* Register the virtual MDIO front-ends */ - ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO"); - ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO"); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index e156ba0104..7bfbacde4f 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -30,8 +30,6 @@ #define EMI1_SLOT4 5 #define EMI2 6 -static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1043AQDS_MDIO_RGMII1", "LS1043AQDS_MDIO_RGMII2", @@ -43,7 +41,11 @@ static const char * const mdio_names[] = { }; /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 2, 3, 4}; +#endif static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) { @@ -75,6 +77,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } +#ifdef CONFIG_FMAN_ENET struct ls1043aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -296,7 +299,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; @@ -493,7 +495,7 @@ int board_eth_init(struct bd_info *bis) } cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); } +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 13359f947b..7ac2c1ae90 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -556,10 +556,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 8233f5461e..13207a1a37 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -27,8 +27,6 @@ #define EMI1_SLOT2 3 #define EMI1_SLOT4 4 -static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1046AQDS_MDIO_RGMII1", "LS1046AQDS_MDIO_RGMII2", @@ -39,7 +37,11 @@ static const char * const mdio_names[] = { }; /* Map SerDes 1 & 2 lanes to default slot. */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; +#endif static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) { @@ -71,6 +73,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } +#ifdef CONFIG_FMAN_ENET struct ls1046aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -263,7 +266,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -423,7 +425,7 @@ int board_eth_init(struct bd_info *bis) } cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); } +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index e5b5441e2c..aa6e30e6b2 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -439,10 +439,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index dac821f1ac..8886d8be33 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -169,7 +169,8 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } -void configure_rgmii(void) +#ifndef CONFIG_DM_ETH +static void configure_rgmii(void) { unsigned short temp; @@ -248,3 +249,4 @@ int board_eth_init(struct bd_info *bis) return pci_eth_init(bis); } +#endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS index c565010ccf..f20baa91c6 100644 --- a/board/freescale/mx28evk/MAINTAINERS +++ b/board/freescale/mx28evk/MAINTAINERS @@ -5,6 +5,3 @@ F: board/freescale/mx28evk/ F: arch/arm/dts/imx28-evk.dts F: include/configs/mx28evk.h F: configs/mx28evk_defconfig -F: configs/mx28evk_auart_console_defconfig -F: configs/mx28evk_nand_defconfig -F: configs/mx28evk_spi_defconfig diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/p2041rdb/pbi.cfg index 75dfc32162..75dfc32162 100644 --- a/board/freescale/corenet_ds/pbi.cfg +++ b/board/freescale/p2041rdb/pbi.cfg diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/p2041rdb/rcw_p2041rdb.cfg index 8df19dd3fe..8df19dd3fe 100644 --- a/board/freescale/corenet_ds/rcw_p2041rdb.cfg +++ b/board/freescale/p2041rdb/rcw_p2041rdb.cfg diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 0932f62b9b..6c5e6fbbcb 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -88,62 +88,6 @@ int onenand_board_init(struct mtd_info *mtd) return 1; } -#if defined(CONFIG_CMD_NET) -static void reset_net_chip(int gpio) -{ - if (!gpio_request(gpio, "eth nrst")) { - gpio_direction_output(gpio, 1); - udelay(1); - gpio_set_value(gpio, 0); - udelay(40); - gpio_set_value(gpio, 1); - mdelay(10); - } -} - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - }; - - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - reset_net_chip(64); -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} -#else -static inline void setup_net_chip(void) {} -#endif - #ifdef CONFIG_OF_BOARD_SETUP static int ft_enable_by_compatible(void *blob, char *compat, int enable) { @@ -234,8 +178,6 @@ int misc_init_r(void) OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, OMAP34XX_CTRL_WKUP_CTRL); - setup_net_chip(); - omap_die_id_display(); set_led(); diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index 8247ae39d3..ef3c62b9de 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -61,25 +61,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy endif -if TARGET_KMTEGR1 - -config SYS_BOARD - default "km83xx" - -config SYS_VENDOR - default "keymile" - -config SYS_CONFIG_NAME - default "kmtegr1" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_MPC8309 - imply CMD_CRAMFS - imply FS_CRAMFS - -endif - if TARGET_TUXX1 config SYS_BOARD diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 9fd5a8500d..ac1f8cbd88 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -10,10 +10,8 @@ F: include/configs/tuxx1.h F: configs/kmopti2_defconfig F: configs/kmsupx5_defconfig F: configs/kmtepr2_defconfig -F: configs/kmtegr1_defconfig F: configs/tuge1_defconfig F: configs/tuxx1_defconfig -F: arch/powerpc/dts/km8309-uboot.dtsi F: arch/powerpc/dts/km8321-uboot.dtsi F: arch/powerpc/dts/km8321.dtsi F: arch/powerpc/dts/km836x-uboot.dtsi @@ -25,7 +23,6 @@ F: arch/powerpc/dts/kmeter1.dts F: arch/powerpc/dts/kmopti2.dts F: arch/powerpc/dts/kmsupc5.dts F: arch/powerpc/dts/kmsupm5.dts -F: arch/powerpc/dts/kmtegr1.dts F: arch/powerpc/dts/kmtepr2.dts F: arch/powerpc/dts/kmtuge1.dts F: arch/powerpc/dts/kmtuxa1.dts diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig deleted file mode 100644 index f163efd989..0000000000 --- a/board/kmc/kzm9g/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KZM9G - -config SYS_BOARD - default "kzm9g" - -config SYS_VENDOR - default "kmc" - -config SYS_CONFIG_NAME - default "kzm9g" - -endif diff --git a/board/kmc/kzm9g/MAINTAINERS b/board/kmc/kzm9g/MAINTAINERS deleted file mode 100644 index 411efd1e31..0000000000 --- a/board/kmc/kzm9g/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KZM9G BOARD -M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -M: Tetsuyuki Kobayashi <koba@kmckk.co.jp> -S: Maintained -F: board/kmc/kzm9g/ -F: include/configs/kzm9g.h -F: configs/kzm9g_defconfig diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile deleted file mode 100644 index aebe9f3546..0000000000 --- a/board/kmc/kzm9g/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -# (C) Copyright 2012 Renesas Solutions Corp. - -obj-y := kzm9g.o diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c deleted file mode 100644 index dccf4691af..0000000000 --- a/board/kmc/kzm9g/kzm9g.c +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CS0BCR_D (0x06C00400) -#define CS4BCR_D (0x16c90400) -#define CS0WCR_D (0x55062C42) -#define CS4WCR_D (0x1e071dc3) - -#define CMNCR_BROMMD0 (1 << 21) -#define CMNCR_BROMMD1 (1 << 22) -#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) -#define VCLKCR1_D (0x27) - -#define SMSTPCR1_CMT0 (1 << 24) -#define SMSTPCR1_I2C0 (1 << 16) -#define SMSTPCR3_USB (1 << 22) -#define SMSTPCR3_I2C1 (1 << 23) - -#define PORT32CR (0xE6051020) -#define PORT33CR (0xE6051021) -#define PORT34CR (0xE6051022) -#define PORT35CR (0xE6051023) - -static int cmp_loop(u32 *addr, u32 data, u32 cmp) -{ - int err = -1; - int timeout = 100; - u32 value; - - while (timeout > 0) { - value = readl(addr); - if ((value & data) == cmp) { - err = 0; - break; - } - timeout--; - } - - return err; -} - -/* SBSC Init function */ -static void sbsc_init(struct sh73a0_sbsc *sbsc) -{ - writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); - writel(0x5, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0xacc90159, &sbsc->sdcr0); - writel(0x00010059, &sbsc->sdcr1); - writel(0x50874114, &sbsc->sdwcrc0); - writel(0x33199b37, &sbsc->sdwcrc1); - writel(0x008f2313, &sbsc->sdwcrc2); - writel(0x31020707, &sbsc->sdwcr00); - writel(0x0017040a, &sbsc->sdwcr01); - writel(0x31020707, &sbsc->sdwcr10); - writel(0x0017040a, &sbsc->sdwcr11); - writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */ - writel(0x30000000, &sbsc->sdwcr2); - - writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); - cmp_loop(&sbsc->sdpcr, 0x80, 0x80); - - writel(0x00002710, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000003f, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x000001f4, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000ff0a, &sbsc->sdmracr0); - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) - writel(0x0, SDMRA3A); - else - writel(0x0, SDMRA3B); - - writel(0x00000032, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1A); - writel(0x0, SDMRA2A); - } else { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1B); - writel(0x0, SDMRA2B); - } - - writel(0x88800004, &sbsc->sdmrtmpcr); - writel(0x00000004, &sbsc->sdmrtmpmsk); - writel(0xa55a0032, &sbsc->rtcor); - writel(0xa55a000c, &sbsc->rtcorh); - writel(0xa55a2048, &sbsc->rtcsr); - writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); - writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); - writel(0xfff20000, &sbsc->zqccr); - - /* SCBS2 only */ - if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { - writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); - writel(0xa5390000, &sbsc->dphycnt1); - writel(0x00001200, &sbsc->dphycnt0); - writel(0x07ce0000, &sbsc->dphycnt1); - writel(0x00001247, &sbsc->dphycnt0); - cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); - writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); - } -} - -void s_init(void) -{ - struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; - struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; - struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; - struct sh73a0_hpb_bscr *hpb_bscr = - (struct sh73a0_hpb_bscr *)HPBSCR_BASE; - - /* Watchdog init */ - writew(0xA507, &rwdt->rwtcsra0); - - /* Secure control register Init */ - #define LIFEC_SEC_SRC_BIT (1 << 15) - writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); - - clrbits_le32(&cpg->smstpcr3, (1 << 15)); - clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); - clrbits_le32(&cpg->smstpcr2, (1 << 18)); - clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); - writel(0x0, &cpg->pllecr); - - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x96235880, &cpg->frqcrb); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0xB, &cpg->flckcr); - clrbits_le32(&cpg->smstpcr0, (1 << 1)); - - clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); - writel(0x0514, &hpb_bscr->smgpiotime); - writel(0x0514, &hpb_bscr->smcmt2time); - writel(0x0514, &hpb_bscr->smcpgtime); - writel(0x0514, &hpb_bscr->smsysctime); - - writel(0x00092000, &cpg->dvfscr4); - writel(0x000000DC, &cpg->dvfscr5); - writel(0x0, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - - /* FRQCR Init */ - writel(0x0012453C, &cpg->frqcra); - writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */ - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - writel(0x00000B0B, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - /* Clock Init */ - writel(0x00000003, PCLKCR); - writel(0x0000012F, &cpg->vclkcr1); - writel(0x00000119, &cpg->vclkcr2); - writel(0x00000119, &cpg->vclkcr3); - writel(0x00000002, &cpg->zbckcr); - writel(0x00000005, &cpg->flckcr); - writel(0x00000080, &cpg->sd0ckcr); - writel(0x00000080, &cpg->sd1ckcr); - writel(0x00000080, &cpg->sd2ckcr); - writel(0x0000003F, &cpg->fsiackcr); - writel(0x0000003F, &cpg->fsibckcr); - writel(0x00000080, &cpg->subckcr); - writel(0x0000000B, &cpg->spuackcr); - writel(0x0000000B, &cpg->spuvckcr); - writel(0x0000013F, &cpg->msuckcr); - writel(0x00000080, &cpg->hsickcr); - writel(0x0000003F, &cpg->mfck1cr); - writel(0x0000003F, &cpg->mfck2cr); - writel(0x00000107, &cpg->dsitckcr); - writel(0x00000313, &cpg->dsi0pckcr); - writel(0x0000130D, &cpg->dsi1pckcr); - writel(0x2A800E0E, &cpg->dsi0phycr); - writel(0x1E000000, &cpg->pll0cr); - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x27000080, &cpg->pll2cr); - writel(0x1D000000, &cpg->pll3cr); - writel(0x00080000, &cpg->pll0stpcr); - writel(0x000120C0, &cpg->pll1stpcr); - writel(0x00012000, &cpg->pll2stpcr); - writel(0x00000030, &cpg->pll3stpcr); - - writel(0x0000000B, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); - - writel(0x000120F0, &cpg->dvfscr3); - writel(0x00000020, &cpg->mpmode); - writel(0x0000028A, &cpg->vrefcr); - writel(0xE4628087, &cpg->rmstpcr0); - writel(0xFFFFFFFF, &cpg->rmstpcr1); - writel(0x53FFFFFF, &cpg->rmstpcr2); - writel(0xFFFFFFFF, &cpg->rmstpcr3); - writel(0x00800D3D, &cpg->rmstpcr4); - writel(0xFFFFF3FF, &cpg->rmstpcr5); - writel(0x00000000, &cpg->smstpcr2); - writel(0x00040000, &cpg_srcr->srcr2); - - clrbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x00000800, 0x0); - - writel(0x00000001, &hpb->hpbctrl6); - cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); - - writel(0x00001414, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - writel(0x1d000000, &cpg->pll3cr); - setbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x800, 0x800); - - /* SBSC1 Init*/ - sbsc_init(sbsc1); - - /* SBSC2 Init*/ - sbsc_init(sbsc2); - - writel(0x00000b0b, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - writel(0xfffffffc, &cpg->cpgxxcs4); -} - -int board_early_init_f(void) -{ - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - - writel(CS0BCR_D, &bsc->cs0bcr); - writel(CS4BCR_D, &bsc->cs4bcr); - writel(CS0WCR_D, &bsc->cs0wcr); - writel(CS4WCR_D, &bsc->cs4wcr); - - clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); - - clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - writel(VCLKCR1_D, &cpg->vclkcr1); - - /* Setup SCIF4 / workaround */ - writeb(0x12, PORT32CR); - writeb(0x22, PORT33CR); - writeb(0x12, PORT34CR); - writeb(0x22, PORT35CR); - - return 0; -} - -void adjust_core_voltage(void) -{ - u8 data; - - data = 0x35; - i2c_set_bus_num(0); - i2c_write(0x40, 3, 1, &data, 1); -} - -int board_init(void) -{ - adjust_core_voltage(); - sh73a0_pinmux_init(); - - /* SCIFA 4 */ - gpio_request(GPIO_FN_SCIFA4_TXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); - gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); - - /* Ethernet/SMSC */ - gpio_request(GPIO_PORT224, NULL); - gpio_direction_input(GPIO_PORT224); - - /* SMSC/USB */ - gpio_request(GPIO_FN_CS4_, NULL); - - /* MMCIF */ - gpio_request(GPIO_FN_MMCCLK0, NULL); - gpio_request(GPIO_FN_MMCCMD0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_1_PU, NULL); - gpio_request(GPIO_FN_MMCD0_2_PU, NULL); - gpio_request(GPIO_FN_MMCD0_3_PU, NULL); - gpio_request(GPIO_FN_MMCD0_4_PU, NULL); - gpio_request(GPIO_FN_MMCD0_5_PU, NULL); - gpio_request(GPIO_FN_MMCD0_6_PU, NULL); - gpio_request(GPIO_FN_MMCD0_7_PU, NULL); - - /* SDHI */ - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICD0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request(GPIO_PORT15, NULL); - gpio_direction_output(GPIO_PORT15, 1); - - /* I2C */ - gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); - gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); - gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); - gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); - - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int ret = 0; -#ifdef CONFIG_SMC911X - ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return ret; -} - -void reset_cpu(void) -{ - /* Soft Power On Reset */ - writel((1 << 31), RESCNT2); -} diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index 9c4c5fdc4a..db1075a594 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -204,9 +204,6 @@ int board_eth_init(struct bd_info *bis) #ifdef CONFIG_USB_GADGET_ATMEL_USBA usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif #endif return rc; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 69ed715403..b944e44c1a 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -69,12 +69,3 @@ int checkboard(void) return 0; } #endif - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/warp/Kconfig b/board/warp/Kconfig deleted file mode 100644 index 9c2fc9df67..0000000000 --- a/board/warp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WARP - -config SYS_BOARD - default "warp" - -config SYS_CONFIG_NAME - default "warp" - -config IMX_CONFIG - default "board/warp/imximage.cfg" - -endif diff --git a/board/warp/MAINTAINERS b/board/warp/MAINTAINERS deleted file mode 100644 index ee2114d082..0000000000 --- a/board/warp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WaRP BOARD -M: Otavio Salvador <otavio@ossystems.com.br> -S: Maintained -F: board/warp/ -F: include/configs/warp.h -F: configs/warp_defconfig diff --git a/board/warp/Makefile b/board/warp/Makefile deleted file mode 100644 index 3a2373d7bf..0000000000 --- a/board/warp/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2014 O.S. Systems Software LTDA. -# Copyright (C) 2014 Kynetics LLC. -# Copyright (C) 2014 Revolution Robotics, Inc. - -obj-y := warp.o diff --git a/board/warp/README b/board/warp/README deleted file mode 100644 index 3cfd22ec76..0000000000 --- a/board/warp/README +++ /dev/null @@ -1,56 +0,0 @@ -How to Update U-Boot on Warp board ----------------------------------- - -Required software on the host PC: - -- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader - -- dfu-util: http://dfu-util.sourceforge.net/releases/ - -Build U-Boot for Warp: - -$ make mrproper -$ make warp_config -$ make - -This will generate the U-Boot binary called u-boot.imx. - -Put warp board in USB download mode - -Connect a USB to serial adapter between the host PC and warp - -Connect a USB cable between the OTG warp port and the host PC - -Open a terminal program such as minicom - -Copy u-boot.imx to the imx_usb_loader folder. - -Load u-boot.imx via USB: - -$ sudo ./imx_usb u-boot.imx - -Then U-Boot should start and its messages will appear in the console program. - -Use the default environment variables: - -=> env default -f -a -=> saveenv - -Run the DFU command: -=> dfu 0 mmc 0 - -Transfer u-boot.imx that will be flashed into the eMMC: - -$ sudo dfu-util -D u-boot.imx -a boot - -Then on the U-Boot prompt the following message should be seen after a -successful upgrade: - -#DOWNLOAD ... OK -Ctrl+C to exit ... - -Remove power from the warp board. - -Put warp board into normal boot mode - -Power up the board and the new updated U-Boot should boot from eMMC diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg deleted file mode 100644 index f6bc604c8b..0000000000 --- a/board/warp/imximage.cfg +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include <config.h> - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ - -BOOT_FROM sd - -/* - * Secure boot support - */ -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020c4018 0x00260324 - -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff - -DATA 4 0x020e0344 0x00003030 -DATA 4 0x020e0348 0x00003030 -DATA 4 0x020e034c 0x00003030 -DATA 4 0x020e0350 0x00003030 -DATA 4 0x020e030c 0x00000030 -DATA 4 0x020e0310 0x00000030 -DATA 4 0x020e0314 0x00000030 -DATA 4 0x020e0318 0x00000030 -DATA 4 0x020e0300 0x00000030 -DATA 4 0x020e031c 0x00000030 -DATA 4 0x020e0338 0x00000028 -DATA 4 0x020e0320 0x00000030 -DATA 4 0x020e032c 0x00000000 -DATA 4 0x020e033c 0x00000008 -DATA 4 0x020e0340 0x00000008 -DATA 4 0x020e05c4 0x00000030 -DATA 4 0x020e05cc 0x00000030 -DATA 4 0x020e05d4 0x00000030 -DATA 4 0x020e05d8 0x00000030 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05c8 0x00000030 -DATA 4 0x020e05b0 0x00020000 -DATA 4 0x020e05b4 0x00000000 -DATA 4 0x020e05c0 0x00020000 -DATA 4 0x020e05d0 0x00080000 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b085c 0x1b4700c7 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00400000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b082c 0xf3333333 -DATA 4 0x021b0830 0xf3333333 -DATA 4 0x021b0834 0xf3333333 -DATA 4 0x021b0838 0xf3333333 -DATA 4 0x021b0848 0x4241444a -DATA 4 0x021b0850 0x3030312b -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x00000000 -DATA 4 0x021b08c0 0x24911492 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b000c 0x33374133 -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0010 0x00100A82 -DATA 4 0x021b0014 0x00000093 -DATA 4 0x021b0018 0x00001688 -DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x009f0e10 -DATA 4 0x021b0038 0x00190778 -DATA 4 0x021b0008 0x00000000 -DATA 4 0x021b0040 0x0000004f -DATA 4 0x021b0000 0x83110000 -DATA 4 0x021b001c 0x003f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0x82018030 -DATA 4 0x021b001c 0x04028030 -DATA 4 0x021b001c 0x02038030 -DATA 4 0x021b001c 0xff0a8038 -DATA 4 0x021b001c 0x82018038 -DATA 4 0x021b001c 0x04028038 -DATA 4 0x021b001c 0x02038038 -DATA 4 0x021b0800 0xa1310003 -DATA 4 0x021b0020 0x00001800 -DATA 4 0x021b0818 0x00000000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x00000000 diff --git a/board/warp/warp.c b/board/warp/warp.c deleted file mode 100644 index c03b648850..0000000000 --- a/board/warp/warp.c +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, 2015 O.S. Systems Software LTDA. - * Copyright (C) 2014 Kynetics LLC. - * Copyright (C) 2014 Revolution Robotics, Inc. - * - * Author: Otavio Salvador <otavio@ossystems.com.br> - */ - -#include <init.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/io.h> -#include <linux/sizes.h> -#include <common.h> -#include <watchdog.h> -#include <fsl_esdhc_imx.h> -#include <i2c.h> -#include <mmc.h> -#include <usb.h> -#include <power/pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ - PAD_CTL_LVE) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ - PAD_CTL_LVE) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C - -enum { - L01_CNFG1 = 0x43, - L01_CNFG2, - L02_CNFG1, - L02_CNFG2, - L03_CNFG1, - L03_CNFG2, - L04_CNFG1, - L04_CNFG2, - L05_CNFG1, - L05_CNFG2, - L06_CNFG1, - L06_CNFG2, - L07_CNFG1, - L07_CNFG2, - L08_CNFG1, - L08_CNFG2, - L09_CNFG1, - L09_CNFG2, - L10_CNFG1, - L10_CNFG2, - LDO_INT1, - LDO_INT2, - LDO_INT1M, - LDO_INT2M, - LDO_CNFG3, - SW1_CNTRL, - SW2_CNTRL, - SW3_CNTRL, - SW4_CNTRL, - EPDCNFG, - EPDINTS, - EPDINT, - EPDINTM, - EPDVCOM, - EPDVEE, - EPDVNEG, - EPDVPOS, - EPDVDDH, - EPDSEQ, - EPDOKINTS, - CID = 0x9c, - PMIC_NUM_OF_REGS, -}; - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static void setup_iomux_uart(void) -{ - static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR, 0, 0, 0, 1}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* Assume boot SD always present */ -} - -int board_mmc_init(struct bd_info *bis) -{ - static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -int board_usb_phy_mode(int port) -{ - return USB_INIT_DEVICE; -} - -/* I2C1 for PMIC */ -#define I2C_PMIC 0 -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .sda = { - .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, - .gp = IMX_GPIO_NR(3, 13), - }, - .scl = { - .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, - .gp = IMX_GPIO_NR(3, 12), - }, -}; - -static int power_max77696_init(unsigned char bus) -{ - static const char name[] = "MAX77696"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = PMIC_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_MAX77696_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg; - - ret = power_max77696_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("MAX77696"); - if (!p) - return -EINVAL; - - ret = pmic_reg_read(p, CID, ®); - if (ret) - return ret; - - printf("PMIC: MAX77696 detected, rev=0x%x\n", reg); - - return pmic_probe(p); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: WaRP Board\n"); - - return 0; -} diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 95b8e82dd1..ead52d5a49 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -66,19 +66,6 @@ int power_init_board(void) } #endif -int board_eth_init(struct bd_info *bis) -{ - int ret = 0; - -#ifdef CONFIG_USB_ETHER - ret = usb_eth_initialize(bis); - if (ret < 0) - printf("Error %d registering USB ether.\n", ret); -#endif - - return ret; -} - int board_init(void) { /* address of boot parameters */ |