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-rw-r--r--board/renesas/condor/Makefile2
-rw-r--r--board/renesas/condor/condor.c47
-rw-r--r--board/renesas/draak/draak.c9
-rw-r--r--board/renesas/eagle/Kconfig2
-rw-r--r--board/renesas/eagle/Makefile2
-rw-r--r--board/renesas/eagle/eagle.c92
-rw-r--r--board/renesas/ebisu/Makefile2
-rw-r--r--board/renesas/ebisu/ebisu.c45
-rw-r--r--board/renesas/falcon/falcon.c7
-rw-r--r--board/renesas/rcar-common/common.c42
-rw-r--r--board/renesas/rcar-common/v3-common.c41
-rw-r--r--board/renesas/salvator-x/salvator-x.c13
-rw-r--r--board/renesas/spider/spider.c5
-rw-r--r--board/renesas/v3hsk/Kconfig15
-rw-r--r--board/renesas/v3hsk/Makefile15
-rw-r--r--board/renesas/v3hsk/cpld.c180
-rw-r--r--board/renesas/v3msk/Kconfig15
-rw-r--r--board/renesas/v3msk/MAINTAINERS6
-rw-r--r--board/renesas/v3msk/Makefile15
-rw-r--r--board/renesas/v3msk/cpld.c368
-rw-r--r--board/renesas/whitehawk/whitehawk.c5
21 files changed, 703 insertions, 225 deletions
diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile
index cf6d566a9b..19e6038430 100644
--- a/board/renesas/condor/Makefile
+++ b/board/renesas/condor/Makefile
@@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
-obj-y := condor.o ../rcar-common/common.o
+obj-y := ../rcar-common/common.o
endif
diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
deleted file mode 100644
index 2dd2c1534c..0000000000
--- a/board/renesas/condor/condor.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/condor/condor.c
- * This file is Condor board support.
- *
- * Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- return 0;
-}
-
-#define RST_BASE 0xE6160000
-#define RST_CA57RESCNT (RST_BASE + 0x40)
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CA57_CODE 0xA5A5000F
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- unsigned long midr, cputype;
-
- asm volatile("mrs %0, midr_el1" : "=r" (midr));
- cputype = (midr >> 4) & 0xfff;
-
- if (cputype == 0xd03)
- writel(RST_CA53_CODE, RST_CA53RESCNT);
- else if (cputype == 0xd07)
- writel(RST_CA57_CODE, RST_CA57RESCNT);
- else
- hang();
-}
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 71efeaf313..1ed72d34a7 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -67,12 +67,3 @@ int board_init(void)
return 0;
}
-
-#define RST_BASE 0xE6160000
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- writel(RST_CA53_CODE, RST_CA53RESCNT);
-}
diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig
index 1e0710e73e..4d12843b4e 100644
--- a/board/renesas/eagle/Kconfig
+++ b/board/renesas/eagle/Kconfig
@@ -10,6 +10,6 @@ config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
- default "eagle"
+ default "rcar-gen3-common"
endif
diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile
index 062c46ba24..9fb6a7c0f0 100644
--- a/board/renesas/eagle/Makefile
+++ b/board/renesas/eagle/Makefile
@@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
-obj-y := eagle.o ../rcar-common/common.o
+obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
endif
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
deleted file mode 100644
index 9af935c33f..0000000000
--- a/board/renesas/eagle/eagle.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/eagle/eagle.c
- * This file is Eagle board support.
- *
- * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <dm.h>
-#include <asm/global_data.h>
-#include <dm/platform_data/serial_sh.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-#include <asm/arch/sh_sdhi.h>
-#include <i2c.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CPGWPR 0xE6150900
-#define CPGWPCR 0xE6150904
-
-/* PLL */
-#define PLL0CR 0xE61500D8
-#define PLL0_STC_MASK 0x7F000000
-#define PLL0_STC_OFFSET 24
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
-void s_init(void)
-{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
- u32 stc;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- /* CPU frequency setting. Set to 0.8GHz */
- stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
- clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
-}
-
-int board_early_init_f(void)
-{
- /* Unlock CPG access */
- writel(0xA5A5FFFF, CPGWPR);
- writel(0x5A5A0000, CPGWPCR);
-
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-#define RST_BASE 0xE6160000
-#define RST_CA57RESCNT (RST_BASE + 0x40)
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CA57_CODE 0xA5A5000F
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- unsigned long midr, cputype;
-
- asm volatile("mrs %0, midr_el1" : "=r" (midr));
- cputype = (midr >> 4) & 0xfff;
-
- if (cputype == 0xd03)
- writel(RST_CA53_CODE, RST_CA53RESCNT);
- else if (cputype == 0xd07)
- writel(RST_CA57_CODE, RST_CA57RESCNT);
- else
- hang();
-}
diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile
index 1fd9a03ecc..956ce8a90f 100644
--- a/board/renesas/ebisu/Makefile
+++ b/board/renesas/ebisu/Makefile
@@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
-obj-y := ebisu.o ../rcar-common/common.o
+obj-y := ../rcar-common/common.o
endif
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
deleted file mode 100644
index 9a70192596..0000000000
--- a/board/renesas/ebisu/ebisu.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/ebisu/ebisu.c
- * This file is Ebisu board support.
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <dm.h>
-#include <asm/global_data.h>
-#include <dm/platform_data/serial_sh.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-#include <asm/arch/sh_sdhi.h>
-#include <i2c.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- return 0;
-}
-
-#define RST_BASE 0xE6160000
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_CA53_CODE 0x5A5A000F
-
-void reset_cpu(void)
-{
- writel(RST_CA53_CODE, RST_CA53RESCNT);
-}
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index ab7464d0ee..0aa0f1afcb 100644
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -84,8 +84,6 @@ int board_early_init_f(void)
}
#define RST_BASE 0xE6160000 /* Domain0 */
-#define RST_SRESCR0 (RST_BASE + 0x18)
-#define RST_SPRES 0x5AA58000
#define RST_WDTRSTCR (RST_BASE + 0x10)
#define RST_RWDT 0xA55A8002
@@ -103,8 +101,3 @@ int board_init(void)
return 0;
}
-
-void reset_cpu(void)
-{
- writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index f38453af82..3a0e88b391 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -10,8 +10,10 @@
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
+#include <hang.h>
#include <init.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <asm/arch/rmobile.h>
#include <linux/libfdt.h>
@@ -47,6 +49,46 @@ int dram_init_banksize(void)
return 0;
}
+int __weak board_init(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_RCAR_GEN3)
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void __weak reset_cpu(void)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}
+#elif defined(CONFIG_RCAR_GEN4)
+#define RST_BASE 0xE6160000 /* Domain0 */
+#define RST_SRESCR0 (RST_BASE + 0x18)
+#define RST_SPRES 0x5AA58000
+
+void __weak reset_cpu(void)
+{
+ writel(RST_SPRES, RST_SRESCR0);
+}
+#else
+#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set
+#endif
+
#if defined(CONFIG_OF_BOARD_SETUP)
static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
{
diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/rcar-common/v3-common.c
new file mode 100644
index 0000000000..7c6202ea49
--- /dev/null
+++ b/board/renesas/rcar-common/v3-common.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <asm/io.h>
+
+#define CPGWPR 0xE6150900
+#define CPGWPCR 0xE6150904
+
+/* PLL */
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_OFFSET 24
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 0.8GHz */
+ stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+int board_early_init_f(void)
+{
+ /* Unlock CPG access */
+ writel(0xA5A5FFFF, CPGWPR);
+ writel(0x5A5A0000, CPGWPCR);
+
+ return 0;
+}
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index c27eb3f17d..939b48ee30 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -67,21 +67,12 @@ int board_init(void)
return 0;
}
-#define RST_BASE 0xE6160000
-#define RST_CA57RESCNT (RST_BASE + 0x40)
-#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CODE 0xA5A5000F
-
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
void reset_cpu(void)
{
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
-#else
- /* only CA57 ? */
- writel(RST_CODE, RST_CA57RESCNT);
-#endif
}
+#endif
#ifdef CONFIG_MULTI_DTB_FIT
int board_fit_config_name_match(const char *name)
diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
index caf88dcc32..fd83a72229 100644
--- a/board/renesas/spider/spider.c
+++ b/board/renesas/spider/spider.c
@@ -65,8 +65,3 @@ int board_init(void)
return 0;
}
-
-void reset_cpu(void)
-{
- writel(RST_SPRES, RST_SRESCR0);
-}
diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig
new file mode 100644
index 0000000000..531ceb788f
--- /dev/null
+++ b/board/renesas/v3hsk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3HSK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "v3hsk"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "v3hsk"
+
+endif
diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
new file mode 100644
index 0000000000..a9d597edd5
--- /dev/null
+++ b/board/renesas/v3hsk/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/v3hsk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-$(CONFIG_SYSRESET) += cpld.o
+endif
diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c
new file mode 100644
index 0000000000..6016f6daef
--- /dev/null
+++ b/board/renesas/v3hsk/cpld.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * V3HSK board CPLD access support
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <linux/err.h>
+#include <sysreset.h>
+#include <command.h>
+
+#define CPLD_ADDR_PRODUCT_0 0x0000 /* R */
+#define CPLD_ADDR_PRODUCT_1 0x0001 /* R */
+#define CPLD_ADDR_PRODUCT_2 0x0002 /* R */
+#define CPLD_ADDR_PRODUCT_3 0x0003 /* R */
+#define CPLD_ADDR_CPLD_VERSION_D 0x0004 /* R */
+#define CPLD_ADDR_CPLD_VERSION_M 0x0005 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_0 0x0006 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_1 0x0007 /* R */
+#define CPLD_ADDR_MODE_SET_0 0x0008 /* R */
+#define CPLD_ADDR_MODE_SET_1 0x0009 /* R */
+#define CPLD_ADDR_MODE_SET_2 0x000A /* R */
+#define CPLD_ADDR_MODE_SET_3 0x000B /* R */
+#define CPLD_ADDR_MODE_SET_4 0x000C /* R */
+#define CPLD_ADDR_MODE_LAST_0 0x0018 /* R */
+#define CPLD_ADDR_MODE_LAST_1 0x0019 /* R */
+#define CPLD_ADDR_MODE_LAST_2 0x001A /* R */
+#define CPLD_ADDR_MODE_LAST_3 0x001B /* R */
+#define CPLD_ADDR_MODE_LAST_4 0x001C /* R */
+#define CPLD_ADDR_DIPSW4 0x0020 /* R */
+#define CPLD_ADDR_DIPSW5 0x0021 /* R */
+#define CPLD_ADDR_RESET 0x0024 /* R/W */
+#define CPLD_ADDR_POWER_CFG 0x0025 /* R/W */
+#define CPLD_ADDR_PERI_CFG_0 0x0030 /* R/W */
+#define CPLD_ADDR_PERI_CFG_1 0x0031 /* R/W */
+#define CPLD_ADDR_PERI_CFG_2 0x0032 /* R/W */
+#define CPLD_ADDR_PERI_CFG_3 0x0033 /* R/W */
+#define CPLD_ADDR_LEDS 0x0034 /* R/W */
+#define CPLD_ADDR_LEDS_CFG 0x0035 /* R/W */
+#define CPLD_ADDR_UART_CFG 0x0036 /* R/W */
+#define CPLD_ADDR_UART_STATUS 0x0037 /* R */
+
+#define CPLD_ADDR_PCB_VERSION_0 0x1000 /* R */
+#define CPLD_ADDR_PCB_VERSION_1 0x1001 /* R */
+#define CPLD_ADDR_SOC_VERSION_0 0x1002 /* R */
+#define CPLD_ADDR_SOC_VERSION_1 0x1003 /* R */
+#define CPLD_ADDR_PCB_SN_0 0x1004 /* R */
+#define CPLD_ADDR_PCB_SN_1 0x1005 /* R */
+
+static u16 cpld_read(struct udevice *dev, u16 addr)
+{
+ u8 data[2];
+
+ /* Random flash reads require 2 reads: first read is unreliable */
+ if (addr >= CPLD_ADDR_PCB_VERSION_0)
+ dm_i2c_read(dev, addr, data, 2);
+
+ /* Only the second byte read is valid */
+ dm_i2c_read(dev, addr, data, 2);
+ return data[1];
+}
+
+static void cpld_write(struct udevice *dev, u16 addr, u8 data)
+{
+ dm_i2c_write(dev, addr, &data, 1);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *dev;
+ u16 addr, val;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+ DM_DRIVER_GET(sysreset_renesas_v3hsk),
+ &dev);
+ if (ret)
+ return ret;
+
+ if (argc == 2 && strcmp(argv[1], "info") == 0) {
+ printf("Product: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) |
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) |
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_PRODUCT_0));
+ printf("CPLD version: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) |
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) |
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) |
+ cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
+ printf("Mode setting (MD0..26): 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) |
+ (cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) |
+ (cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_MODE_LAST_0));
+ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
+ cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff,
+ (cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf);
+ printf("Power config: 0x%08x\n",
+ cpld_read(dev, CPLD_ADDR_POWER_CFG));
+ printf("Periferals config: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) |
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) |
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_PERI_CFG_0));
+ printf("PCB version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION_1),
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION_0));
+ printf("SOC version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION_1),
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION_0));
+ printf("PCB S/N: %d\n",
+ (cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) |
+ cpld_read(dev, CPLD_ADDR_PCB_SN_0));
+ return 0;
+ }
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) {
+ printf("cpld invalid addr\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 3 && strcmp(argv[1], "read") == 0) {
+ printf("0x%x\n", cpld_read(dev, addr));
+ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+ val = simple_strtoul(argv[3], NULL, 16);
+ cpld_write(dev, addr, val);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(cpld, 4, 1, do_cpld,
+ "CPLD access",
+ "info\n"
+ "cpld read addr\n"
+ "cpld write addr val\n"
+);
+
+static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+ return -EINPROGRESS;
+}
+
+static int renesas_v3hsk_sysreset_probe(struct udevice *dev)
+{
+ if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+ return -EPROTONOSUPPORT;
+
+ return 0;
+}
+
+static struct sysreset_ops renesas_v3hsk_sysreset = {
+ .request = renesas_v3hsk_sysreset_request,
+};
+
+static const struct udevice_id renesas_v3hsk_sysreset_ids[] = {
+ { .compatible = "renesas,v3hsk-cpld" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_v3hsk) = {
+ .name = "renesas_v3hsk_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &renesas_v3hsk_sysreset,
+ .probe = renesas_v3hsk_sysreset_probe,
+ .of_match = renesas_v3hsk_sysreset_ids,
+};
diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig
new file mode 100644
index 0000000000..fe037fd98f
--- /dev/null
+++ b/board/renesas/v3msk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3MSK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "v3msk"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rcar-gen3-common"
+
+endif
diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS
new file mode 100644
index 0000000000..12822a4571
--- /dev/null
+++ b/board/renesas/v3msk/MAINTAINERS
@@ -0,0 +1,6 @@
+V3MSK BOARD
+M: Cogent Embedded, Inc. <source@cogentembedded.com>
+S: Maintained
+F: board/renesas/v3msk/
+F: include/configs/v3msk.h
+F: configs/r8a77970_v3msk_defconfig
diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile
new file mode 100644
index 0000000000..ec493e572f
--- /dev/null
+++ b/board/renesas/v3msk/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/v3msk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-$(CONFIG_SYSRESET) += cpld.o
+endif
diff --git a/board/renesas/v3msk/cpld.c b/board/renesas/v3msk/cpld.c
new file mode 100644
index 0000000000..aed616ac85
--- /dev/null
+++ b/board/renesas/v3msk/cpld.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * V3MSK board CPLD access support
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <sysreset.h>
+#include <linux/delay.h>
+#include <command.h>
+
+#define CPLD_ADDR_PRODUCT_L 0x000 /* R */
+#define CPLD_ADDR_PRODUCT_H 0x001 /* R */
+#define CPLD_ADDR_CPLD_VERSION_D 0x002 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y 0x003 /* R */
+#define CPLD_ADDR_MODE_SET_L 0x004 /* R/W */
+#define CPLD_ADDR_MODE_SET_H 0x005 /* R/W */
+#define CPLD_ADDR_MODE_APPLIED_L 0x006 /* R */
+#define CPLD_ADDR_MODE_APPLIED_H 0x007 /* R */
+#define CPLD_ADDR_DIPSW 0x008 /* R */
+#define CPLD_ADDR_RESET 0x00A /* R/W */
+#define CPLD_ADDR_POWER_CFG 0x00B /* R/W */
+#define CPLD_ADDR_PERI_CFG1 0x00C /* R/W */
+#define CPLD_ADDR_PERI_CFG2 0x00D /* R/W */
+#define CPLD_ADDR_LEDS 0x00E /* R/W */
+#define CPLD_ADDR_PCB_VERSION 0x300 /* R */
+#define CPLD_ADDR_SOC_VERSION 0x301 /* R */
+#define CPLD_ADDR_PCB_SN_L 0x302 /* R */
+#define CPLD_ADDR_PCB_SN_H 0x303 /* R */
+
+#define MDIO_DELAY 10 /* microseconds */
+
+#define CPLD_MAX_GPIOS 2
+
+struct renesas_v3msk_sysreset_priv {
+ struct gpio_desc miso;
+ struct gpio_desc mosi;
+ struct gpio_desc mdc;
+ struct gpio_desc enablez;
+ /*
+ * V3MSK Videobox Mini board has CANFD PHY connected
+ * we must shutdown this chip to use bb pins
+ */
+ struct gpio_desc gpios[CPLD_MAX_GPIOS];
+};
+
+static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+ dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+ dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN);
+}
+
+static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val)
+{
+ dm_gpio_set_value(&priv->mosi, val);
+}
+
+static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv)
+{
+ return dm_gpio_get_value(&priv->miso);
+}
+
+static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val)
+{
+ dm_gpio_set_value(&priv->mdc, val);
+}
+
+static void mdio_bb_delay(void)
+{
+ udelay(MDIO_DELAY);
+}
+
+/* Send the preamble, address, and register (common to read and write) */
+static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv,
+ u8 op, u8 addr, u8 reg)
+{
+ int i;
+
+ /* 32-bit preamble */
+ mdio_bb_active_mdio(priv);
+ mdio_bb_set_mdio(priv, 1);
+ for (i = 0; i < 32; i++) {
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ }
+ /* send the ST (2-bits of '01') */
+ mdio_bb_set_mdio(priv, 0);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdio(priv, 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* send the OP (2-bits of Opcode: '10'-read, '01'-write) */
+ mdio_bb_set_mdio(priv, op >> 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdio(priv, op & 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* send the PA5 (5-bits of PHY address) */
+ for (i = 0; i < 5; i++) {
+ mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ addr <<= 1;
+ }
+ /* send the RA5 (5-bits of register address) */
+ for (i = 0; i < 5; i++) {
+ mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ reg <<= 1;
+ }
+}
+
+static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv,
+ u8 addr, u8 reg)
+{
+ int i;
+ u16 data = 0;
+
+ mdio_bb_pre(priv, 2, addr, reg);
+ /* tri-state MDIO */
+ mdio_bb_tristate_mdio(priv);
+ /* read TA (2-bits of turn-around, last bit must be '0') */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* check the turnaround bit: the PHY should drive line to zero */
+ if (mdio_bb_get_mdio(priv) != 0) {
+ printf("PHY didn't drive TA low\n");
+ for (i = 0; i < 32; i++) {
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ }
+ /* There is no PHY, set value to 0xFFFF */
+ return 0xFFFF;
+ }
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ /* read 16-bits of data */
+ for (i = 0; i < 16; i++) {
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ data <<= 1;
+ data |= mdio_bb_get_mdio(priv);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ }
+
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+
+ debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data);
+
+ return data;
+}
+
+static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv,
+ u8 addr, u8 reg, u16 val)
+{
+ int i;
+
+ mdio_bb_pre(priv, 1, addr, reg);
+ /* send the TA (2-bits of turn-around '10') */
+ mdio_bb_set_mdio(priv, 1);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ mdio_bb_set_mdio(priv, 0);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ /* write 16-bits of data */
+ for (i = 0; i < 16; i++) {
+ mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+ val <<= 1;
+ }
+ /* tri-state MDIO */
+ mdio_bb_tristate_mdio(priv);
+ mdio_bb_set_mdc(priv, 0);
+ mdio_bb_delay();
+ mdio_bb_set_mdc(priv, 1);
+ mdio_bb_delay();
+}
+
+static u16 cpld_read(struct udevice *dev, u16 addr)
+{
+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+ /* random flash reads require 2 reads: first read is unreliable */
+ if (addr >= CPLD_ADDR_PCB_VERSION)
+ mdio_bb_read(priv, addr >> 5, addr & 0x1f);
+
+ return mdio_bb_read(priv, addr >> 5, addr & 0x1f);
+}
+
+static void cpld_write(struct udevice *dev, u16 addr, u16 data)
+{
+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+ mdio_bb_write(priv, addr >> 5, addr & 0x1f, data);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *dev;
+ u16 addr, val;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+ DM_DRIVER_GET(sysreset_renesas_v3msk),
+ &dev);
+ if (ret)
+ return ret;
+
+ if (argc == 2 && strcmp(argv[1], "info") == 0) {
+ printf("Product: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) |
+ cpld_read(dev, CPLD_ADDR_PRODUCT_L));
+ printf("CPLD version: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) |
+ cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
+ printf("Mode setting (MD0..26): 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) |
+ cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L));
+ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
+ (cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff,
+ (cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf);
+ printf("Power config: 0x%08x\n",
+ cpld_read(dev, CPLD_ADDR_POWER_CFG));
+ printf("Periferals config: 0x%08x\n",
+ (cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) |
+ cpld_read(dev, CPLD_ADDR_PERI_CFG1));
+ printf("PCB version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8,
+ cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff);
+ printf("SOC version: %d.%d\n",
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8,
+ cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff);
+ printf("PCB S/N: %d\n",
+ (cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) |
+ cpld_read(dev, CPLD_ADDR_PCB_SN_L));
+ return 0;
+ }
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) {
+ printf("cpld invalid addr\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 3 && strcmp(argv[1], "read") == 0) {
+ printf("0x%x\n", cpld_read(dev, addr));
+ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+ val = simple_strtoul(argv[3], NULL, 16);
+ cpld_write(dev, addr, val);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(cpld, 4, 1, do_cpld,
+ "CPLD access",
+ "info\n"
+ "cpld read addr\n"
+ "cpld write addr val\n"
+);
+
+static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+ return -EINPROGRESS;
+}
+
+static int renesas_v3msk_sysreset_probe(struct udevice *dev)
+{
+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
+
+ if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
+ GPIOD_IS_IN))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ /* V3MSK Videobox Mini board has CANFD PHY connected
+ * we must shutdown this chip to use bb pins
+ */
+ gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ return 0;
+}
+
+static struct sysreset_ops renesas_v3msk_sysreset = {
+ .request = renesas_v3msk_sysreset_request,
+};
+
+static const struct udevice_id renesas_v3msk_sysreset_ids[] = {
+ { .compatible = "renesas,v3msk-cpld" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_v3msk) = {
+ .name = "renesas_v3msk_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &renesas_v3msk_sysreset,
+ .probe = renesas_v3msk_sysreset_probe,
+ .of_match = renesas_v3msk_sysreset_ids,
+ .priv_auto = sizeof(struct renesas_v3msk_sysreset_priv),
+};
diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c
index 19f09e009b..32284b2ecc 100644
--- a/board/renesas/whitehawk/whitehawk.c
+++ b/board/renesas/whitehawk/whitehawk.c
@@ -65,8 +65,3 @@ int board_init(void)
return 0;
}
-
-void reset_cpu(void)
-{
- writel(RST_SPRES, RST_SRESCR0);
-}
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 08:51:34 +0000