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-rw-r--r--board/gateworks/gw_ventana/common.c572
-rw-r--r--board/gateworks/gw_ventana/common.h6
-rw-r--r--board/gateworks/gw_ventana/eeprom.c6
-rw-r--r--board/gateworks/gw_ventana/gsc.c172
-rw-r--r--board/gateworks/gw_ventana/gw_ventana.c180
-rw-r--r--board/gateworks/gw_ventana/gw_ventana_spl.c7
-rw-r--r--board/gateworks/gw_ventana/ventana_eeprom.h3
-rw-r--r--board/gateworks/venice/gsc.c82
-rw-r--r--board/gateworks/venice/gsc.h6
-rw-r--r--board/gateworks/venice/imx8mm_venice.c40
-rw-r--r--board/gateworks/venice/lpddr4_timing.c516
-rw-r--r--board/gateworks/venice/lpddr4_timing.h1
-rw-r--r--board/gateworks/venice/spl.c13
13 files changed, 1038 insertions, 566 deletions
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 4a15837473..2be921f47a 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -19,6 +19,7 @@
#include <power/pmic.h>
#include <power/ltc3676_pmic.h>
#include <power/pfuze100_pmic.h>
+#include <power/mp5416.h>
#include "common.h"
@@ -178,21 +179,12 @@ void setup_ventana_i2c(int i2c)
* Baseboard specific GPIO
*/
static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
-
/* GPS_SHDN */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* VID_PWR */
- IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
@@ -204,28 +196,14 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* GPS_SHDN */
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
/* USBOTG_SEL */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* VID_PWR */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
- /* PCI_RST# (GW522x) */
- IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
@@ -239,16 +217,6 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
@@ -257,14 +225,14 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* GPS_SHDN */
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
- /* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+ /* J6_PWREN */
+ IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG),
+ /* PCIEGBE_EN */
+ IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
@@ -274,16 +242,6 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG),
/* MIPI_DIO */
IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
/* RS485_EN */
@@ -294,23 +252,17 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
- /* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+ /* J7_PWREN */
+ IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG),
+ /* PCIEGBE_EN */
+ IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLED# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
@@ -320,16 +272,6 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* USBOTG_SEL */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* MX6_DIO[4:9] */
IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
@@ -348,14 +290,6 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
/* SD3_VSELECT */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
- /* VID_PWR */
- IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
@@ -363,45 +297,23 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
- /* USBH2_PEN (OTG) */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* 12V0_PWR_EN */
IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* ETH1_EN */
IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* PMIC reset */
IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
/* COM_CFGA/B/C/D */
@@ -418,24 +330,14 @@ static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* CAN1_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* CAN2_STBY */
- IOMUX_PADS(PAD_SD3_CLK__GPIO7_IO03 | DIO_PAD_CFG),
/* UART1_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* 5V_UVLO */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* ETI_IRQ# */
IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
/* DIO_IRQ# */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
- /* USBOTG_PEN */
- IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
@@ -449,8 +351,6 @@ static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
/* USBH1_PEN (EHCI) */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* USBH2_PEN (OTG) */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* USBDPC_PEN */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* TOUCH_RST */
@@ -459,8 +359,6 @@ static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
/* UART1_TEN# */
IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* LVDS_BKLEN # */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* RGMII_PDWN# */
@@ -472,14 +370,6 @@ static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
@@ -511,28 +401,18 @@ static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
/* EMMY_PDN# */
IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* MIPI_RST */
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
/* MIPI_PWDN */
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
/* USBEHCI_SEL */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_16__GPIO7_IO11 | DIO_PAD_CFG),
/* LVDS_BKLEN # */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
/* SPK_SHDN# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* LOCLED# */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
- /* FLASH LED1 */
- IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | DIO_PAD_CFG),
- /* FLASH LED2 */
- IOMUX_PADS(PAD_DISP0_DAT12__GPIO5_IO06 | DIO_PAD_CFG),
/* DECT_RST# */
IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
/* USBH1_PEN (EHCI) */
@@ -549,6 +429,28 @@ static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw5910_gpio_pads[] = {
+ /* SD3_VSELECT */
+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+ /* RS232_EN# */
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+ /* RF_RESET# */
+ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+ /* RF_BOOT */
+ IOMUX_PADS(PAD_GPIO_8__GPIO1_IO08 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5912_gpio_pads[] = {
+ /* SD3_VSELECT */
+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+ /* RS232_EN# */
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+};
+
/* Digital I/O */
struct dio_cfg gw51xx_dio[] = {
{
@@ -949,6 +851,51 @@ struct dio_cfg gw5906_dio[] = {
},
};
+struct dio_cfg gw5913_dio[] = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+ IMX_GPIO_NR(1, 18),
+ { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+ 4
+ },
+ {
+ { IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15) },
+ IMX_GPIO_NR(1, 15),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14) },
+ IMX_GPIO_NR(1, 14),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05) },
+ IMX_GPIO_NR(4, 5),
+ { 0, 0 },
+ 0
+ },
+};
+
/*
* Board Specific GPIO
*/
@@ -959,18 +906,13 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
.dio_cfg = gw54xx_dio,
.dio_num = ARRAY_SIZE(gw54xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 10),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
.mezz_pwren = IMX_GPIO_NR(4, 7),
.mezz_irq = IMX_GPIO_NR(4, 9),
.rs485en = IMX_GPIO_NR(3, 24),
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.mmc_cd = IMX_GPIO_NR(7, 0),
+ .wdis = -1,
},
/* GW51xx */
@@ -979,17 +921,10 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
.dio_cfg = gw51xx_dio,
.dio_num = ARRAY_SIZE(gw51xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 10),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 2),
- .vidin_en = IMX_GPIO_NR(5, 20),
.wdis = IMX_GPIO_NR(7, 12),
- .nand = true,
},
/* GW52xx */
@@ -998,23 +933,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
.dio_cfg = gw52xx_dio,
.dio_num = ARRAY_SIZE(gw52xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
- .vidin_en = IMX_GPIO_NR(3, 31),
.usb_sel = IMX_GPIO_NR(1, 2),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
- .nand = true,
},
/* GW53xx */
@@ -1023,22 +950,14 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
.dio_cfg = gw53xx_dio,
.dio_num = ARRAY_SIZE(gw53xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
- .vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
- .nand = true,
},
/* GW54xx */
@@ -1047,16 +966,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
.dio_cfg = gw54xx_dio,
.dio_num = ARRAY_SIZE(gw54xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.rs485en = IMX_GPIO_NR(7, 1),
- .vidin_en = IMX_GPIO_NR(3, 31),
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.wdis = IMX_GPIO_NR(5, 17),
@@ -1064,7 +976,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs232_en = GP_RS232_EN,
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
- .nand = true,
},
/* GW551x */
@@ -1073,12 +984,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
.dio_cfg = gw551x_dio,
.dio_num = ARRAY_SIZE(gw551x_dio),
- .leds = {
- IMX_GPIO_NR(4, 7),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
- .nand = true,
},
/* GW552x */
@@ -1087,16 +993,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
.dio_cfg = gw552x_dio,
.dio_num = ARRAY_SIZE(gw552x_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
- .nand = true,
},
/* GW553x */
@@ -1105,16 +1004,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
.dio_cfg = gw553x_dio,
.dio_num = ARRAY_SIZE(gw553x_dio),
- .leds = {
- IMX_GPIO_NR(4, 10),
- IMX_GPIO_NR(4, 11),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
- .vidin_en = IMX_GPIO_NR(5, 20),
.wdis = IMX_GPIO_NR(7, 12),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
- .nand = true,
},
/* GW560x */
@@ -1123,16 +1015,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
.dio_cfg = gw560x_dio,
.dio_num = ARRAY_SIZE(gw560x_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(4, 31),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.rs232_en = GP_RS232_EN,
- .vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
.mmc_cd = IMX_GPIO_NR(7, 0),
},
@@ -1142,11 +1027,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.gpio_pads = gw5901_gpio_pads,
.num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
.dio_cfg = gw5901_dio,
- .leds = {
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .nand = true,
+ .wdis = -1,
},
/* GW5902 */
@@ -1154,12 +1035,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.gpio_pads = gw5902_gpio_pads,
.num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
.dio_cfg = gw5902_dio,
- .leds = {
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
.rs232_en = GP_RS232_EN,
- .nand = true,
+ .wdis = -1,
},
/* GW5903 */
@@ -1168,10 +1045,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
.dio_cfg = gw5903_dio,
.dio_num = ARRAY_SIZE(gw5903_dio),
- .leds = {
- IMX_GPIO_NR(6, 14),
- },
.mmc_cd = IMX_GPIO_NR(6, 11),
+ .wdis = -1,
},
/* GW5904 */
@@ -1180,24 +1055,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
.dio_cfg = gw5904_dio,
.dio_num = ARRAY_SIZE(gw5904_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
+ .wdis = -1,
},
/* GW5905 */
{
.gpio_pads = gw5905_gpio_pads,
.num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
- .leds = {
- IMX_GPIO_NR(6, 14),
- },
- .pcie_rst = IMX_GPIO_NR(7, 11),
.wdis = IMX_GPIO_NR(7, 13),
},
@@ -1207,16 +1073,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
.dio_cfg = gw5906_dio,
.dio_num = ARRAY_SIZE(gw5906_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
- .nand = true,
},
/* GW5907 */
@@ -1225,13 +1084,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
.dio_cfg = gw51xx_dio,
.dio_num = ARRAY_SIZE(gw51xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 10),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
- .nand = true,
},
/* GW5908 */
@@ -1240,16 +1093,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
.dio_cfg = gw53xx_dio,
.dio_num = ARRAY_SIZE(gw53xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
- .vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
@@ -1261,14 +1107,42 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
.dio_cfg = gw5904_dio,
.dio_num = ARRAY_SIZE(gw5904_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
+ .wdis = -1,
+ },
+
+ /* GW5910 */
+ {
+ .gpio_pads = gw5910_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw5910_gpio_pads) / 2,
+ .dio_cfg = gw52xx_dio,
+ .dio_num = ARRAY_SIZE(gw52xx_dio),
+ .wdis = IMX_GPIO_NR(7, 12),
+ .rs232_en = GP_RS232_EN,
+ .vsel_pin = IMX_GPIO_NR(6, 14),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
+ },
+
+ /* GW5912 */
+ {
+ .gpio_pads = gw5912_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2,
+ .dio_cfg = gw54xx_dio,
+ .dio_num = ARRAY_SIZE(gw54xx_dio),
+ .wdis = IMX_GPIO_NR(1, 0),
+ .rs232_en = GP_RS232_EN,
+ .vsel_pin = IMX_GPIO_NR(6, 14),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
+ },
+
+ /* GW5913 */
+ {
+ .gpio_pads = gw5912_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2,
+ .dio_cfg = gw5913_dio,
+ .dio_num = ARRAY_SIZE(gw5913_dio),
+ .wdis = IMX_GPIO_NR(1, 0),
},
};
@@ -1280,8 +1154,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
gpio_direction_input(gpio);
void setup_iomux_gpio(int board, struct ventana_board_info *info)
{
- int i;
-
if (board >= GW_UNKNOWN)
return;
@@ -1295,24 +1167,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_direction_output(gpio_cfg[board].rs232_en, 0);
}
- /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
- if (board == GW52xx && info->model[4] == '2')
- gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
-
- /* assert PCI_RST# */
- gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#");
- gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
-
- /* turn off (active-high) user LED's */
- for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
- char name[16];
- if (gpio_cfg[board].leds[i]) {
- sprintf(name, "led_user%d", i);
- gpio_request(gpio_cfg[board].leds[i], name);
- gpio_direction_output(gpio_cfg[board].leds[i], 1);
- }
- }
-
/* MSATA Enable - default to PCI */
if (gpio_cfg[board].msata_en) {
gpio_request(gpio_cfg[board].msata_en, "msata_en");
@@ -1341,12 +1195,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
}
- /* Analog video codec power enable */
- if (gpio_cfg[board].vidin_en) {
- gpio_request(gpio_cfg[board].vidin_en, "anavidin_en");
- gpio_direction_output(gpio_cfg[board].vidin_en, 1);
- }
-
/* DIOI2C_DIS# */
if (gpio_cfg[board].dioi2c_en) {
gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
@@ -1366,7 +1214,7 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
}
/* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
- if (gpio_cfg[board].wdis) {
+ if (gpio_cfg[board].wdis != -1) {
gpio_request(gpio_cfg[board].wdis, "wlan_dis");
gpio_direction_output(gpio_cfg[board].wdis, 1);
}
@@ -1386,16 +1234,23 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
/* Anything else board specific */
switch(board) {
+ case GW53xx:
+ gpio_request(IMX_GPIO_NR(3, 15), "j6_pwren");
+ gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
+ gpio_request(IMX_GPIO_NR(3, 14), "gbe_en");
+ gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
+ break;
+ case GW54xx:
+ gpio_request(IMX_GPIO_NR(3, 15), "j7_pwren");
+ gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
+ gpio_request(IMX_GPIO_NR(3, 14), "gbe_en");
+ gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
+ break;
case GW560x:
gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
break;
- case GW5901:
- SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can_stby", 0);
- break;
case GW5902:
- SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can1_stby", 0);
- SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 3), "can2_stby", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
break;
case GW5903:
@@ -1453,6 +1308,11 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
*/
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
break;
+ case GW5910:
+ /* CC1352 */
+ SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "rf_reset#", 1);
+ SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 8), "rf_boot", 1);
+ break;
}
}
@@ -1695,6 +1555,170 @@ void setup_pmic(void)
pmic_reg_write(p, LTC3676_BUCK3, 0xc0);
pmic_reg_write(p, LTC3676_BUCK4, 0xc0);
}
+
+ /* configure MP5416 PMIC */
+ else if (!i2c_probe(0x69)) {
+ puts("PMIC: MP5416\n");
+ switch (board) {
+ case GW5910:
+ /* SW1: VDD_ARM 1.2V -> (1.275 to 1.475) */
+ reg = MP5416_VSET_EN | MP5416_VSET_SW1_SVAL(1475000);
+ i2c_write(0x69, MP5416_VSET_SW1, 1, (uint8_t *)&reg, 1);
+ /* SW4: VDD_SOC 1.2V -> (1.350 to 1.475) */
+ reg = MP5416_VSET_EN | MP5416_VSET_SW4_SVAL(1475000);
+ i2c_write(0x69, MP5416_VSET_SW4, 1, (uint8_t *)&reg, 1);
+ break;
+ }
+ }
+}
+
+#include <fdt_support.h>
+#define WDOG1_ADDR 0x20bc000
+#define WDOG2_ADDR 0x20c0000
+#define GPIO3_ADDR 0x20a4000
+#define USDHC3_ADDR 0x2198000
+
+static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
+{
+ int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
+
+ if (off) {
+ fdt_delprop(blob, off, "ext-reset-output");
+ fdt_delprop(blob, off, "fsl,ext-reset-output");
+ }
+}
+
+void ft_early_fixup(void *blob, int board_type)
+{
+ struct ventana_board_info *info = &ventana_info;
+ char rev = 0;
+ int i;
+
+ /* determine board revision */
+ for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
+ if (ventana_info.model[i] >= 'A') {
+ rev = ventana_info.model[i];
+ break;
+ }
+ }
+
+ /*
+ * Board model specific fixups
+ */
+ switch (board_type) {
+ case GW51xx:
+ /*
+ * disable wdog node for GW51xx-A/B to work around
+ * errata causing wdog timer to be unreliable.
+ */
+ if (rev >= 'A' && rev < 'C') {
+ i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
+ WDOG1_ADDR);
+ if (i)
+ fdt_status_disabled(blob, i);
+ }
+
+ /* GW51xx-E adds WDOG1_B external reset */
+ if (rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+
+ case GW52xx:
+ /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
+ if (info->model[4] == '2') {
+ u32 handle = 0;
+ u32 *range = NULL;
+
+ i = fdt_node_offset_by_compatible(blob, -1,
+ "fsl,imx6q-pcie");
+ if (i)
+ range = (u32 *)fdt_getprop(blob, i,
+ "reset-gpio", NULL);
+
+ if (range) {
+ i = fdt_node_offset_by_compat_reg(blob,
+ "fsl,imx6q-gpio", GPIO3_ADDR);
+ if (i)
+ handle = fdt_get_phandle(blob, i);
+ if (handle) {
+ range[0] = cpu_to_fdt32(handle);
+ range[1] = cpu_to_fdt32(23);
+ }
+ }
+
+ /* these have broken usd_vsel */
+ if (strstr((const char *)info->model, "SP318-B") ||
+ strstr((const char *)info->model, "SP331-B"))
+ gpio_cfg[board_type].usd_vsel = 0;
+
+ /* GW522x-B adds WDOG1_B external reset */
+ if (rev < 'B')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ }
+
+ /* GW520x-E adds WDOG1_B external reset */
+ else if (info->model[4] == '0' && rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+
+ case GW53xx:
+ /* GW53xx-E adds WDOG1_B external reset */
+ if (rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+
+ /* GW53xx-G has an adv7280 instead of an adv7180 */
+ else if (rev > 'F') {
+ i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
+ if (i) {
+ fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
+ fdt_setprop_empty(blob, i, "adv,force-bt656-4");
+ }
+ }
+ break;
+
+ case GW54xx:
+ /*
+ * disable serial2 node for GW54xx for compatibility with older
+ * 3.10.x kernel that improperly had this node enabled in the DT
+ */
+ fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
+ 0);
+
+ /* GW54xx-E adds WDOG2_B external reset */
+ if (rev < 'E')
+ ft_board_wdog_fixup(blob, WDOG2_ADDR);
+
+ /* GW54xx-G has an adv7280 instead of an adv7180 */
+ else if (rev > 'F') {
+ i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
+ if (i) {
+ fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
+ fdt_setprop_empty(blob, i, "adv,force-bt656-4");
+ }
+ }
+ break;
+
+ case GW551x:
+ /* GW551x-C adds WDOG1_B external reset */
+ if (rev < 'C')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+ case GW5901:
+ case GW5902:
+ /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
+ if (rev < 'B')
+ ft_board_wdog_fixup(blob, WDOG1_ADDR);
+ break;
+ }
+
+ /* remove no-1-8-v if UHS-I support is present */
+ if (gpio_cfg[board_type].usd_vsel) {
+ debug("Enabling UHS-I support\n");
+ i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
+ USDHC3_ADDR);
+ if (i)
+ fdt_delprop(blob, i, "no-1-8-v");
+ }
}
#ifdef CONFIG_FSL_ESDHC_IMX
@@ -1711,6 +1735,8 @@ int board_mmc_init(struct bd_info *bis)
case GW53xx:
case GW54xx:
case GW553x:
+ case GW5910:
+ case GW5912:
/* usdhc3: 4bit microSD */
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 813f7d9f56..edfb065f6a 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -61,13 +61,10 @@ struct ventana {
struct dio_cfg *dio_cfg;
int dio_num;
/* various gpios (0 if non-existent) */
- int leds[3];
- int pcie_rst;
int mezz_pwren;
int mezz_irq;
int rs485en;
int gps_shdn;
- int vidin_en;
int dioi2c_en;
int pcie_sson;
int usb_sel;
@@ -78,7 +75,6 @@ struct ventana {
int mmc_cd;
/* various features */
bool usd_vsel;
- bool nand;
};
extern struct ventana gpio_cfg[GW_UNKNOWN];
@@ -93,5 +89,7 @@ void setup_pmic(void);
void setup_iomux_gpio(int board, struct ventana_board_info *);
/* late setup of GPIO (configuration per baseboard and env) */
void setup_board_gpio(int board, struct ventana_board_info *);
+/* early model/revision ft fixups */
+void ft_early_fixup(void *fdt, int board_type);
#endif /* #ifndef _GWVENTANA_COMMON_H_ */
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index b9862c7dfc..d21aa3c38f 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -124,6 +124,12 @@ read_eeprom(int bus, struct ventana_board_info *info)
type = GW5908;
else if (info->model[4] == '0' && info->model[5] == '9')
type = GW5909;
+ else if (info->model[4] == '1' && info->model[5] == '0')
+ type = GW5910;
+ else if (info->model[4] == '1' && info->model[5] == '2')
+ type = GW5912;
+ else if (info->model[4] == '1' && info->model[5] == '3')
+ type = GW5913;
break;
default:
printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 59fd1b6939..324e5dbed2 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -15,10 +15,13 @@
#include <linux/ctype.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include "ventana_eeprom.h"
#include "gsc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* The Gateworks System Controller will fail to ACK a master transaction if
* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
@@ -65,24 +68,116 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
return ret;
}
-static void read_hwmon(const char *name, uint reg, uint size)
+int gsc_get_board_temp(void)
{
- unsigned char buf[3];
- uint ui;
+ const void *fdt = gd->fdt_blob;
+ int node, reg, mode, val;
+ const char *label;
+ u8 buf[2];
+ int ret;
- printf("%-8s:", name);
- memset(buf, 0, sizeof(buf));
- if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
- puts("fRD\n");
- } else {
- ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
- if (size == 2 && ui > 0x8000)
- ui -= 0xffff;
- if (ui == 0xffffff)
- puts("invalid\n");
- else
- printf("%d\n", ui);
+ node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
+ if (node <= 0)
+ return node;
+ i2c_set_bus_num(0);
+
+ /* iterate over hwmon nodes */
+ node = fdt_first_subnode(fdt, node);
+ while (node > 0) {
+ reg = fdtdec_get_int(fdt, node, "reg", -1);
+ mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
+ label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
+
+ if ((reg == -1) || (mode == -1) || !label) {
+ printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
+ continue;
+ }
+
+ if ((mode != 0) || strcmp(label, "temp"))
+ continue;
+
+ memset(buf, 0, sizeof(buf));
+ ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf));
+ val = buf[0] | buf[1] << 8;
+ if (val >= 0) {
+ if (val > 0x8000)
+ val -= 0xffff;
+ return val;
+ }
+ node = fdt_next_subnode(fdt, node);
}
+
+ return 0;
+}
+
+/* display hardware monitor ADC channels */
+int gsc_hwmon(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int node, reg, mode, len, val, offset;
+ const char *label;
+ u8 buf[2];
+ int ret;
+
+ node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
+ if (node <= 0)
+ return node;
+ i2c_set_bus_num(0);
+
+ /* iterate over hwmon nodes */
+ node = fdt_first_subnode(fdt, node);
+ while (node > 0) {
+ reg = fdtdec_get_int(fdt, node, "reg", -1);
+ mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
+ offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
+ label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
+
+ if ((reg == -1) || (mode == -1) || !label)
+ printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
+
+ memset(buf, 0, sizeof(buf));
+ ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf));
+ val = buf[0] | buf[1] << 8;
+ if (val >= 0) {
+ const u32 *div;
+ int r[2];
+
+ switch (mode) {
+ case 0: /* temperature (C*10) */
+ if (val > 0x8000)
+ val -= 0xffff;
+ printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
+ break;
+ case 1: /* prescaled voltage */
+ if (val != 0xffff)
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ case 2: /* scaled based on ref volt and resolution */
+ val *= 2500;
+ val /= 1 << 12;
+
+ /* apply pre-scaler voltage divider */
+ div = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
+ if (div && (len == sizeof(uint32_t) * 2)) {
+ r[0] = fdt32_to_cpu(div[0]);
+ r[1] = fdt32_to_cpu(div[1]);
+ if (r[0] && r[1]) {
+ val *= (r[0] + r[1]);
+ val /= r[1];
+ }
+ }
+
+ /* adjust by offset */
+ val += (offset / 1000);
+
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ }
+ }
+ node = fdt_next_subnode(fdt, node);
+ }
+
+ return 0;
}
int gsc_info(int verbose)
@@ -103,54 +198,13 @@ int gsc_info(int verbose)
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
&buf[GSC_SC_STATUS], 1);
}
- if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
- int ui = buf[0] | buf[1]<<8;
- if (ui > 0x8000)
- ui -= 0xffff;
- printf(" board temp at %dC", ui / 10);
- }
+ printf(" board temp at %dC", gsc_get_board_temp() / 10);
puts("\n");
if (!verbose)
return CMD_RET_SUCCESS;
- read_hwmon("Temp", GSC_HWMON_TEMP, 2);
- read_hwmon("VIN", GSC_HWMON_VIN, 3);
- read_hwmon("VBATT", GSC_HWMON_VBATT, 3);
- read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3);
- read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3);
- read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
- read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
- read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
- read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
- if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
- read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
- read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
- read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
- switch (ventana_info.model[3]) {
- case '1': /* GW51xx */
- read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
- break;
- case '2': /* GW52xx */
- break;
- case '3': /* GW53xx */
- read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */
- read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
- break;
- case '4': /* GW54xx */
- read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
- read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
- break;
- case '5': /* GW55xx */
- break;
- case '6': /* GW560x */
- read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
- read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
- break;
- case '9': /* GW590x */
- read_hwmon("AMONBMON", GSC_HWMON_VDD_IO3, 3);
- read_hwmon("BAT_VOLT", GSC_HWMON_VDD_EXT, 3);
- read_hwmon("BAT_TEMP", GSC_HWMON_VDD_IO4, 2);
- }
+ gsc_hwmon();
+
return 0;
}
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 912075db88..79629828d0 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -372,18 +372,6 @@ int power_init_board(void)
return 0;
}
-int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
-{
- if (board_type < GW_UNKNOWN) {
- uint pin = gpio_cfg[board_type].pcie_rst;
- gpio_request(pin, "pci_rst#");
- gpio_direction_output(pin, 0);
- mdelay(50);
- gpio_direction_output(pin, 1);
- }
- return 0;
-}
-
/*
* Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
* GPIO's as PERST# signals for its downstream ports - configure the GPIO's
@@ -967,16 +955,6 @@ void ft_board_pci_fixup(void *blob, struct bd_info *bd)
}
#endif /* if defined(CONFIG_CMD_PCI) */
-void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
-{
- int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
-
- if (off) {
- fdt_delprop(blob, off, "ext-reset-output");
- fdt_delprop(blob, off, "fsl,ext-reset-output");
- }
-}
-
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
@@ -986,16 +964,12 @@ void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
* - board (full model from EEPROM)
* - peripherals removed from DTB if not loaded on board (per EEPROM config)
*/
-#define WDOG1_ADDR 0x20bc000
-#define WDOG2_ADDR 0x20c0000
-#define GPIO3_ADDR 0x20a4000
-#define USDHC3_ADDR 0x2198000
#define PWM0_ADDR 0x2080000
int ft_board_setup(void *blob, struct bd_info *bd)
{
struct ventana_board_info *info = &ventana_info;
struct ventana_eeprom_config *cfg;
- static const struct node_info nodes[] = {
+ static const struct node_info nand_nodes[] = {
{ "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
};
@@ -1017,11 +991,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
- if (test_bit(EECONFIG_NAND, info->config)) {
- /* Update partition nodes using info from mtdparts env var */
- puts(" Updating MTD partitions...\n");
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- }
+ /* Update MTD partition nodes using info from mtdparts env var */
+ puts(" Updating MTD partitions...\n");
+ fdt_fixup_mtdparts(blob, nand_nodes, ARRAY_SIZE(nand_nodes));
/* Update display timings from display env var */
if (display) {
@@ -1043,139 +1015,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
/* set desired digital video capture format */
ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
- /*
- * Board model specific fixups
- */
- switch (board_type) {
- case GW51xx:
- /*
- * disable wdog node for GW51xx-A/B to work around
- * errata causing wdog timer to be unreliable.
- */
- if (rev >= 'A' && rev < 'C') {
- i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
- WDOG1_ADDR);
- if (i)
- fdt_status_disabled(blob, i);
- }
-
- /* GW51xx-E adds WDOG1_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
-
- case GW52xx:
- /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
- if (info->model[4] == '2') {
- u32 handle = 0;
- u32 *range = NULL;
-
- i = fdt_node_offset_by_compatible(blob, -1,
- "fsl,imx6q-pcie");
- if (i)
- range = (u32 *)fdt_getprop(blob, i,
- "reset-gpio", NULL);
-
- if (range) {
- i = fdt_node_offset_by_compat_reg(blob,
- "fsl,imx6q-gpio", GPIO3_ADDR);
- if (i)
- handle = fdt_get_phandle(blob, i);
- if (handle) {
- range[0] = cpu_to_fdt32(handle);
- range[1] = cpu_to_fdt32(23);
- }
- }
-
- /* these have broken usd_vsel */
- if (strstr((const char *)info->model, "SP318-B") ||
- strstr((const char *)info->model, "SP331-B"))
- gpio_cfg[board_type].usd_vsel = 0;
-
- /* GW522x-B adds WDOG1_B external reset */
- if (rev < 'B')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- }
-
- /* GW520x-E adds WDOG1_B external reset */
- else if (info->model[4] == '0' && rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
-
- case GW53xx:
- /* GW53xx-E adds WDOG1_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
-
- case GW54xx:
- /*
- * disable serial2 node for GW54xx for compatibility with older
- * 3.10.x kernel that improperly had this node enabled in the DT
- */
- fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
- 0);
-
- /* GW54xx-E adds WDOG2_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG2_ADDR);
- break;
-
- case GW551x:
- /*
- * isolate CSI0_DATA_EN for GW551x-A to work around errata
- * causing non functional digital video in (it is not hooked up)
- */
- if (rev == 'A') {
- u32 *range = NULL;
- int len;
- const u32 *handle = NULL;
-
- i = fdt_node_offset_by_compatible(blob, -1,
- "fsl,imx-tda1997x-video");
- if (i)
- handle = fdt_getprop(blob, i, "pinctrl-0",
- NULL);
- if (handle)
- i = fdt_node_offset_by_phandle(blob,
- fdt32_to_cpu(*handle));
- if (i)
- range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
- &len);
- if (range) {
- len /= sizeof(u32);
- for (i = 0; i < len; i += 6) {
- u32 mux_reg = fdt32_to_cpu(range[i+0]);
- u32 conf_reg = fdt32_to_cpu(range[i+1]);
- /* mux PAD_CSI0_DATA_EN to GPIO */
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- mux_reg == 0x260 &&
- conf_reg == 0x630)
- range[i+3] = cpu_to_fdt32(0x5);
- else if (!is_cpu_type(MXC_CPU_MX6Q) &&
- mux_reg == 0x08c &&
- conf_reg == 0x3a0)
- range[i+3] = cpu_to_fdt32(0x5);
- }
- fdt_setprop_inplace(blob, i, "fsl,pins", range,
- len);
- }
-
- /* set BT656 video format */
- ft_sethdmiinfmt(blob, "yuv422bt656");
- }
-
- /* GW551x-C adds WDOG1_B external reset */
- if (rev < 'C')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
- case GW5901:
- case GW5902:
- /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
- if (rev < 'B')
- ft_board_wdog_fixup(blob, WDOG1_ADDR);
- break;
- }
+ /* early board/revision ft fixups */
+ ft_early_fixup(blob, board_type);
/* Configure DIO */
for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
@@ -1201,15 +1042,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
}
- /* remove no-1-8-v if UHS-I support is present */
- if (gpio_cfg[board_type].usd_vsel) {
- debug("Enabling UHS-I support\n");
- i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
- USDHC3_ADDR);
- if (i)
- fdt_delprop(blob, i, "no-1-8-v");
- }
-
#if defined(CONFIG_CMD_PCI)
if (!env_get("nopcifixup"))
ft_board_pci_fixup(blob, bd);
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index a4f64395a1..5a69aff671 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -729,10 +729,10 @@ void board_boot_order(u32 *spl_boot_list)
/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* its our chance to print info about boot device */
+static int board_type;
void spl_board_init(void)
{
u32 boot_device;
- int board_type;
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
boot_device = spl_boot_device();
@@ -785,3 +785,8 @@ int spl_start_uboot(void)
return ret;
}
#endif
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ ft_early_fixup(spl_image->fdt_addr, board_type);
+}
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index 4fa085b320..2d5c27261e 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -121,6 +121,9 @@ enum {
GW5907,
GW5908,
GW5909,
+ GW5910,
+ GW5912,
+ GW5913,
GW_UNKNOWN,
GW_BADCRC,
};
diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c
index 271bc8c229..7d6acd7b4a 100644
--- a/board/gateworks/venice/gsc.c
+++ b/board/gateworks/venice/gsc.c
@@ -18,6 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct venice_board_info som_info;
struct venice_board_info base_info;
char venice_model[32];
+uint32_t venice_serial;
/* return a mac address from EEPROM info */
int gsc_getmac(int index, uint8_t *address)
@@ -123,13 +124,13 @@ enum {
GSC_SC_RST_CAUSE_MAX = 10,
};
+#include <dm/device.h>
static struct udevice *gsc_get_dev(int busno, int slave)
{
- static const char * const i2c[] = { "i2c@30a20000", "i2c@30a30000" };
struct udevice *dev, *bus;
int ret;
- ret = uclass_get_device_by_name(UCLASS_I2C, i2c[busno - 1], &bus);
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
if (ret) {
printf("GSC : failed I2C%d probe: %d\n", busno, ret);
return NULL;
@@ -246,7 +247,7 @@ int gsc_hwmon(void)
return node;
/* probe device */
- dev = gsc_get_dev(1, GSC_HWMON_ADDR);
+ dev = gsc_get_dev(GSC_BUSNO, GSC_HWMON_ADDR);
if (!dev) {
puts("ERROR: Failed to probe GSC HWMON\n");
return -ENODEV;
@@ -451,33 +452,22 @@ const char *gsc_get_dtb_name(int level, char *buf, int sz)
static int gsc_read(void)
{
+ char rev_pcb;
+ int rev_bom;
int ret;
- ret = gsc_read_eeprom(1, GSC_EEPROM_ADDR, 1, &som_info);
+ ret = gsc_read_eeprom(GSC_BUSNO, GSC_EEPROM_ADDR, 1, &som_info);
if (ret) {
memset(&som_info, 0, sizeof(som_info));
return ret;
}
/* read optional baseboard EEPROM */
- return gsc_read_eeprom(2, 0x52, 2, &base_info);
-}
+ gsc_read_eeprom(BASEBOARD_EEPROM_BUSNO, BASEBOARD_EEPROM_ADDR,
+ 2, &base_info);
-static int gsc_info(int verbose)
-{
- struct udevice *dev;
- unsigned char buf[16];
- char rev_pcb;
- int rev_bom;
-
- if (!base_info.model[0]) {
- strcpy(venice_model, som_info.model);
- printf("Model : %s\n", som_info.model);
- printf("Serial : %d\n", som_info.serial);
- printf("MFGDate : %02x-%02x-%02x%02x\n",
- som_info.mfgdate[0], som_info.mfgdate[1],
- som_info.mfgdate[2], som_info.mfgdate[3]);
- } else {
+ /* create model strings */
+ if (base_info.model[0]) {
sprintf(venice_model, "GW%c%c%c%c-%c%c-",
som_info.model[2], /* family */
base_info.model[3], /* baseboard */
@@ -498,27 +488,38 @@ static int gsc_info(int verbose)
sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
else
sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+ } else {
+ strcpy(venice_model, som_info.model);
+ }
+ venice_serial = som_info.serial;
- if (verbose > 1) {
- printf("SOM : %s %d %02x-%02x-%02x%02x\n",
- som_info.model, som_info.serial,
- som_info.mfgdate[0], som_info.mfgdate[1],
- som_info.mfgdate[2], som_info.mfgdate[3]);
- printf("BASE : %s %d %02x-%02x-%02x%02x\n",
- base_info.model, base_info.serial,
- base_info.mfgdate[0], base_info.mfgdate[1],
- base_info.mfgdate[2], base_info.mfgdate[3]);
- }
- printf("Model : %s\n", venice_model);
- printf("Serial : %d\n", som_info.serial);
- printf("MFGDate : %02x-%02x-%02x%02x\n",
+ return 0;
+}
+
+static int gsc_info(int verbose)
+{
+ struct udevice *dev;
+ unsigned char buf[16];
+
+ printf("Model : %s\n", venice_model);
+ printf("Serial : %d\n", som_info.serial);
+ printf("MFGDate : %02x-%02x-%02x%02x\n",
+ som_info.mfgdate[0], som_info.mfgdate[1],
+ som_info.mfgdate[2], som_info.mfgdate[3]);
+ if (base_info.model[0] && verbose > 1) {
+ printf("SOM : %s %d %02x-%02x-%02x%02x\n",
+ som_info.model, som_info.serial,
som_info.mfgdate[0], som_info.mfgdate[1],
som_info.mfgdate[2], som_info.mfgdate[3]);
+ printf("BASE : %s %d %02x-%02x-%02x%02x\n",
+ base_info.model, base_info.serial,
+ base_info.mfgdate[0], base_info.mfgdate[1],
+ base_info.mfgdate[2], base_info.mfgdate[3]);
}
/* Display RTC */
puts("RTC : ");
- dev = gsc_get_dev(1, GSC_RTC_ADDR);
+ dev = gsc_get_dev(GSC_BUSNO, GSC_RTC_ADDR);
if (!dev) {
puts("Failed to probe GSC RTC\n");
} else {
@@ -542,7 +543,7 @@ int gsc_init(int quiet)
*/
while (1) {
/* probe device */
- dev = gsc_get_dev(1, GSC_SC_ADDR);
+ dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR);
if (dev)
break;
mdelay(1);
@@ -575,6 +576,11 @@ const char *gsc_get_model(void)
return venice_model;
}
+uint32_t gsc_get_serial(void)
+{
+ return venice_serial;
+}
+
#if !(IS_ENABLED(CONFIG_SPL_BUILD))
static int gsc_sleep(unsigned long secs)
{
@@ -583,7 +589,7 @@ static int gsc_sleep(unsigned long secs)
int ret;
/* probe device */
- dev = gsc_get_dev(1, GSC_SC_ADDR);
+ dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR);
if (!dev)
return -ENODEV;
@@ -631,7 +637,7 @@ static int gsc_boot_wd_disable(void)
int ret;
/* probe device */
- dev = gsc_get_dev(1, GSC_SC_ADDR);
+ dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR);
if (!dev)
return -ENODEV;
diff --git a/board/gateworks/venice/gsc.h b/board/gateworks/venice/gsc.h
index 27b02117bb..b391b2e326 100644
--- a/board/gateworks/venice/gsc.h
+++ b/board/gateworks/venice/gsc.h
@@ -6,11 +6,16 @@
#ifndef _GSC_H_
#define _GSC_H_
+/* I2C bus numbers */
+#define GSC_BUSNO 0
+#define BASEBOARD_EEPROM_BUSNO 1
+
/* I2C slave addresses */
#define GSC_SC_ADDR 0x20
#define GSC_RTC_ADDR 0x68
#define GSC_HWMON_ADDR 0x29
#define GSC_EEPROM_ADDR 0x51
+#define BASEBOARD_EEPROM_ADDR 0x52
struct venice_board_info {
u8 mac[6]; /* 0x00: MAC base */
@@ -35,5 +40,6 @@ int gsc_hwmon(void);
const char *gsc_get_model(void);
const char *gsc_get_dtb_name(int level, char *buf, int len);
int gsc_getmac(int index, uint8_t *enetaddr);
+uint32_t gsc_get_serial(void);
#endif
diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c
index 2657bd675f..2a97d55d32 100644
--- a/board/gateworks/venice/imx8mm_venice.c
+++ b/board/gateworks/venice/imx8mm_venice.c
@@ -13,6 +13,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include <asm/unaligned.h>
#include "gsc.h"
@@ -20,20 +21,19 @@ DECLARE_GLOBAL_DATA_PTR;
int board_phys_sdram_size(phys_size_t *size)
{
- int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
-
- if (ddr_size == 0x4) {
- *size = 0x100000000;
- } else if (ddr_size == 0x3) {
- *size = 0xc0000000;
- } else if (ddr_size == 0x2) {
- *size = 0x80000000;
- } else if (ddr_size == 0x1) {
- *size = 0x40000000;
- } else {
- printf("Unknown DDR type!!!\n");
- *size = 0x40000000;
- }
+ const fdt64_t *val;
+ int offset;
+ int len;
+
+ /* get size from dt which SPL updated per EEPROM config */
+ offset = fdt_path_offset(gd->fdt_blob, "/memory");
+ if (offset < 0)
+ return -EINVAL;
+
+ val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+ if (len < sizeof(*val) * 2)
+ return -EINVAL;
+ *size = get_unaligned_be64(&val[1]);
return 0;
}
@@ -113,6 +113,10 @@ int board_late_init(void)
led_default_state();
+ /* Set board serial/model */
+ env_set_ulong("serial#", gsc_get_serial());
+ env_set("model", gsc_get_model());
+
/* Set fdt_file vars */
i = 0;
do {
@@ -148,3 +152,11 @@ int board_mmc_get_env_dev(int devno)
{
return devno;
}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* set board model dt prop */
+ fdt_setprop_string(blob, 0, "board", gsc_get_model());
+
+ return 0;
+}
diff --git a/board/gateworks/venice/lpddr4_timing.c b/board/gateworks/venice/lpddr4_timing.c
index 47e93e1236..f362d9741c 100644
--- a/board/gateworks/venice/lpddr4_timing.c
+++ b/board/gateworks/venice/lpddr4_timing.c
@@ -2503,3 +2503,519 @@ struct dram_timing_info dram_timing_4gb = {
.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
.fsp_table = { 3000, 400, 100, },
};
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_2gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x2 },
+ { 0x110a3, 0x3 },
+ { 0x110a4, 0x4 },
+ { 0x110a5, 0x5 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x5 },
+ { 0x130a3, 0x2 },
+ { 0x130a4, 0x3 },
+ { 0x130a5, 0x4 },
+ { 0x130a6, 0x7 },
+ { 0x130a7, 0x6 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_2gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_2gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_2gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_2gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg_2gb[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg_2gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_2gb),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg_2gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_2gb),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg_2gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_2gb),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg_2gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_2gb),
+ },
+};
+
+/* lpddr4 timing config params */
+struct dram_timing_info dram_timing_2gb = {
+ .ddrc_cfg = lpddr4_ddrc_cfg_2gb,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_2gb),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg_2gb,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_2gb),
+ .fsp_msg = lpddr4_dram_fsp_msg_2gb,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_2gb),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h
index 94445f86a4..b73d067f7d 100644
--- a/board/gateworks/venice/lpddr4_timing.h
+++ b/board/gateworks/venice/lpddr4_timing.h
@@ -7,6 +7,7 @@
#define __LPDDR4_TIMING_H__
extern struct dram_timing_info dram_timing_1gb;
+extern struct dram_timing_info dram_timing_2gb;
extern struct dram_timing_info dram_timing_4gb;
#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 8c357757c1..b819c6846d 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -44,6 +44,9 @@ static void spl_dram_init(int size)
case 1:
dram_timing = &dram_timing_1gb;
break;
+ case 2:
+ dram_timing = &dram_timing_2gb;
+ break;
case 4:
dram_timing = &dram_timing_4gb;
break;
@@ -116,7 +119,7 @@ static int power_init_board(void)
if ((!strncmp(model, "GW71", 4)) ||
(!strncmp(model, "GW72", 4)) ||
(!strncmp(model, "GW73", 4))) {
- ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a20000", &bus);
+ ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
if (ret) {
printf("PMIC : failed I2C1 probe: %d\n", ret);
return ret;
@@ -133,8 +136,12 @@ static int power_init_board(void)
BIT(7) | MP5416_VSET_SW3_SVAL(920000));
}
- else if (!strncmp(model, "GW7901", 6)) {
- ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a30000", &bus);
+ else if ((!strncmp(model, "GW7901", 6)) ||
+ (!strncmp(model, "GW7902", 6))) {
+ if (!strncmp(model, "GW7901", 6))
+ ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
+ else
+ ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
if (ret) {
printf("PMIC : failed I2C2 probe: %d\n", ret);
return ret;
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-02 22:19:28 +0000